Struck SIS3800 User manual

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SIS Documentation SIS3800
Scaler/Counter
Page 1 of 39
SIS3800
VME Scaler/Counter
User Manual
SIS GmbH
Harksheider Str.102A
22399 Hamburg
Germany
Phone: ++49 (0) 40 60 87 305 0
Fax: ++49 (0) 40 60 87 305 20
email: [email protected]
http://www.struck.de
Version: 1.21 as of 20.01.04
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SIS Documentation SIS3800
Scaler/Counter
Page 2 of 39
Revision Table:
Revision Date Modification
1.1 18.09.98 Generation
1.13 29.01.99 introduction of revision table
LEMO control/flat cable counter front panel included
1.20 10.11.99 Firmware Version 3.0
1.21 20.01.04 Firmware Version 5.0 bug fix BLT readout
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SIS Documentation SIS3800
Scaler/Counter
Page 3 of 39
1 Table of contents
1 Table of contents .............................................................................................................................................3
2 Introduction.....................................................................................................................................................5
3 Technical Properties/Features..........................................................................................................................6
3.1 Board Layout...........................................................................................................................................6
3.2 Counter Design and Modus Operandi .....................................................................................................7
3.3 Count Enable Logic.................................................................................................................................8
3.4 Clear Logic..............................................................................................................................................8
4 Getting Started.................................................................................................................................................9
4.1 Factory Default Settings..........................................................................................................................9
4.1.1 Adressing.........................................................................................................................................9
4.1.2 System Reset Behaviour..................................................................................................................9
5 Firmware Selection..........................................................................................................................................9
5.1 Examples ...............................................................................................................................................10
6 Front Panel LEDs ..........................................................................................................................................11
7 VME addressing............................................................................................................................................12
7.1 Address Space .......................................................................................................................................12
7.2 Base Address.........................................................................................................................................12
7.2.1 VME..............................................................................................................................................12
7.2.2 VIPA/VME64x..............................................................................................................................12
7.3 Address Map..........................................................................................................................................13
8 Register Description......................................................................................................................................14
8.1 Status Register (0x0) .............................................................................................................................14
8.2 Control Register (0x0)...........................................................................................................................15
8.3 Module Identification and IRQ control register (0x4)...........................................................................16
8.4 Count disable register 0xC.....................................................................................................................17
8.5 Overflow registers 0x380, 0x3A0, 0x3C0, 0x 3E0................................................................................17
8.6 Broadcast Addressing............................................................................................................................17
9 VME Interrupts..............................................................................................................................................19
10 Data Format...............................................................................................................................................20
10.1 D16........................................................................................................................................................20
10.2 D32........................................................................................................................................................20
11 Readout Schemes.......................................................................................................................................20
11.1 Read Shadow Register...........................................................................................................................20
11.2 Read and Clear all Counters..................................................................................................................20
11.3 Read Counter.........................................................................................................................................20
11.4 Special behaviour of Firmware Version 3.............................................................................................20
12 Input Configuration ...................................................................................................................................21
12.1 ECL .......................................................................................................................................................21
12.2 NIM.......................................................................................................................................................22
12.3 TTL........................................................................................................................................................23
12.3.1 TTL/LEMO ...................................................................................................................................23
12.3.2 TTL/Flat Cable..............................................................................................................................23
13 Connector Specification ............................................................................................................................23
14 Control Input Modes..................................................................................................................................24
14.1 Version 1 ...............................................................................................................................................24
14.2 Version 2 and 3......................................................................................................................................24
15 Signal Specification...................................................................................................................................25
15.1 Control Signals......................................................................................................................................25
15.2 Inputs.....................................................................................................................................................25
16 Operating Conditions.................................................................................................................................25
16.1 Power Consumption/Voltage requirement.............................................................................................25
16.2 Cooling..................................................................................................................................................25
16.3 Insertion/Removal .................................................................................................................................25
17 Test............................................................................................................................................................26
17.1 LED (selftest) ........................................................................................................................................26
17.2 Internal pulser tests................................................................................................................................26
17.2.1 Single Pulse ...................................................................................................................................26
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SIS Documentation SIS3800
Scaler/Counter
Page 4 of 39
17.2.2 25 MHz Pulser...............................................................................................................................26
17.3 Reference pulser channel 1....................................................................................................................26
17.4 Signal-Input Priority..............................................................................................................................26
18 Software Support.......................................................................................................................................27
18.1 Contents of the included Floppy............................................................................................................27
19 Appendix...................................................................................................................................................28
19.1 Address Modifier Overview..................................................................................................................28
19.2 Front Panel Layout ................................................................................................................................29
19.3 Flat cable Input/Output Pin Assignments..............................................................................................30
19.3.1 ECL................................................................................................................................................30
19.3.2 TTL................................................................................................................................................31
19.4 List of Jumpers......................................................................................................................................32
19.5 Jumper and rotary switch locations .......................................................................................................32
19.5.1 Addressing mode and base address selection ................................................................................32
19.5.2 J500 (Bootfile Selection) and J520 (SYSRESET Behaviour) .......................................................33
19.6 Board Layout.........................................................................................................................................34
19.7 FLASHPROM Versions........................................................................................................................35
19.8 Row d and z Pin Assignments...............................................................................................................36
19.9 Geographical Address Pin Assignments................................................................................................37
19.10 Additional Information on VME .......................................................................................................37
20 Index..........................................................................................................................................................38
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SIS Documentation SIS3800
Scaler/Counter
Page 5 of 39
2 Introduction
The SIS3800 is one of the classic VME counter/scaler implementations on the base of the
SIS360x/38xx printed circuit board. The unit has 32 counter channels and a maximum
counting frequency of 200 MHz (ECL and NIM) 100 MHz (TTL) respective. As all boards of
the family it is of single slot double Eurocard form factor and available with flat cable
connectors for ECL and TLL levels and LEMO connectors for NIM and TTL levels.
The SIS360x/38xx card is a flexible concept to implement a variety of latch and counter
firmware designs. The flexibility is based on two to six Xilinx FPGAs in conjunction with a
FLASHPROM from which the firmware files are loaded into the FPGAs. Depending on the
stuffing options of the printed circuit board, the user has the possibility to cover several
purposes with the same card, hence the manual is a combination of firmware and hardware
description .
All cards of the family are equipped with the 5 row VME64x VME connectors, a side cover
and EMC front panel, as well as the VIPA LED set. For users with VME64xP subracks VIPA
extractor handles can be installed. The base board is prepared for VIPA style addressing, the
current first version of the SIS3800 firmware does not feature VIPA modes yet however.
As we are aware, that no manual is perfect, we appreciate your feedback and will try to
incorporate proposed changes and corrections as quickly as possible. The most recent version
of this manual can be obtained by email from [email protected], the revision dates are online
under http://www.struck.de/manuals.htm. A list of available firmware designs can be
retrieved from http://www.struck.de/sis3638firm.htm
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SIS Documentation SIS3800
Scaler/Counter
Page 6 of 39
3 Technical Properties/Features
The SIS3800 is rather a firmware design in combination with given board stuffing options,
than a name for the board (this is the reason, why the modules are named SIS360x/38xx on
the front panel and the distinction of the units is made by the module identifier register). The
firmware makes use of part of the possibilites of the SIS360x/38xx PCB, if the SIS3800 or
other firmware designs of the family come close to what you need, but something is missing,
a custom firmware design may be an option to consider.
Find below a list of key features of the SIS3800.
•32 channels
•200 MHz counting rate (ECL and NIM), 100 MHz for TTL
•32-bit channel depth
•NIM/TTL/ECL versions
•flat cable (TTL/ECL) and LEMO (TTL/NIM) versions
•Shadow register
•Read on the fly
•A16/A24/A32 D16/D32/BLT32 (CBLT32 prepared)
•Base address settable via 5 rotary switches (A32-A12) and one jumper (A11)
•VME interrupt capability
•VIPA geographical addressing prepared
•VIPA LED set
•Reference Pulser Capability
•Up to eight firmware files
•single supply (+5 V)
3.1 Board Layout
Xilinx FPGAs are the working horses of the SIS360x/38xx board series. The counter (prescaler,
latch, ...) logic is implemented in one to four chips, each chip handles eight front end channels.
The VME interface and the input and output control logic reside in two Xilinx chips also. The
actual firmware is loaded into the FPGAs upon power up from a FLASHPROM under jumper
control. The user can select among up to eight different boot files by the means of a 3-bit jumper
array. The counter and control inputs can be factory configured for ECL, NIM and TTL levels, on
the control outputs the same levels are the available as options. The standard SIS3800 version 1
design has no outputs implemented. The front panel is available as flat cable (ECL and TTL) or
LEMO (NIM and TTL) version. The board layout is illustrated with the block diagram below:
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SIS Documentation SIS3800
Scaler/Counter
Page 7 of 39
Control
XILINX
Counter
XILINX
VME
Interface
XILINX
Level Adaption
Driver/Receiver
Level Adaption
Driver/Receiver
Level Adaption
Driver/Receiver
Level Adaption
Driver/Receiver
VME Bus
4
4
4
4
Counter
XILINX
Level Adaption
Driver/Receiver
Level Adaption
Driver/Receiver
4
4
FLASH
PROM
File
Selection
Counter
XILINX
Level Adaption
Driver/Receiver
Level Adaption
Driver/Receiver
4
4
Counter
XILINX
Level Adaption
Driver/Receiver
Level Adaption
Driver/Receiver
4
4
SIS3800 Block Diagram
3.2 Counter Design and Modus Operandi
The counters are implemented in XILINX FPGAs. One of the counter FPGAs holds 8 32-bit
deep counter channels. The actual scaler contents are passed to the VME bus via a shadow
register. The scaler data have to be copied into the shadow register before readout via a
software command or a front panel hardware pulse. This can take place in parallel to the
acquisition of counts, what is called read on the fly. On a read on the fly the status of the
lowest 6 bits may be not accurate, i.e. the counter readout value is accurate modulo 64. (read
on the fly readout accuracy down to one count can be achieved with the SIS3801 multiscaler).
No pulses are missed during a read on the fly, i.e. the frontend continues counting. A diagram
of the setup is shown in the figure below. The different readout schemes are addressed in the
key register section.
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SIS Documentation SIS3800
Scaler/Counter
Page 8 of 39
Scaler Channel
Shadow
Register
Input
VME Interface
Control
VME Bus
Clock
Shadow
Clock
Shadow
External
VME Clock Shadow
Latch
3.3 Count Enable Logic
A channel acquires input or test counts, if the selective count enable and the global count
enable conditions are true. Via the test enable toggle bits in the control register the input of
the counter is switched to test pulses or front panel signals.
Scaler Channel N
Enable Scaler
AND
Count Enable
Selective Disable
Control Input Disable
MUX
MUX
OR
25 MHz reference (channel 1 only)
Input N
25 MHz test pulses
Single Test Pulse
External Test Pulse
3.4 Clear Logic
The contents of the counters can be cleared via VME access or a front panel pulse. The four
possible clear sources are ored as shown in the diagram below.
Scaler Channel N
VME Selective Clear Channel N
VME Clear All
OR
External Clear
Clear
Clear after VME read
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SIS Documentation SIS3800
Scaler/Counter
Page 9 of 39
4 Getting Started
The minimum setup to operate the SIS3800 requires the following steps:
•Check the proper firmware design is selected (should be design zero, i.e. all jumpers of
jumper array J500 set.
•Select the VME base address for the desired addressing mode
•Select the VME SYSRESET behaviour via J520
•turn the VME crate power off
•install the scaler in the VME crate
•connect your signals to the counter
•turn crate power back on
•set global count enable via key address 0x28
•read all counters with clock shadow register via block transfer from start address 0x280
(read) or 0x300 (read and clear) or subsequent single word reads.
A good way of checking first time communication with the SIS3800 consists of switching on
the user LED by a write to the control register at offset address 0x0 with data word 0x1 (the
LED can be switched back off by writing 0x1000 to the control register)..
4.1 Factory Default Settings
4.1.1 Adressing
SIS3800 boards are shipped with the En_A32, the En_A24 and the En_A16 jumpers installed
and the rotary switches set to:
Switch SW_A32U SW_A32L SW_A24U SW_A24L SW_A16 J A_11 Bits 7-4 Bits 3-0
Setting 3 8 3 8 3 8 0 0
Jumper A_11 is open (bit 11 set).
Hence the unit will respond to the following base addresses:
Mode Base address
A32 0x38383800
A24 0x383800
A16 0x3800
Firmware Design
Design 1 of the FLASHPROM is selected (lowest jumper of jumper array J500 open, the
others set).
4.1.2 System Reset Behaviour
J520 is set, i.e. the SIS3800 is reset upon VME reset.
5 Firmware Selection
The FLASH PROM of a SIS360x/38xx board can contain several boot files. A list of
available FLASHPROM versions can be found on our web site http://www.struck.de in the
manuals page. If your FLASHPROM has more than one firmware design, you can select the
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SIS Documentation SIS3800
Scaler/Counter
Page 10 of 39
desired firmware via the firmware selection jumper array J500 . You have to make sure, that
the input/output configuration and FIFO configuration of your board are in compliance with
the requirements of the selected firmware design (a base board without FIFO can not be
operated as multi channel scaler e.g.). A total of 8 boot files from the FLASHPROM can be
selected via the three bits of the jumper array. The array is located towards the rear of the card
between the VME P1 and P2 connectors. The lowest bit sits towards the bottom of the card, a
closed jumper represents a zero, an open jumper a one.
5.1 Examples
The figures below show jumper array 500 with the soldering side of the board facing the user
and the VME connectors pointing to the right hand side.
Bootfile 0 selected
With all jumpers closed boot file 0 is selected
Bootfile 3 selected
With the lowest two jumpers open bit 0 and bit 1 are set to 1 and hence boot file 3 is selected
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SIS Documentation SIS3800
Scaler/Counter
Page 11 of 39
6 Front Panel LEDs
The SIS3800 has 8 front panel LEDs to visualise part of the units status. Three LEDs
according to the VME64xP standard (Power, Access and Ready) plus 5 additional LEDs
(VME user LED, Clear, Overflow, Scaler enable and VIPA user LED).
Designation LED Color Function
A Access yellow Signals VME access to the unit
P Power red Flags presence of VME power
R Ready green Signals configured logic
U VME user LED green To be switched on/off under user program control
CLR Clear yellow Signals soft or hardware clear
OVL Overflow red Signals Overlow in one or more channels
S Scaler Enable green Signals one or more enabled channels
VU VIPA user LED green for future use
The LED locations are shown in the portion of the front panel drawing below.
The VME Access, the Clear and the Scaler enable LED are monostable (i.e. the duration of
the on phase is stretched for better visibility), the other LEDs reflect the current status.
An LED test cycle is performed upon power up (refer to the chapter 17.1).
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SIS Documentation SIS3800
Scaler/Counter
Page 12 of 39
7 VME addressing
7.1 Address Space
As bit 11 is the lowest settable bit on the 360x/38xx board, an address space of 2 Kbytes
(Offset plus 0x000 to 0x7ff) is occupied by the module.
7.2 Base Address
7.2.1 VME
The VME addressing mode (A16/A24/A32) is selected via the jumpers EN_A16, EN_A24
and EN_A32.The mode is selected by closing the corresponding jumper, it is possible to
enable two or all three addressing modes simultaneously.
The base address is set via the five rotary switches SW_A32U, SW_A32L, SW_A24U,
SW_A24L and SW_A16 and the jumper J_A11. The table below lists the switches and
jumpers and their corresponding address bits.
Switch/Jumper Affected Bits
SW_A32U 31-28
SW_A32L 27-24
SW_A24U 23-20
SW_A24L 19-16
SW_A16 15-12
J_A11 11
In the table below you can see, which jumpers and switches are used for address decoding in
the three different addressing modes (fields marked with an x are used).
SW_A32U SW_A32L SW_A24U SW_A24L SW_A16 J_A11
A32xxxxxx
A24 x x x x
A16 x x
Note: J_A11 closed represents a 0, J_A11 open a one
7.2.2 VIPA/VME64x
As the VME64x and the VME64xP (VIPA) standard are not yet standards to refer to and to
declare conformity with, addressing modes (like geographical addressing e.g.) according to
these standards are prepared but not yet implemented in the current firmware revisions.
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SIS Documentation SIS3800
Scaler/Counter
Page 13 of 39
7.3 Address Map
The SIS360x/38xx boards are operated via VME registers, VME key addresses and the FIFO
(where installed). The following table gives an overview on all SIS3800 addresses and their
offset from the base address, a closer description of the registers and their function is given in
the following subsections.
Offset Key Access Type Function
0x000 R/W D16/D32 Control and Status register
0x004 R/W D16/D32 Module Identification and IRQ control register
0x00C W D16/D32 Selective count disable register
0x020 KA W D16/D32 clear all counters and overflow bits
0x024 KA W D16/D32 clock shadow register
0x028 KA W D16/D32 global count enable
0x02C KA W D16/D32 global count disable
0x030 KA W D16/D32 Broadcast; clear all counters and overflow bits
0x034 KA W D16/D32 Broadcast; clock shadow register
0x038 KA W D16/D32 Broadcast; global count enable
0x03C KA W D16/D32 Broadcast; global count disable
0x040 KA W D16/D32 clear counter group and overflow channel 1-8
0x044 KA W D16/D32 clear counter group and overflow channel 9-16
0x048 KA W D16/D32 clear counter group and overflow channel 17-24
0x04C KA W D16/D32 clear counter group and overflow channel 25-32
0x050 KA W D16/D32 enable reference pulser channel 1
0x054 KA W D16/D32 disable reference pulser chanel 1
0x060 KA W D16/D32 reset register (global reset)
0x068 KA W D16/D32 Test pulse (generate a single pulse)
0x100-
0x17C KA W D16/D32 clear counter N and its overflow bit
0x180-
0x1FC KA W D16/D32 clear overflow bit of counter N
0x200-
0x27C R D16/D32/ BLT32 read shadow register (does not initiate clock shadow)
0x280-
0x2FC R D16/D32/ BLT32 read counter (initiates clock shadow also)
0x300-
0x37C R D16/D32/ BLT32 read and clear all counters
0x380 R D16/D32 Overflow register channel 1-8
0x3A0 R D16/D32 Overflow register channel 9-16
0x3C0 R D16/D32 Overflow register channel 17-24
0x3E0 R D16/D32 Overflow register channel 25-32
Note: D08 is not supported by the SIS38xx boards
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SIS Documentation SIS3800
Scaler/Counter
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8 Register Description
8.1 Status Register (0x0)
The status register reflects the current settings of most of the SIS3800 parameters in read
access, in write access it functions as the control register.
Bit Function
31 0
30 Status VME IRQ source 2 (test IRQ)
29 Status VME IRQ source 1 (ext. clock shadow)
28 Status VME IRQ source 0 (Overflow)
27 VME IRQ
26 internal VME IRQ
25 0
24 0
23 0
22 Status VME IRQ Enable Bit Source 2
21 Status VME IRQ Enable Bit Source 1
20 Status VME IRQ Enable Bit Source 0
19 0
18 0
17 0
16 reserved (read back as 0 at power up)
15 Global Count Enable
14 General Overflow Bit
13 Status enable reference pulser channel 1
12 0
11 0
10 0
90
80
7 Status broadcast mode handshake controller
6 Status broadcast mode
5 Status input test mode
4 Status 25 MHz test pulses
3 Status input mode bit 1
2 Status input mode bit 0
1 Status IRQ source 2 for software IRQ testing
0 Status user LED
The reading of the status register after power up or key reset is 0x0 (see default settings of
control register).
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SIS Documentation SIS3800
Scaler/Counter
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8.2 Control Register (0x0)
The control register is in charge of the control of most of the basic properties of the SIS3800
board in write access. It is implemented via a selective J/K register, a specific function is
enabled by writing a 1 into the set/enable bit, the function is disabled by writing a 1 into the
clear/disable bit (which has a different location within the register). An undefined toggle
status will result from setting both the enable and disable bits for a specific function at the
same time.
On read access the same register represents the status register.
Bit Function
31 reserved
30 disable IRQ source 2 (*)
29 disable IRQ source 1 (*)
28 disable IRQ source 0 (*)
27 reserved
26 reserved
25 reserved
24 clear reserved bit
23 reserved
22 enable IRQ source 2
21 enable IRQ source 1
20 enable IRQ source 0
19 reserved
18 reserved
17 reserved
16 set reserved bit
15 disable broadcast mode handshale controller (*)
14 disable broadcast mode (*)
13 disable input test mode (*)
12 disable 25 MHz test pulses (*)
11 clear input mode bit 1 (*)
10 clear input mode bit 0 (*)
9 clear IRQ test source 2
8 switch off user LED (*)
7 enable handshake controller for broadcast mode
6 enable broadcast mode
5 enable input test mode
4 enable 25 MHz test pulses
3 set input mode bit 1
2 set input mode bit 0
1 set IRQ test (source 2)
0 switch on user LED
(*) denotes the default power up or key reset state
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SIS Documentation SIS3800
Scaler/Counter
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8.3 Module Identification and IRQ control register (0x4)
This register has two basic functions. The first is to give information on the active firmware
design. This function is implemented via the read only upper 20 bits of the register. Bits 16-
31 hold the four digits of the SIS module number (like 3800 or 3600 e.g.), bits 12-15 hold the
version number. The version number allows a distinction between different implementations
of the same module number, the SIS3801 for example has the 24-bit mode with user bits and
the straight 32-bit mode as versions.
Bit Read/Write access Function
31 read only Module Identification Bit 15
30 read only Module Identification Bit 14
29 read only Module Identification Bit 13
28 read only Module Identification Bit 12
Module Id Digit 3
27 Read only Module Identification Bit 11
26 read only Module Identification Bit 10
25 read only Module Identification Bit 9
24 read only Module Identification Bit 8
Module Id Digit 2
23 read only Module Identification Bit 7
22 read only Module Identification Bit 6
21 read only Module Identification Bit 5
20 read only Module Identification Bit 4
Module Id Digit 1
19 read only Module Identification Bit 3
18 read only Module Identification Bit 2
17 read only Module Identification Bit 1
16 read only Module Identification Bit 0
Module Id Digit 0
15 read only Version Bit 3
14 read only Version Bit 2
13 read only Version Bit 1
12 read only Version Bit 0
11 read/write VME IRQ Enable (0=IRQ disabled, 1=IRQ enabled)
10 read/write VME IRQ Level Bit 2
9 read/write VME IRQ Level Bit 1
8 read/write VME IRQ Level Bit 0
7 read/write IRQ Vector Bit 7; placed on D7 during VME IRQ ACK cycle
6 read/write IRQ Vector Bit 6; placed on D6 during VME IRQ ACK cycle
5 read/write IRQ Vector Bit 5; placed on D5 during VME IRQ ACK cycle
4 read/write IRQ Vector Bit 4; placed on D4 during VME IRQ ACK cycle
3 read/write IRQ Vector Bit 3; placed on D3 during VME IRQ ACK cycle
2 read/write IRQ Vector Bit 2; placed on D2 during VME IRQ ACK cycle
1 read/write IRQ Vector Bit 1; placed on D1 during VME IRQ ACK cycle
0 read/write IRQ Vector Bit 0; placed on D0 during VME IRQ ACK cycle
The second function of the register is interrupt control. The interrupter type of the SIS3800 is
D08(O) . Via bits 0-7 of the module identifier and interrupt control register you can define the
interrupt vector, which is placed on the VME bus during the interrupt acknowledge cycle. Bits
8 through 10 define the VME interrupt level, bit 11 is used to enable (bit set to 1) or disable
(bit set to 0) interrupting.
Module identification and version example:
The register for a SIS3801 in straight 32-bit mode (version 1) reads 0x38011nnn, for a
SIS3801 in 24-bit mode (version 2) it reads 0x38012nnn. (the status of the lower 3 nibbles is
denoted with n in the example).
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SIS Documentation SIS3800
Scaler/Counter
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8.4 Count disable register 0xC
The count disable register can be used to disable single channels or arbitrary groups of
channels. Note, that both the external (if used) and the internal conditions have to be in status
enable for the given channel.
The register is write only.
If bit N of the register is set, channel N+1 is disabled.
Example: If 0x5 is written to the count disable register, counting of channel 1 and 3 is
disabled.
8.5 Overflow registers 0x380, 0x3A0, 0x3C0, 0x 3E0
Each overflow register holds the overflow bit of eight counter channels (i.e. of one counter
XILINX) in its lowest eight bits.
Example: register 0x380 holds the overflow bits of channels 1-8 as shown in the table below.
Bit3130292827262524Bits23-1
Ch 8 Ch 7 Ch 6 Ch 5 Ch 4 Ch 3 Ch 2 Ch 1 undefined
8.6 Broadcast Addressing
Broadcast addressing is an efficient way to issue the same command to a number of modules.
It can be used in A24 and A32 mode on SIS360x/38xx boards. The higher address bits are
used to define the broadcast class, the distinction of the modules is done via the A16 rotary
switch and the A_11 jumper. If broadcast addressing is used, the A32_U, the A_32_L, the
A24_U and the A24_L rotary switches must have the same setting in A32 mode, in A24
mode the A24_U and A24_L setting must be the same on all participating units. One of the
participating units must be configured as broadcast handshake controller by setting bit 7 in the
units control register. All of the participating units must have set bit 6 (enable broadcast) in
the control register. The broadcast time jitter was measured to be less than 40 ns within a
VME crate, i.e. you have the possibility issue commands under software control with a
maximum uncertainty of 40 ns (like clear all counters), what sure is worse, than a hard wired
front panel clear, but is much better than a VME single cycle loop over a number of units. The
four broadcast commands are executed via the VME key addresses at offset 0x030 through
0x3C.
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SIS Documentation SIS3800
Scaler/Counter
Page 18 of 39
A32 Broadcast Example:
Let four SIS3800 participate by setting the A_32 jumper and setting the base address of the
units to:
Unit 1: 0x32001000
Unit 2: 0x32001800
Unit 3: 0x32002000
Unit 4: 0x32002800
Switch on enable broadcast by setting bit 6 in the control register of the four units.
Enable broadcast handshake controller on unit 4 by setting bit 7 of its control register.
An A232 write to address 0x32000034 will clock the shadow register on units 1 through 4.
A24 Broadcast Example:
Let three SIS3800 participate by setting the A_24 jumper and setting the base address of the
units to:
Unit 1: 0x541000
Unit 2: 0x542000
Unit 3: 0x543000
Switch on enable broadcast by setting bit 6 in the control register of the three units.
Enable broadcast handshake controller on unit 1 by setting bit 7 of its control register.
An A24 write to address 0x540030 will clear the counters on units 1 through 3.
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SIS Documentation SIS3800
Scaler/Counter
Page 19 of 39
9 VME Interrupts
Three VME interrupt sources are implemented in the SIS3800 firmware design:
•Overflow
•External Latch Shadow Input
•Test Interrupt
The interrupter is of type D8(O).
The interrupt logic is shown below. For VME interrupt generation the corresponding interrupt
source has to be enabled by setting the respective bit in the VME control register (disabling is
done with the sources J/K bit). Interrupt generation has to be enabled by setting bit 11 in the
IRQ and version register. The internal VME interrupt flag can be used to check on an IRQ
condition without actually making use of interrupts on the bus.
The VME interrupt level (1-7) are defined by bits 8 through 10 and the VME interrupt vector
(0-255) by bits 0 through 7 of the VME IRQ and version register.
In general an interrupt condition is cleared by disabling the corresponding interrupt, clearing
the interrupt condition (i.e. clear overflow) and enabling the IRQ again.
Note: In most cases your experiment may not require interrupt driven scaler readout,
but the interrupt capability of the SIS3800 provides a way to overcome the problem of
missing front panel inputs on most commercial VME CPUs.
AND
Enable 2
Test
AND
Enable 1
ext. Shadow
AND
Enable 0
Overflow
OR
AND
VME IRQ
VME_IRQ_ENABLE
INTERNAL_VME_IRQ
Source 2
Source 1
Source 0
Clear
CtrlReg
Bit1
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