Summit SMH4804 User manual

-48V Programmable Hot Swap Sequencing Power Controller
© SUMMIT Microelectronics, Inc. 2005 • 1717 Fox Drive • San Jose CA 95131 • Phone [phone] • Fax [phone] • www.summitmicro.com
2050 3.8 10/13/05 1
SMH4804
–
FEATURES AND APPLICATIONS
Features:
• Soft Starts Main Power Supply on Card Insertion or
System Power Up
• In-Rush Current Limiting
• Master Enable to Allow System Control of Power Up or
Down
• Programmable Independent Control of up to 4 DC/DC
Converters via 4 Power Good Signals, PG[4:1]#
• Highly Programmable Circuit Breaker Level and Mode
– Programmable Quick-Trip™ Value, Current
Limiting, Duty Cycle Times, and Over-Current Filter
• Programmable Host Voltage Fault Monitoring
– Programmable UV/OV Filter and UV Hysteresis
• Programmable Fault Mode: Latched or Duty Cycle
• Internal Shunt Regulator Allows for a Wide Supply
Range (typically -32 to -72 Volts)
•I
2C 2-Wire Serial Bus Interface for Programming,
Power On/Off and Operational Status
Applications:
• Telecom Hot-Swap Card
• Distributed Power Architectures
• Power-on LAN, IEEE 802.3
–
INTRODUCTION
The SMH4804 is a user-programmable -48V power supply
controller designed to control the hot-swapping of plug-in
cards and to sequence supplies in a distributed power
environment. The SMH4804 drives an external power
MOSFET switch that connects the bus side supply to the
card side load and controls in-rush current while providing
both current regulation and over-current protection. When
the source and drain voltages of the external MOSFET are
within specification, the SMH4804 asserts four PG[4:1]#
power-good logic outputs either simultaneously or
sequenced at programmable intervals to enable DC-DC
converters to distribute card side power.
Additional features of the device include: UV and OV
monitor, master enable or temperature sense input (EN/
TS), 2.5V and 5V reference outputs for expanding monitor
functions, two Pin-Detect enable inputs (PD1# and PD2#)
for card insertion verification, and duty-cycle or latched
over-current protection modes. All features are
programmed in nonvolatile registers through the I2C
interface which is simplified with the SMX3200 interface
adapter and Windows GUI software available from Summit
Microelectronics. Engineers can program the device
directly in-circuit with units of voltage, current and time,
allowing fast design cycles.
–
SIMPLIFIED APPLICATION DRAWING
Figure 1. SMH4804 Simplified Application Diagram
-48V RTN (0V) RD
10K, 1/2W
D1 Dual
MMBD1401 3
2
20
24
(Short Pins)
R2
267K, 1%
R3
10K, 1%
-48V1
R4
10K, 1%
PD2#
PD1#
UV
OV
D2
D3
-48V1
-48V2
C1
100nF
R5
0.02
C2
100nF
R7
10
R8
1K
C3
10nF
R9
100K C4
100nF
Q1
IRF1310N
13 4448
17, 18
D4
MMBD1401
Note 1
PG#1
PG#2
PG#3
PG#4
SMH4804
VDD
5VREF
2.5VREF
FS#
A0 A1 A2
SDA
SCL
36
37
34
40
VSS CBSense VGate DrainSense
I2C
7
8
7
8
7
8
7
8
3
2
1
3
2
1
3
2
1
3
2
1
5.0V
3.3V
2.5V
1.8V
Vin+
On/Off
Vin-
Vout+
Vout-
Vin+
On/Off
Vin-
Vout+
Vout-
Vin+
On/Off
Vin-
Vout+
Vout-
Vin+
On/Off
Vin-
Vout+
Vout-
Note 1: Safety isolation interface may be required. See Apps Section.
42 26 28 25 46 22 10 1215
-48V2
-48V
470
R1
R6
D5
D6

Functional Block Diagram SMH4804
2 2050 3.8 10/13/05 Summit Microelectronics
–
FUNCTIONAL BLOCK DIAGRAM
Figure 2. SMH4804 Block Diagram
PROGRAMM-
ABLE
DELAY
PROGRAMM-
ABLE
DELAY
PROGRAMM-
ABLE
DELAY
PROGRAMM-
ABLE
DELAY
+
–
+
–
+
–
Programmable
Quick Response
Ref. Voltage
50mV
FAULT
LATCH
AND
DUTY
CYCLE
TIMER
P. D.
FILTER
+
–
+
–
5V 2.5V
12V
VGATE
SENSE
+
–
VDD
VSS
MODE
RESET#
CBSENSE
EN/TS
PD1#
PD2#
UV
OV
PG3#
ENPGA ENPGB
2.5VREF
PG2#
PG1#
DRAIN
SENSE
VGATE
FAULT#
5.0VREF
12VREF
50kΩ
200kΩ
50kΩ
PROG
REF
SDA
SCL
PROGRAMMING
STEERING
LOGIC
ENPGC
DEVICE
ADDRESS
DECODE
A2
A1
A0
PG4#
10µA
2050 BD
50kΩ
50kΩ
50kΩ
50kΩ
50kΩ
Programmable
Shutdown
Timer
FS#
Three
@ 50kΩ
50kΩ50kΩ
OV/UV
FILTER
P. D.
FILTER
27
24
26
25
19
18
7
3
28
4
5
6
1
15
17
14
13
16
8
9
2
12
10
11 20 23 22 21

SMH4804 Functional Description
Summit Microelectronics 2050 3.8 10/13/05 3
–\
FUNCTIONAL DESCRIPTION
The SMH4804 integrated hot swap power controller
operates within a wide supply range, typically -32 to -72
volts, and generates the signals necessary to drive isolated-
output DC/DC converters. The general start-up procedure is
as follows:
• A physical connection must first be made with the
chassis to discharge any electrostatic voltage potentials
when a typical add-in board is inserted into the powered
backplane.
• The board then contacts the long pins on the backplane
that provide power and ground.
• As soon as power is applied the device starts up, but
does not immediately apply power to the output load.
• Under-voltage and over-voltage circuits inside the
controller verify that the input voltage is within a user-
specified range.
• The SMH4804 senses the PD1# and PD2# pin
detection signals to indicate the card is seated properly.
These requirements must be met for a Pin Detect Delay
period of tPDD. Once this time has elapsed, the hot-swap
controller enables VGATE to turn on the external power
MOSFET switch. The VGATE output is current limited to
IVGATE, allowing the slew rate to be easily modified using
external passive components. During the controlled turn-on
period the VDS of the MOSFET is monitored by the drain
sense input. When DRAIN SENSE drops below 2.5V, and
VGATE rises above VDD – VGT, the SMH4804 asserts the
PG1# through PG4# power good outputs to enable the DC/
DC controllers. The ENPGA, ENPGB, and ENPGC Power
Good Enable inputs may be used to activate or deactivate
specific output loads.
Steady-state operation is maintained as long as all
conditions are normal. Any of the following events may
cause the device to disable the DC/DC controllers by
shutting down the power MOSFET:
• an under-voltage or over-voltage condition on the host
power supply.
• an over-current event detected on the CBSENSE input
• a failure of the power MOSFET sensed via the DRAIN
SENSE pin.
• the PD1#/PD2# pin detect signals becoming invalid.
• the master enable (EN/TS) falls below 2.5V.
• the FS# input is driven low by events on the secondary
side of the DC/DC controllers.
The SMH4804 may be configured so that after any of these
events occurs, the VGATE output shuts off and either
latches into an off state, or recycles power after a cooling
down period, tCYC.
Powering VDD
The SMH4804 contains an internal shunt regulator on the
VDD pin that prevents the voltage from exceeding 12V. It is
necessary to use a dropper resistor (RD) between the host
power supply and the VDD pin in order to limit current into the
device and prevent possible damage. The dropper resistor
allows the device to operate across a wide range of system
supply voltages, typically -32 V to -72V, and also helps
protect the device against common-mode power surges.
Refer to the Applications Section for help on calculating the
RDresistance value.
Hot-Swap Verification
There are several enabling inputs that allow the host to
control the SMH4804. The Pin Detect signals (PD1# and
PD2#) are two active low enables that are generally used to
indicate that the add-in circuit card is properly seated.
These inputs must be held low for a pin-detect delay period
of tPDD before a power-up sequence may be initiated. This is
typically done by clamping the inputs to VSS through the
implementation of an ejector switch, or alternatively through
the use of staggered pins at the card-cage interface. The pin
detect delay (tPDD) timing parameter is controlled by bits 1:0
of register 9. Refer to Register 9 - Address 1001 on page 38
for more information.
Two shorter pins, arranged at opposite ends of the
connector, force the card to be fully seated before both pin
detects are enabled. Care must be taken not to exceed the
maximum voltage rating of these pins during the insertion
process. Refer to details in the Applications Section for
proper circuit implementation. Note that the PD1# and PD2#
inputs are enabled or disabled using bit 0 of Register 3.
Refer to Register 3 - Address 0011 on page 32 for more
information.
The EN/TS input provides an active high comparator input
that may be used as a master enable or temperature sense
input. This input signal must exceed 2.5V (nominal) for
proper operation. Refer to the Pin Descriptions on page 10
for more information.
Under-/Over-Voltage Sensing
The Under-Voltage (UV) and Over-Voltage (OV) inputs
provide a set of comparators that act in conjunction with an
external resistive divider ladder to sense whether or not the
host supply voltage is within the user-defined limits. The
power-up sequence is initiated when the input to the UV pin
rises above 2.5V and the input to the OV pin falls below

Functional Description SMH4804
4 2050 3.8 10/13/05 Summit Microelectronics
2.5V for a period of at least tPDD (Pin Detect Delay time).
The tPDD filter helps prevent spurious start-up sequences
while the card is being inserted. If UV falls below 2.5V or OV
rises above 2.5V, the PG[4:1]# and VGATE outputs are
disabled immediately.
Under-/Over-Voltage Filtering
The SMH4804 can be configured so that an out-of-
tolerance condition on UV/OV does not shut off the output
immediately. Instead, a filter delay may be inserted so that
only sustained under-voltage or over-voltage conditions can
shut off the output. An out-of-tolerance condition on UV/OV
for longer than the filter delay time (tUOFLTR in Figure 3)
causes the VGATE and PG[4:1]# outputs to shut off when
the UV/OV filter option is enabled using bits 2:1 of Register
4. The under-/over-voltage filtering feature is disabled (bits
2:1 = 00) in the default configuration. Refer to Register 4 -
Address 0100 on page 33 for more information on the filter
delay options. The UV and OV filters are enabled and
disabled by programming bits 3 and 2 of Register 6
respectively. Refer to Register 6 - Address 0110 on page 36
for more information. Note that the delay values in Register
4 are only valid if the corresponding over or under voltage
filtering is enabled using bits 3:2 of Register 6.
Figure 3 shows the timing for the under-/over-voltage filter.
Figure 3. Under-/Over-Voltage Filter Timing
Under-/Over-Voltage Latching
An additional option for an out-of-tolerance condition on UV/
OV is to latch the VGATE and PG[4:1]# outputs off such that
a return to normal UV/OV operation does not turn them back
on. In this case the FAULT# output is asserted.
Under-Voltage Hysteresis
The Under-Voltage comparator input may be configured
with a programmable level of hysteresis using Register 7.
The falling voltage compare level may be set in steps of
62.5mV below 2.5V. The rising voltage compare level is
fixed at 2.5V. The default under-voltage hysteresis level is
set to 62.5mV. In default conditions the SMH4804 is not in
an under-voltage state once the UV voltage rises above
2.5V; and after that an under-voltage occurrence is not
recognized until the UV voltage falls below 2.4375V (2.5V –
62.5mV).
Soft Start Slew Rate Control
Once all of the preconditions for powering up the DC/DC
controllers have been met as explained in the previous
sections, the SMH4804 provides a means to soft start the
external power MOSFET. It is important to limit in-rush
current to prevent damage to the add-in card or disruptions
to the host power supply. For example, charging the filter
capacitance too quickly (normally required at the input of the
DC/DC controllers) may generate very high current. The
VGATE output of the SMH4804 is current limited to IVGATE,
allowing the slew rate to be easily modified using external
passive components. The slew rate may be found by
dividing IVGATE by the gate-to-drain capacitance placed on
the external FET.
Load Control — Sequencing the Secondary
Supplies
The PG1# through PG4# output pins are used to enable the
external DC/DC controllers. Once the card is inserted, the
SMH4804 samples the PD1# and PD2# pin detect input
pins to determine if the card as been inserted properly. It
then monitors the state of the UV and OV input pins to
assure there is no under-voltage or over-voltage condition
present. Once these conditions are met, and the EN/TS pin
is greater than 2.5V, the SMH4804 asserts the VGATE
output to turn on the external MOSFET.
During the time it takes to turn the MOSFET on, the
SMH4804 monitors the system for an over-current condition
via the CBSENSE input pin. In addition, the device internally
monitors the voltage level on the VGATE output pin. This is
shown by the ‘VGATE Sense’ block in Figure 2.
Once power has been ramped to the DC/DC controllers, two
conditions must be met before the PG[4:1]# outputs can be
enabled:
• the DRAIN SENSE input voltage must be below 2.5V.
• the VGATE voltage must be greater than VDD – VGT,
where VGT is the gate threshold.
The DRAIN SENSE input helps ensure that the power
MOSFET is not absorbing too much steady state power
from operating at a high VDS. This sensor remains active at
all times (except when current regulation is enabled). The
2050 Fig07
OV / UV
FAULT#
tUOFLTR
2.5V

SMH4804 Functional Description
Summit Microelectronics 2050 3.8 10/13/05 5
VGATE sensor makes sure that the power MOSFET is
operating well into its saturation region before allowing the
loads to be switched on. Once VGATE reaches VDD – VGT
this sensor is latched.
When the external MOSFET is properly switched on the
PG[4:1]# outputs may be enabled. Output PG1# is activated
first, followed by PG2# after a delay of tPGD, PG3# after
another tPGD delay, and PG4# after a final tPGD delay. The
delays built into the SMH4804 allow timed sequencing of
power to the loads. The delay times are programmable from
50µs to 160ms using bits 3:2 of Register 3 and bit 3 of
Register 9. Refer to Register 3 - Address 0011 on page 32
and Register 9 - Address 1001 on page 38 for more
information.
The ENPGA, ENPGB, and ENPGC input pins in Figure 5
are used to enabled the PG[4:1]# outputs. The ENPGA pin
controls the PG[4:2]# outputs. If ENPGA is deasserted by
external logic, the SMH4804 disables the PG[4:2]# outputs
and they enter the high-impedance state. The ENPGA input
must be asserted in order for PG[4:2]# to be driven by the
SMH4804.
The ENPGB pin controls the PG[4:3]# outputs. If ENPGB is
deasserted by external logic, the SMH4804 disables the
PG[4:3]# outputs and they enter the high-impedance state.
The ENPGB input must be asserted in order for PG[4:3]# to
be driven by the SMH4804.
The ENPGC pin controls the PG[4]# output. If ENPGC is
deasserted by external logic, the SMH4804 disables the
PG[4]# outputs and the output enters the high-impedance
state. The ENPGC input must be asserted in order for
PG[4]# to be driven by the SMH4804.
This cascaded control mechanism is useful for enabling
supplies that have dependencies based on the other
voltages in the system.
The PG[4:1]# outputs have a 12V withstand capability, so
high voltages must not be connected to these pins. Bipolar
transistors or opto-isolators can be used to boost the
withstand voltage to that of the host supply. Refer to
Figure 18 for connectivity information.
Figure 5 shows the relationship between the PG[4:1]# and
the ENPG[C:A] signals.
Figure 4. PG Output and ENPG Input Relationship
Forced Shutdown — Secondary Feedback
The Forced Shutdown signal (FS#) is an active low input
that provides a method of receiving feedback from the
secondary side of the DC/DC controllers. A built-in
shutdown timer allows the SMH4804 to ignore the state of
the FS# input until the timer period expires. The timer period
is defined in bits 2:0 of Register 5. The FS# input must be
driven high by the end of this timer period. A low level on this
input causes a Fault condition, driving the FAULT# pin low
and shutting off the VGATE and PG[4:1]# outputs.
The purpose of the shutdown timer is to allow enough time
for devices on the secondary side of the DC/DC controllers
to power up and stabilize. This feature allows supervisory
circuits such as an SMS44 to control the shutdown of the
primary side soft start circuit, even though the secondary
side initially has no power.
Alternatively, the FS# input can be programmed to act as a
fourth ENPG input controlling the PG1# output. This is
combined with an option to independently enable PG1#
with no affect on the other PG[4:2]# outputs, or it can be
programmed so PG1# is the enabling output for the other
outputs.
2050 Fig02 2.1
PG1#
PG2#
PG3#
PG4#
ENPGA
ENPGC
ENPGB
tPGD
tPGD
tPGD

Functional Description SMH4804
6 2050 3.8 10/13/05 Summit Microelectronics
Circuit Breaker Operation
The SMH4804 provides a number of circuit breaker
functions to protect against over-current conditions. A
sustained over-current event could damage the host supply
and/or the load circuitry. The board’s load current passes
through a series resistor (RS) connected between the
MOSFET source (which is tied to CBSENSE) and VSS. The
breaker trips whenever the voltage drop across RSis
greater than 50mV for more than tCBD (a programmable
filter delay ranging from 10µs to 500µs).
The circuit breaker cycle time is controlled via bit 0 of
Register 4.
Figure 5 shows the circuit breaker duty cycle operation with
RESET# high.
Figure 5. Circuit Breaker Duty Cycle Operation with
RESET# High
Figure 6 shows the behavior of VGATE and CBSENSE
immediately after RESET# is deasserted.
The circuit breaker cycle time can be programmed to a
value of either 2.5 seconds of 5 seconds depending on the
system configuration. Refer to bit 0 of Register 4 - Address
0100 on page 33 for more information on selecting the
circuit breaker cycle time.
Figure 6. Circuit Breaker Reset with RESET# Low
Quick-TripTM Circuit Breaker
The SMH4804 provides a Quick-Trip™ feature that causes
the circuit breaker to trip immediately if the voltage drop
across RSexceeds VQCB. The Quick-Trip level may be set to
60mV, 100mV (default), 200mV, or the feature may be
disabled. Refer to bits 1:0 of Register 2 - Address 0010 on
page 31 for more information.
Figure 7 shows the circuit breaker ‘Quick Trip’ response.In
this figure, the voltage rises above VQCB, causing VGATE to
be deasserted.
Figure 7. Circuit Breaker Quick Trip Response
Current Regulation
The current regulation mode is an optional feature that
provides a means to regulate current through the MOSFET
for a programmable period of time using bits 1:0 of Register
6.
CBSENSE
VGATE
T
CBD
T
CBD
T
CYC
2050 Fig03 1.0
50mV
2050 Fig04 2.1
CBSENSE
RESET#
VGATE
TCBD
TPDD
50mV
TCBRST
2050 Fig05 2.0
CBSENSE
VGATE
<TCBD
TFSTSHTDN
50mV
VQCB

SMH4804 Functional Description
Summit Microelectronics 2050 3.8 10/13/05 7
Current regulation is generally enabled in applications that
have switched dual (A and B) distributed power sources. By
using the current regulation function, unwarranted
shutdowns can be avoided if one of the dual supplies is
switched in when it is at a more negative potential the
currently operating supply.
When current regulation is selected by programming bits
1:0 of Register 6 to a binary value of 01 (5 ms), 10 (80 ms),
or 11 (160 ms), it is enabled during a soft-start (power on
period) and during normal operation after the PG[4:1]#
outputs are enabled. If the voltage monitored at the
CBSENSE pin is greater than 50mV, but less than 60mV,
the SMH4804 reduces the VGATE voltage in order to
maintain a CBSENSE potential less than 60mV, effectively
regulating the current through the MOSFET.
Figure 8 and Figure 9 illustrate the current regulation
function. The time period tPCR — selectable at 5, 80, or 160
ms — is the maximum time during which regulation is
enforced. If either VQCB or tPCR are exceeded the VGATE
and PG[4:1]# outputs are immediately deasserted.
However, if CBSENSE drops below 50mV before the timer
period ends, the timer is reset and VGATE resumes normal
operation (see Current Regulation With Recovery on page
7). If the Quick-Trip level is exceeded, the device bypasses
the current regulation timer and shuts down immediately.
The current regulation feature is disabled in the default
configuration.
Figure 8. Current Regulation With Recovery
Figure 9. Current Regulation Without Recovery
Nonvolatile Fault Latch
The SMH4804 provides an optional nonvolatile fault latch
(NVFL) circuit breaker feature. The nonvolatile fault latch
essentially provides a programmable fuse on the circuit
breaker. When the latch is enabled by setting bit 5 of
Register 5, the nonvolatile fault latch is set whenever the
circuit breaker trips. Once set, it cannot be reset by cycling
power or through the use of the RESET# pin.
Note: The device remains disabled until Register C is
reprogrammed. Refer to Register C - Address 1100 on page
38 for more information.
As long as the NVFL is set, the FAULT# output remains
asserted. The Nonvolatile Fault Latch feature is disabled in
the default configuration.
Resetting FAULT#
When the circuit breaker trips, the VGATE output is turned
off and the SMH4804 drives FAULT# low. There are two
methods to reset the circuit breaker which are selectable
with the MODE pin:
• When the MODE is held high or left floating, the circuit
breaker is in the duty-cycle mode. In this case the
breaker resets automatically after a time of tCYC.
• When the MODE pin is held low (or disabled in the
Configuration Register) FAULT# can be reset by
bringing RESET# low. The VGATE output attempts to
restart the MOSFET slew control circuitry tPDD after
bringing RESET# back high again.
In either case, cycling power to the board resets the circuit
breaker. If the over current condition still exists after the
MOSFET switches back on, the circuit breaker will re-trip.
2050 Fig06a
V
QCB
VGATE
t
CRD
50mV
0V
CBSENSE
t
PCR
12V
0V
<tPCR
2050 Fig06b
V
QCB
VGATE
50mV
0V
CBSENSE
t
PCR
12V
0V

Functional Description SMH4804
8 2050 3.8 10/13/05 Summit Microelectronics
Serial Interface
The SMT4804 uses the industry standard I2C, 2-wire serial
data interface. This interface provides access to the
configuration registers and the nonvolatile fault latch. The
interface has three address inputs (A0 - A2) allowing up to
eight devices on the same bus. This allows multiple devices
on the same board or multiple boards in a system to be
controlled with two signals; SDA and SCL.
Device configuration utilizing the Windows based SMT4804
graphical user interface (GUI) is highly recommended. The
software is available from the Summit website
(www.summitmicro.com). Using the GUI in conjunction with
this datasheet, simplifies the process of device prototyping
and the interaction of the various functional blocks. A
programming Dongle (SMX3200) is available from Summit
to communicate with the SMT4804. The Dongle connects
directly to the parallel port of a PC and programs the device
through a cable using the I2C bus protocol.

SMH4804 Package And Pin Configurations
Summit Microelectronics 2050 3.8 10/13/05 9
–
PACKAGE AND PIN CONFIGURATIONS
PACKAGE AND PIN CONFIGURATIONS
Figure 10. 28-Pin SOIC Package Pinout
Figure 11. 48-Pin TQFP Package Pinout1
1. All unnamed pins on this package are no-connects.
DRAIN SENSE
A0
VGATE
EN/TS
PD1#
PD2#
FAULT#
RESET#
MODE
SDA
SCL
CBSENSE
A1
VSS
VDD
PG4#
PG2#
PG1#
PG3#
ENPGA
ENPGB
ENPGC
2.5VREF
5VREF
FS#
OV
A2
UV
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
2050 SOIC PCon 2.1
28-Pin SOIC
EN/TS
PD1#
PD2#
FAULT#
RESET#
MODE
SDA
SCL
PG1#
PG3#
ENPGA
ENPGB
ENPGC
2.5VREF
5VREF
FS#
48-Pin TQFP
2050 TQFP PCon 2.1
CBSENSE
A1
VSS VSS
UV
A2
OV
VGATE A0 DRAIN SENSE VDD PG4# PG2#
1
2
3
4
5
6
7
8
9
10
11
12
13 14 15 16 17 18 19 20 21 22 23 24
36
35
34
33
32
31
30
29
28
27
26
25
48 47 46 45 44 43 42 41 40 39 38 37

Pin Descriptions SMH4804
10 2050 3.8 10/13/05 Summit Microelectronics
–
PIN DESCRIPTIONS
Table 1 provides the type, name, and description of the SMH4804 pins. Pin numbers are provided for both the
28-pin SOIC and 48-pin TQFP packages.
Pin Number
(28-Pin SOIC)
Pin Number
(48-Pin TQFP)
Pin Type
(I/O)
Pin Name Description
1 44 I DRAIN SENSE The DRAIN SENSE input monitors the voltage at the
drain of the external power MOSFET switch with
respect to VSS. An internal 10µA source pulls the
DRAIN SENSE signal towards the 5V reference level.
DRAIN SENSE must be held below 2.5V to enable the
PG[4:1] outputs.
2 46 I A0 The A0 input works in conjunction with the A1 and A2
inputs. Together these inputs are used for decoding
multiple devices on the serial bus. The A0 input has an
internal 50KΩpull-up to 5V.
3 48 O VGATE The VGATE output activates an external power
MOSFET switch. This signal supplies a constant
current output (100µA typical), which allows easy
adjustment of the MOSFET to turn on slew rate.
4 1 I EN/TS The Enable/Temperature Sense input is the master
enable input. If EN/TS is less than 2.5V, VGATE is
disabled. This pin has an internal 200KΩpull-up to 5V.
5 2 I PD1# The PD1# pin works in conjunction with the PD2# pin
to optionally enable VGATE and the PG[4:1]outputs
when they are at VSS. This pin has an internal 50KΩ
pull-up to 5V.
6 3 I PD2# The PD2# pin works in conjunction with the PD1# pin
to optionally enable VGATE and the PG[4:1]# outputs
when they are at VSS. This pin has an internal 50KΩ
pull-up to 5V.
7 5 O FAULT# FAULT# is an open-drain, active-low output that
indicates the fault status of the device.
8 7 I RESET# The RESET# pin is used to clear latched fault
conditions. When this pin is asserted, the VGATE and
PG[4:1]# outputs are disabled. Refer to the section on
Circuit Breaker Operation for more information. This
pin has an internal 50KΩpull-up to 5V.
9 9 I/O SDA SDA is the bidirectional serial data I/O port. This pin
has an internal 50KΩpull-up to 5V.
10 10 I MODE The state of the MODE signal determines how fault
conditions are cleared. The device is in latched mode
when this pin is low, and in cycle mode when the pin
is high or floating.
Table 1. SMH4804 Pin Descriptions

SMH4804 Pin Descriptions
Summit Microelectronics 2050 3.8 10/13/05 11
11 12 I SCL SCL is the serial clock input. This pin has an internal
50KΩpull-up to 5V.
12 13 I CBSENSE The circuit breaker sense input is used to detect over-
current conditions across an external, low value sense
resistor (RS)tied in series with the Power MOSFET. A
voltage drop of greater than 50mV across the resistor
for longer than tCBD trips the circuit breaker. A
programmable Quick-Trip™ sense point is also
available.
13 15 I A1 The A1 input works in conjunction with the A0 and A2
inputs. Together these inputs are used for decoding
multiple devices on the serial bus. The A1 input has an
internal 50KΩpull-up to 5V.
14 17 I VSS This is connected to the negative side of the supply.
15 20 I UV The UV pin is used as an under-voltage supply
monitor, typically in conjunction with an external
resistor ladder. VGATE is disabled if UV is less than
2.5V. Programmable internal hysteresis is available
on the UV input, adjustable in increments of 62.5mV.
Also available is a filter delay on the UV input.
16 22 I A2 The A2 input works in conjunction with the A0 and A1
inputs. Together these inputs are used for decoding
multiple devices on the serial bus. The A2 input has an
internal 50KΩpull-up to 5V.
17 24 I OV The OV pin is used as an over-voltage supply monitor,
typically in conjunction with an external resistor
ladder. VGATE is disabled if OV is greater than 2.5V.
A filter delay is available on the OV input.
18 25 I FS# The Forced Shutdown (FS#) pin is an active low input
that causes VGATE and the PG[4:1]# outputs to be
shut down at any time after an internal shutdown timer
has expired. The shutdown timer allows supervisory
circuits on the secondary side (which are not powered
up initially) to control shut down of the SMH4804 via
an opto-isolator. This input has no pull-up resistor.
19 26 O 5VREF This is a precision 5V output reference voltage that
may be used to expand the logic input functions on the
SMH4804. The output reference voltage is with
respect to VSS.
20 28 O 2.5VREF This is a precision 2.5V output reference voltage that
may be used to expand the logic input functions on the
SMH4804. The output reference voltage is with
respect to VSS.
Pin Number
(28-Pin SOIC)
Pin Number
(48-Pin TQFP)
Pin Type
(I/O)
Pin Name Description
Table 1. SMH4804 Pin Descriptions (Continued)

Pin Descriptions SMH4804
12 2050 3.8 10/13/05 Summit Microelectronics
21 29 I ENPGC The active-high ENPGC input controls the PG4#
output. When ENPGC is low, the PG4# output is
immediately placed in a high-impedance state. When
ENPGC is high, or left floating, PG4# is driven low at
a time period of tPGD after PG3# is asserted. This pin
has an internal 50kΩ pull-up to 5V.
22 30 I ENPGB The active-high ENPGB input controls the PG3# and
PG4# outputs. When ENPGB is low, the PG3#, and
PG4# outputs are immediately placed in a high-
impedance state. When ENPGB is high, or left
floating, PG3# is driven low at a time period of tPGD
after PG2# is asserted. This pin has an internal 50kΩ
pull-up to 5V.
23 32 I ENPGA The active-high ENPGA input controls the PG2#,
PG3#, and PG4# outputs. When ENPGA is low, the
PG2#, PG3#, and PG4# outputs are immediately
placed in a high-impedance state. When ENPGA is
high, or left floating, PG2# is driven low at a time
period of tPGD after PG1# is asserted. This pin has an
internal 50kΩ pull-up to 5V.
24 34 O PG3# The PG3# output is an open-drain, active low signal
with no internal pull-up resistor. This pin can be used
to switch a load or enable a DC/DC converter. PG1#
is enabled immediately after VGATE reaches VDD -
VGT and the DRAIN SENSE voltage is less than 2.5V.
Each successive PGn# output (PG2# →PG3# →
PG4#) is enabled tPGD after its predecessor, provided
that the ENPGx inputs are high. The voltage on this
pin cannot exceed 12V relative to VSS. ENPGx refers
to the ENPGA, ENPGB, and ENPGC inputs.
25 36 O PG1# The PG1# output is an open-drain, active low signal
with no internal pull-up resistor. This pin can be used
to switch a load or enable a DC/DC converter. PG1#
is enabled immediately after VGATE reaches VDD -
VGT and the DRAIN SENSE voltage is less than 2.5V.
Each successive PGn# output (PG2# →PG3# →
PG4#) is enabled tPGD after its predecessor, provided
that the ENPGx inputs are high. The voltage on this
pin cannot exceed 12V relative to VSS. ENPGx refers
to the ENPGA, ENPGB, and ENPGC inputs.
Pin Number
(28-Pin SOIC)
Pin Number
(48-Pin TQFP)
Pin Type
(I/O)
Pin Name Description
Table 1. SMH4804 Pin Descriptions (Continued)

SMH4804 Pin Descriptions
Summit Microelectronics 2050 3.8 10/13/05 13
26 37 O PG2# The PG2# output is an open-drain, active low signal
with no internal pull-up resistor. This pin can be used
to switch a load or enable a DC/DC converter. PG1#
is enabled immediately after VGATE reaches VDD -
VGT and the DRAIN SENSE voltage is less than 2.5V.
Each successive PGn# output (PG2# →PG3# →
PG4#) is enabled tPGD after its predecessor, provided
that the ENPGx inputs are high. The voltage on this
pin cannot exceed 12V relative to VSS. ENPGx refers
to the ENPGA, ENPGB, and ENPGC inputs.
27 40 O PG4# The PG4# output is an open-drain, active low signal
with no internal pull-up resistor. This pin can be used
to switch a load or enable a DC/DC converter. PG1#
is enabled immediately after VGATE reaches VDD -
VGT and the DRAIN SENSE voltage is less than 2.5V.
Each successive PGn# output (PG2# →PG3# →
PG4#) is enabled tPGD after its predecessor, provided
that the ENPGx inputs are high. The voltage on this
pin cannot exceed 12V relative to VSS. ENPGx refers
to the ENPGA, ENPGB, and ENPGC inputs.
28 42 I VDD This is the positive supply input. An internal shunt
regulator limits the voltage on this pin to approximately
12V with respect to VSS. A resistor must be placed in
series with the VDD pin to limit the regulator current
(RDin the application illustrations).
Pin Number
(28-Pin SOIC)
Pin Number
(48-Pin TQFP)
Pin Type
(I/O)
Pin Name Description
Table 1. SMH4804 Pin Descriptions (Continued)

Absolute Maximum Ratings SMH4804
14 2050 3.8 10/13/05 Summit Microelectronics
–
ABSOLUTE MAXIMUM RATINGS
Temperature Under Bias.............................–55°C to 125°C
Power Supply Current (IDD) .......................................15 mA
Storage Temperature ..................................–65°C to 150°C
Lead Solder Temperature (10 seconds) ................... 300 °C
Terminal Voltage with Respect to VSS:
VGATE ...................................................... VDD + 0.3V
A0, A1, A2, MODE, RESET, ENPGA, ENPGB,
ENPGC, FS#, SDA, and SCL..................... -0.3 to +7V
PD1#, PD2#, VDD, UV, OV, CBSENSE, DRAIN
SENSE, EN/TS, FAULT#, PG1#, PG2#, PG3#,
and PG4# ................................................. -0.3 to +15V
Open Drain Output Short Circuit Current.................100 mA
Junction Temperature ...............................................150oC
ESD Rating per JEDEC .............................................2000V
Latch-Up testing per JEDEC..................................± 100mA
Stresses listed under Absolute Maximum Ratings may
cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these
or any other conditions outside those listed in the
operational sections of this specification is not implied.
Exposure to any absolute maximum rating for extended
periods may affect device performance and reliability.
–
RECOMMENDED OPERATING CONDITIONS
Temperature Range (Ambient) ................. -40oC to +85oC
Supply Voltage(VDD) (IDD = 5 mA)..................... 11V to 13V
Package Thermal Resistance (θJA) 28-pin SOIC ... 79oC/W
Package Thermal Resistance (θJA) 48-pin TQFP... 80oC/W
Moisture Classification Level 3(MSL 3)per J-STD-020
Reliability Characteristics
Data Retention ..................................................... 100 Years
Endurance1................................................. 100,000 Cycles
1. Guaranteed by Design

SMH4804 DC Operating Characteristics
Summit Microelectronics 2050 3.8 10/13/05 15
–
DC OPERATING CHARACTERISTICS
(Over recommended operating conditions, unless otherwise notes. All voltages are relative to GND.)
Symbol Parameter Conditions Min Typ Max Unit
VDD Supply voltage IDD = 3 mA 11 12 13 V
5VREF 5V reference output voltage IDD = 3 mA 4.8 5.00 5.25 V
ILOAD5 5V reference output current IDD = 3 mA -1 1 mA
2.5VREF 2.5V reference output voltage IDD = 3 mA 2.45 2.50 2.55 V
ILOAD2.5 2.5V reference output current IDD = 3 mA -0.5 0.5 mA
IDD1Power supply current 2 13 mA
VUV Under-voltage threshold IDD = 3 mA 2.45 2.50 2.55 V
VUVHYST Under-voltage hysteresis IDD = 3 mA 632mV
VOV Over-voltage threshold IDD = 3 mA 2.45 2.50 2.55 V
VOVHYST Over-voltage hysteresis IDD = 3 mA 10 mV
VGATE VGATE output voltage IGATE = 80 µAV
DD - VGT VDD V
IGATE VGATE output current VGATE = 5 V 80 85 90 µA
VSENSE DRAIN SENSE threshold VSENSE = VSS 2.45 2.50 2.55 V
ISENSE DRAIN SENSE current output IDD = 3 mA 9 10 11 µA
VCB Circuit breaker threshold IDD = 3 mA 45 50 55 mV
VQCB Programmable Quick Trip circuit
breaker threshold voltage
QT = 200 mV 180 200 220 mV
QT = 100 mV 90 100 110 mV
QT = 60 mV 54 60 66 mV
VENTS EN/TS threshold voltage IDD = 3 mA 2.40 2.45 2.50 V
VENTSHYST EN/TS threshold hysteresis
voltage
IDD = 3 mA 10 mV
VIH Input voltages: ENPGA/B/C,
MODE, RESET#, PD1#, PD2#
35V
REF V
VIL -0.1 2 V
VOL Output low voltage: FAULT# IOL = 3 mA 0 0.4 V
Output low voltage: PG1#/2#/3#/
4#
IOL = 3 mA 0 0.4 V
IIL Input current: PD1#, PD2#, EN/
TS
VIL = VSS 100 µA
VGT Gate threshold 0.7 1.8 3.0 V
1. This value is set by the RDresistor.
2. See Table 8 for a listing of programmable under-voltage hysteresis settings.

AC Operating Characteristics SMH4804
16 2050 3.8 10/13/05 Summit Microelectronics
–
AC OPERATING CHARACTERISTICS
(Over recommended operating conditions, unless otherwise notes. All voltages are relative to GND.)
Symbol Description Conditions Min Typ Max Unit Comment
tCBD Programmable Over-Current Filter
tCBD = 5 µs
-25 tCBD +25
µs
See Figure 5,
Figure 6,
Figure 7, and
Figure 13
tCBD = 50 µs1
1. Indicates default value
µs
tCBD = 150 µsµs
tCBD = 400 µsµs
tPGD
Programmable power good delay
(PG1 →PG2, PG2 →PG3, PG3 →
PG4)
tPGD = 50 µs
-25 tPGD +25
%
See Figure 4
tPGD = 250 µs%
tPGD = 500 µs%
tPGD = 1000 µs%
tPGD = 5 ms1%
tPGD = 20 ms %
tPGD = 80 ms %
tPGD = 160 ms %
tQTSD Quick-Trip shutdown 200 ns See Figure 7
tCYC
Circuit breaker cycle mode cycle
time
tCYC = 2.5 s1
-25 tCYC +25 % See Figure 5
tCYC = 5 s
tCBRST CBRESET pulse width 200 ns See Figure 6
tPUVF Programmable under-voltage filter
tPUVF = Off1
-25 tPUVF +25 %
tPUVF = 5 ms
tPUVF = 80 ms
tPUVF = 160 ms
tPDD Programmable pin detect
tPDD = 0.5 ms
-25 tPDD +25 % See Figure 6
and Figure 13
tPDD = 5 ms
tPDD = 80 ms1
tPDD = 160 ms

SMH4804 I2C 2-Wire Serial Interface AC Operating
Characteristics
Summit Microelectronics 2050 3.8 10/13/05 17
–
I2C 2-WIRE SERIAL INTERFACE AC OPERATING CHARACTERISTICS
–
TIMING DIAGRAM
Figure 12 shows a timing diagram for the Bus Interface Memory timing. The table above lists the AC timing
parameters for Figure 12. One bit of data is transferred during each clock pulse. Note that data must remain
stable when the clock is high.
Figure 12. Bus Interface Memory Timing
(Over recommended operating conditions, unless otherwise notes. All voltages are relative to GND.)
Symbol Parameter Conditions Min Max Units
fSCL SCL clock frequency 0 100 kHz
tLOW Clock period low 4.7 µs
tHIGH Clock period high 4.0 µs
tBUF Bus free time1
1. Values are guaranteed by the design.
Before new transmission 4.7 µs
tSU:STA Start condition setup time 4.7 µs
tHD:STA Start condition hold time 4.0 µs
tSU:STO Stop condition setup time 4.7 µs
tAA Clock edge to valid output SCL low to valid SDA (cycle n) 0.2 3.5 µs
tDH Data out hold time SCL low (cycle n+1) to SDA
change
0.2 µs
tRSCL and SDA rise time11000 ns
tFSCL and SDA fall time1300 ns
tSU:DAT Data in setup time 250 ns
tHD:DAT Data in hold time 0 ns
tINoise filter SCL and SDA1Noise suppression 100 ns
tWR Write cycle time 5 ms
tF
tR
tLOW
tHIGH
tHD:SDA
tSU:SDA tBUF
tDH
tHD:DAT tSU:DAT tSU:STO
SCL
SDA In
SDA Out
tAA
2050 Fig09 2.0

Timing Diagram SMH4804
18 2050 3.8 10/13/05 Summit Microelectronics
Power-on Timing
Figure 13 illustrates some power on sequences, including the UV and OV differentials to their reference, and
Power Good cascading. Refer to the table on page 17 for more information on the tPDD and tCBD timings.
Figure 13. SMH4804 Power-On Sequences
2050 Fig01 2.1
VDD
UV
OV
PD1#/
PD2#
VGATE
DRAIN
SENSE
2.5VREF
2.5VREF
11 ≤VDD ≤13
tPDD
PG1#
PG2#
PG3#
tPGD
<tPUVF
50mVREF
<tCBD
CBSENSE
5V
VDD
VDD – VGT
tPGD
tPGD
PG4#
Note - A 'Fault' condition
has caused Drain
Sense to go high.

SMH4804 Timing Diagram
Summit Microelectronics 2050 3.8 10/13/05 19
SMH4804 Power-On Waveforms - Ref to -48V
Tektronix TDS3054: Time/Horizontal division = 40mS
Ch 1 (2V/Div) = 3.3V DC-DC converter output (Yellow trace)
Ch 2 (50V/Div) = PG#2 output (Blue trace) - Note 1
Ch 3 (50V/Div) = Switched 48V supply voltage (Purple trace)
Ch 4 (2A/Div) = Inrush input current (Green)
SMH4804 with 0.1uF and 0.01uF Soft-Start Capacitors
Tektronix TDS3054: Time/Horizontal division = 40mS
Ch 1 (50V/Div) = MOSFET Drain (Yellow trace)
Ch 2 (5V/Div) = SMH4804 UV pin (Blue trace)
Ch 3 (10V/Div) = MOSFET Gate (Purple trace)
Ch 4 (2A/Div) = -48V Inrush input current (Green)
Note 1 – After initial hot swap conditions are met, he PG# outputs first drop to –43V
until ready to sequence the DC-DC converter. When ready to sequence, the PG#
outputs then drop an additional 5V to enable the converters.
SMH4804 Sequencing waveforms - Ref to GND
Four DC/DC converters sequenced on at 160ms intervals
Tektronix TDS3054: Time/Horizontal division = 100mS
Ch 1 (1V/Div) = 5.0V DC-DC converter output (Yellow trace)
Ch 2 (1V/Div) = 3.3V DC-DC converter output (Yellow trace)
Ch 3 (1V/Div) = 2.5V DC-DC converter output (Yellow trace)
Ch 4 (1V/Div) = 1.8V DC-DC converter output (Yellow trace)
SMH4804 with 1uF and 0.1uF Soft-Start Capacitors
Tektronix TDS3054: Time/Horizontal division = 200mS
Ch 1 (50V/Div) = MOSFET Drain (Yellow trace)
Ch 2 (5V/Div) = SMH4804 UV pin (Blue trace)
Ch 3 (10V/Div) = MOSFET Gate (Purple trace)
Ch 4 (2A/Div) = -48V Inrush input current (Green)

Timing Diagram SMH4804
20 2050 3.8 10/13/05 Summit Microelectronics
Operating at High Voltages
The breakdown voltage of the external active and passive
components limits the maximum operating voltage of the
SMH4804 hot-swap controller. Components that must be
able to withstand the full supply voltage are: the input and
output decoupling capacitors, the protection diode in series
with the DRAIN SENSE pin, the power MOSFET switch and
the capacitor connected between its drain and gate, the
high-voltage transistors connected to the power good
outputs, and the dropper resistor connected to the
controller’s VDD pin.
Over-Voltage and Under-Voltage Resistors
In Figures 21, 22, and 23, the three resistors (R1, R2, and
R3) connected to the OV and UV inputs must be capable of
withstanding the maximum supply voltage of several
hundred volts. The trip voltage of the UV and OV inputs is
2.5V relative to VSS. As the input impedance of UV and OV
is very high, large value resistors can be used in the
resistive divider. The divider resistors should be high
stability, 1% metal-film resistors to keep the under-voltage
and over-voltage trip points accurate.
Telecom Design Example
A hot-swap telecom application may use a 48V power
supply with a –25% to +50% tolerance (i.e., the 48V supply
can vary from 36V to 72V). The formula for calculating R1,
R2, and R3 are as follows.
First, a peak current, IDMAX, must be specified for the
resistive network. The value of the current is arbitrary, but it
cannot be too high (self-heating in R3 becomes a problem),
or too low (the value of R3 becomes very large, and leakage
currents can reduce the accuracy of the OV and UV trip
points). The value of IDMAX should be ≥200µA for the best
accuracy at the OV and UV trip points. A value of 250µA for
IDMAX is used to illustrate the following calculations.
With VOV (2.5V) being the over-voltage trip point, R1 is
calculated by the formula:
Substituting:
Next the minimum current that flows through the resistive
divider, IDMIN,is calculated from the ratio of minimum and
maximum supply voltage levels:
Substituting:
Now the value of R3 is calculated from IDMIN:
VUV is the under-voltage trip point, also 2.5V. Substituting:
The closest standard 1% resistor value is 267 kΩ
Then R2 is calculated:
or
Substituting:
An Excel spread sheet is available on Summit's website
(www.summitmicro.com) to simplify the resistor value
calculations and tolerance analysis for R1, R2, and R3.
Dropper Resistor Selection
The SMH4804 is powered from the high-voltage supply via
a dropper resistor, RD. The dropper resistor must provide
the SMH4804 (and its loads) with sufficient operating
current under minimum supply voltage conditions, but must
R1 = VOV
IDMAX
R1 = 2.5V
250µA= 10 KΩ
IDMIN = IDMAX x VSMIN
VSMAX
IDMIN = 2.5 V
250µA x 36V = 125 µΑ
R3 = VSMIN x VUV
IDMIN
R3 = 36V x 2.5V
125 µΑ = 286 kΩ
(R1 + R2) = VUV
IDMIN
R2 = VUV
IDMIN - R1
R2 = 2.5V
125 µΑ - 10 kΩ = 20 kΩ − 10 kΩ = 10 kΩ