3
How It Works
The only circuitry on the MP-B2 mother board is that tying the various interface cards to the
system's interface information bus. IC1 is a non-inverting buffer used to drive selected control lines
feeding the interface cards. One of eight decoders IC3 and IC6 decode and enable one of eight
interface cards when one of the interface addresses is loaded to the 50-line system information bus.
Since the eight bit data bus for the main boards as well as the interface cards is bi-directional,
transceiver buffers IC7 and IC8 buffer the incoming and outgoing data to and from the interface data
bus to the system's data bus. Gates within NAND gate IC4 and NOR gate IC5 control the direction of
data flow within the transceiver/buffers. +5 VDC power for the interface decode/buffer circuitry is
provided by voltage regulator IC2. +5 VDC power for all of the plug-on boards, including interfaces, is
provided by separate regulators on each board.
The following is a brief description of each of the fifty lines on the system information bus:
D0 -D7# The D0 -D7# lines carry inverted data bits 0 thru 7 respectively forming 8-bit data
words which are exchanged between the various boards within the system.
A0 -A15 The A0 -A15 lines carry address bits 0 thru 15 respectively forming a 16-bit address
which is used to define either a memory location or interface address.
GND The GND line is the system's common or power supply ground point.
7-8
VDC UNREG
or +8 UNR
The 7 -8 VDC UNREG point is the line to which a +7 to 8 volt DC @10A unregulated
power supply should be attached. This voltage is then regulated down to +5 VDC by
in dependent regulators on the various boards within the system.
-12, +12 The -12 and +12 points are lines to which an isolated ground -12@200 Ma and +12
@200 Ma power supply should be connected. The voltages are necessary for
generating the currents required by 20 Ma current loop and RS-232 equipment on
the serial interfaces.
INDEX The INDEX is an unused bus and is provided so the pin on each of the male
connectors may be cut with the corresponding female connector pins plugged,
preventing the circuit boards from being plugged on incorrectly
M. RESET#
The MANUAL RESET# line when momentarily grounded indirectly resets the
registers internal to the processor and interfaces, and loads the ROM stored
mini-operating system. This line is normally grounded by depressing the RESET
button on the system's front panel.
NMI# The NMI# is the non-maskable, single level interrupt line feeding the processor
board. When momentarily grounded it forces the processor into a push-down stack,
store routine, followed by a program jump to a user selected address stored in the
operating system RAM. The NMI# is non-maskable thus, can not be inhibited by the
programmer thru software.
IRQ# The IRQ# is the maskable, single level interrupt request line feeding the processor
board. If not inhibited by software it will, when momentarily grounded, force the
processor into a push-down stack, store routine followed by a program jump to a user
selected address stored in the operating system RAM.
UD1, UD2 The UD1 and UD2 are user defined lines and have not been assigned a function.
ø2 ø2 is one of the two complementary system clock outputs and is used to signal that
valid data is on the data lines D0 -D7# when low.
VMA# VMA# is the valid memory address line which goes low to confirm that valid memory
data is being presented on the sixteen address lines, A0 -A15.
