Tektronix 7D11 Operating instructions

Tektronix, Inc.
P.O. Box 500
Beaverton, Oregon 97005
070 · 1377 ·01
TEKTRONI»
7D11
DIGITAL DELAY
SERVICE
INSTRUCTION MANUAL
Serial Nu mber
873

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WARRANTY
All TEKTRONIX instrumenU are warranted against
defective materials and wor1<manship for one year. Any
questions with respect to the wlnlnty should be taken up
with your TEKTRONIX Field Engineer or representative.
All requests for repair and replace ment parts should be
directed to the TEKTRONIX Field Office or representative
in your area. This will assure you the fastest possibfe
service. Please include the instrument Type Number or Part
Number and Se.-ia' Number with aU requests for parts or
se rvi ce.
Specifications and price change privileges reserved.
Copyright @1973 by Tektronix , Inc., Beaverton, Oregon.
Printed in the United States of America. All rights resel'Yed.
Content s of thi s publication may not be reproduced in any
form without perm rss ion of Tektronix, Inc.
U.s .A. and Foreign TEKTRONIX products covered by U.S.
and foreign patents and/or patents pending.
TEKTRONIX is a registered tradem.k of Tektronix. Inc.

7011 Service
TABLE OF CONTENTS
SECTION 1 OPERATING INFORMATION
Page
7011 FEATURES
1-1
PRELIMINARY INFORMATION
1-1
Installation
1-1
Display
1-1
CONTROLS AND CONNECTORS 1-3
GENERAL OPERATING INFORMATION
1-3
Signal Connection 1-3
Count Mode 1-4
Trigger Controls 1-4
Triggered Light 1-4
Trigger Coupling 1-4
Trigger Source 1-5
Trigger Slope/Level 1-5
Events Start Trigger 1-5
Delay Tim~ or Events 1-5
Fine Delay 1-5
B
Sweep Delay Mode 1-5
OUTPUT SIGNALS 1-6
Front Panel Output Signals 1-6
Output Signals to Mainframe 1-6
OPERATING MODES 1-7
Sweep Delay 1-7
Echo Delay Time Mode 1-7
SECTION 2 THEORY OF OPERATION
INTRODUCTION
2-1
BLOCK DIAGRAM
2-1
Time/Events Trigger
2-1
Phase Lock Loop and Gated Countdown
2-1
Outputs Processing and Events Start Trigger
2-1
Delaying Counter and Display Generator
2-1
~
Readout Encoding
2-1
®

7D 11 Service
TABLE OF CONTENTS (cant)
SECTION 2 THEORY OF OPERATION (cont)
Page
THEORY OF OPERATION 2-2
TRIGGER CIRCUITS<y 2-2
Trigger Preamp 2-2
Trigger Generator 2-3
PHASE LOCK LOOP AND GATED COUNTDOWN<§> 2-5
Phase Lock Loop 2-5
Fine Delay 2-6
Gated Countdown 2-6
OUTPUTS PROCESSING AND EVENTS
START TRIGGER 0 2-9
Time/Events Count Source Gate 2-9
Delayed Trigger Output Flip-Flop 2-9
Delayed Gate Flip-Flop 2-10
Events Start Trigger 2-11
DELAYING COUNTER AND DISPLAY GENERATOR 0 2-11
Voltage to Frequency Converter 2-11
Reversible Counter and Nines Complement Review 2-12
Delaying Counter 2-12
Power-On Initializer 2-12
Reset 2-13
READOUT ENCODING
<§> 2-13
POWER DISTRIBUTION AND MAINFRAME
CONNECTOR 0 2-13
D.C. Inverter 2-14
INTRODUCTION TO THE READOUT SYSTEM 2-14
Introduction 2-14
The Readout System 2-14
SECTION 3 MAINTENANCE
INTRODUCTION 3-1
PREVENTIVE MAINTENANCE 3-1
General
3-1
Cleaning 3-1
Lubrication 3-1
Recalibration 3-1
ii ®

REV. B. FEB. 1977
TABLE OF CONTENTS (cont)
SECTION 3 MAINTENANCE (cont)
TROUBLESHOOTING
General
Troubleshooting Aids
Troubleshooting Equipment
Troubleshooting Procedure
REPLACEMENT PARTS
Standard Parts
Transistor and Integrated
Circuit Replacement
Recalibration
After Repair
Special Parts
Ordering Parts
Repackaging
for Shipment
SECTION 4 CALIBRATION
Calibration Interval
Tektronix Field Service
Using This Procedure
TEST
EQUIPMENT REQUIRED
1
General
Test Equipment Alternatives
Signal Connections
CALIBRATION PROCEDURE INTRODUCTION
Index to Calibration Procedure
Preliminary Procedure
DIGITAL READOUT DISPLAY
TRIGGERING
EVENTS COUNT MODE
TIME COUNT MODE
OUTPUT SIGNALS
SECTION 5 ElECTR ICAl PARTS LIST
SECTION 6
DIAGRAMS
SECTION 7 MECHANICAL PARTS LIST
CHANGE INFORMATION
Page
3-1
3-1
3-1
3-2
3-2
3-3
3-3
3-3
3-3
3-3
3-3
3-3
4-1
4-1
4-1
4-1
4-1
4-1
4-1
4-4
4-4
4-5
4-6
4-7
4-11
4-14
4-19
7011 Service
iii

•
7011 Service
-
--
lIIlGILER
7011
CIIU'UII SOURCf
.. ..
iii iii
_bILl lIII
iii iii
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iii iii
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iii iii
DELAY TIME odYfITl
j
•
Ol Y'O TRIG OUT
t.TV INTO fi.On
o ~~ ~ ~ I ~;';:;:::;:: ;:
"'"
DIGITAl DELAY
Fig. 1-1 . 1011 Oigi1~1 O e l~y .
®

Section 1-7011 Service
OPERATING INFORMATION
7011 FEATURES
The 7D11 Digital Delay plug-in unit is designed for use
with Tektronix 7000-series Oscilloscope mainframes
equipped
with a readout system. The 7D11 uses the
readout system to display the selected delay count on the
CRT. A delayed trigger output is generated by counting
time or events. Digital delay time to one second is read out
in 100-nanosecond increments. Additional analog delay
time from zero to 100 nanoseconds selected from a
cal ibrated front-panel dial provides added resolution. An
"echo" time-delay mode provides a divide-by-two scaler to
read out the "one-way trip" time, up to l two seconds, for
radar ranging and TDR applications. Delay time accuracy is
controlled by an internal crystal oscillator; greater accuracy
can be obtained by the use of an external one-megahertz
standard.
In the Count by Events mode, the CRT readout
displays the integer number of events from one to 10
7
events at count rates up to 50 megahertz.
The 7D11
can be used to delay a 7B-series time-base unit
in either a runs-after or triggerable-after delay time mode.
Other 7D 11 features include on-screen display of delay
interval
by vertical signal or display blanking, trigger
pickoff from vertical amplifier unit, and blanking of the
two leading zeros (count by time mode only).
PRELIMINARY INFORMATION
Installation
The 7D11 is designed to operate in any plug-in compart-
ment of Tektronix 7000-series mainframes. However, cer-
tain modes of operation require the 7D 11 to be installed in
a specific
compartment. The unit must be operated in a
horizontal compartment to trigger from a signal applied to
REV. B. OCT. 1974
a vertical amplifier unit. The 7D 11 must be operated in the
A
Horizontal compartment to control the delay mode of a
time-base
unit in the B Horizontal compartment. Operation
in a vertical
compartment is necessary to view the Delay
Interval Pedestal
without the use of external cables.
To install the 7D 11 into a plug-in compartment, push
the unit in until it is seated flush against the front panel of
the mainframe. To remove, pull the release latch to
disengage the 7D11. Continue to pull the release latch to
remove the'unit from the mainframe.
Display
The 7D11 readout display is presented on the CRT of
the mainframe, along with information encoded by the
other plug-in units. Digital delay time (in milliseconds) is
displayed in five to eight digits. The + symbol to the right
of the digital display reminds the operator to add any
analog delay time selected by the FINE DELAY (ns) dial to
the delay time. The number of events being counted is
presented in a seven to eight digit display.
The 7D11 readout display appears on the CRT in a
location corresponding to the plug-in compartment used.
The delay
time or number of events will be displayed in the
top division of the CRT graticule. The delay-time measure-
ment unit (ms) will be displayed in the bottom division. It
is not necessary to select the 7D 11 with the mainframe
Vertical or Horizontal Mode switches to view the digital
display. In order to view the Delay Interval Pedestal
waveform, selection
with the Vertical Mode switch is
required.
1-1

Operating Inform ation - 70ll Service
4 5 6
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fill. 1· 2. 7011 fronl ·panel co nlr ols and conneclor s.
®

CONTROLS AND CONNECTORS
The major controls and connectors for operation of the
7D11
are located on the front panel of the unit. Two
controls located inside the unit for auxiliary functions are
described in the General Operating I nformation section.
The front-panel controls
and connectors are identified in
Fig. 1-2;
their functions are as follows:
®
GJ COUNT MODE Switch
Selects mode
of operation and clock-signal
source
for Time count mode.
o B SWEEP DELAY MODE Switch
Selects the delay mode logic
for time-base unit.in
B Horizontal compartment of mainframe.
o TRIGGER SLOPE/LEVEL Controls
Select slope
and amplitude point of input signal
where the delay is initiated.
o TRIG'D Indicator
Lights when a trigger is produced.
o COUPLING Switch
Selects the method
of coupling the input signal
to the Trigger circuit.
o SOURCE Switch
Selects Trigger
input signal source.
EVENTS START TRIGGER SLOPE/LEVEL
Controls
Select slope
and amplitude point of input signal
where the Events Start count is initiated.
DELAY TIME OR EVENTS Control
Selects delay
time or number of events counted.
Direction
of rotation selects increase or decrease
in delay
time or number of events.
RESET
Resets the DELAY TIME or EVENTS to
0000001.
FINE
DELAY (ns) Dial
Selects analog delay
time added to digital delay
time selected by DELAY TIME OR EVENTS
control.
Operating Information-7D11 Service
G2J DLY'D TRIG OUT
BNC connector for Delayed Trigger output
signal.
(g] EXT 1 MHz IN or EVENTS START TRIG IN
BNC connector for input of external 1 MHz
time·reference signal
or input of Events Start
Trigger input signal. Connector function is deter-
mined by setting of COUNT MODE switch.
~ DLY INTERVAL OUT
BNC connector for Delay Interval output signal.
[!;] EXT TRIG IN
BNC connector
for external input to Trigger
circuit (selected by SOURCE switch in the
external positions).
GENERAL OPERATING INFORMATION
Signal Connection
In general, probes offer the most convenient means of
connecting signals to the 7D11 external trigger inputs.
Tektronix probes are shielded to prevent pickup of electro-
static interference. A 10X attenuation probe offers a high
input impedance and allows the circuit under test to
perform very close to normal operating conditions. Also, a
10X probe attenuates the input signal ten times.
Tektronix probes are designed to monitor the signal
source with minimum circuit loading. The use of a probe
will, however, limit the maximum trigger frequency range.
To obtain maximum trigger bandwidth when using probes,
select a probe capable of compensating the input capaci-
tance; observe the grounding considerations given in the
probe manual. The probe-to-connector adapters
and the
bayonet-ground
tip provide the best frequency response.
In high-frequency applications, requiring maximum over-
all bandwidth,
use a coaxial cable terminated at both ends
in the characteristic impedance
of the cable. To maintain
the high-frequency characteristics
of the applied signal, use
high-quality low-loss cable. Resistive coaxial attenuators
can be used to minimize reflection if the applied signal has
suitable amplitude.
High-level, low-frequency signals
can be connected
directly to the external trigger inputs with short, unshielded
leads. When this method is used, establish a common
ground between the 7D
11 and the associated equ ipment.
The common ground provided
by the line cords is usually
inadequate. If interference is excessive with unshielded
leads,
use a coaxial cable or probe.
1-3

Operating Information-7D11 Service
A signal can also
be routed to the 7D 11 through an
amplifier unit via the internal trigger circuitry of the
mainframe (7D 11 installed in a horizontal compartment).
This method of signal connection minimizes circuit loading,
especially when triggering a time-base unit in parallel with
the 7D 11.
NOTE
Only external signals can be used with the Events
Start Trigger.
The front-panel output signals, DL Y'D TR IG OUT and
DLY INTERVAL
OUT, should be connected to other
equipment with 50-ohm coaxial cables. The cables should
be terminated in 50 ohms to maintain the rise and falltime
characteristics of these signals.
Count Mode
General. Two basic count modes, Time and Events, can
be performed by the 7D11, as selected by the COUNT
MODE switch. The delay interval in both modes is selected
by the DELAY TIME OR EVENTS control and is read out
on the CRT.
TIME INT CLOCK.
The 7D 11 counts precise incre-
ments of time after the receipt of a trigger. The TRIGGER
controls select and condition the signal to start the time
delay. Accuracy in this mode is determined by an internal,
crystal-controlled oscillator.
TIME EXT 1 MHz. This
count mode is the same as
TIME INT CLOCK except the accuracy is derived from an
external, one-megahertz standard.
EVENTS.
The 7D 11 counts events, periodic or aperi-
odic, at count rates to 50 megahertz. The EVENTS START
TRIGGER provides a means of discriminating between the
event that starts the delay and the events to be counted.
The events to be counted are selected and conditioned by
the TRIGGER controls.
Trigger Controls
The input signal may have a wide variety of shapes and
amplitudes, many of which are unsuitable as delay-initiating
triggers.
For this reason, these signals are first applied to a
trigger circuit where they are converted to pulses of
uniform
amplitude and shape. This makes it possible to
start the delay with a pulse that has a constant size,
eliminating variations of the delay circuit operation caused
by changing
input signals. The TRIGGER controls provide
a means to select the signal source, filter unwanted
frequencies, and start the delay at any voltage level on
either slope of the waveform.
1-4
Triggered Light
The TRIG'D light provides a convenient indication of
the Trigger circuit condition. If the TRIGGER controls are
correctly set and an adequate signal is applied, the TRIG'D
light is on. If the TR IG'D light is off, no delay interval is
started. The cause might be an incorrectly set TRIGGER
control, low signal amplitude, or a signal repetition rate
outside the usable frequency range. This feature can be
used as a general indication of correct triggering when there
is no display on the CRT. The Delay Interval Pedestal and
Z-Axis Blanking displays also aid
in obtaining correct
TRIGGER control settings. See the discussion of these
features under Output Signals to Mainframe for further
information.
NOTE
When the 7D11 is used in the EVENTS count mode,
the
EVENTS START TRIGGER affects the output
of the Trigger circuit but has no effect on the
TRIG'D light.
Trigger Coupling
The TRIGGER pushbuttons located below the
COUPLING title select the method in which the input
signal is connected to the Trigger circuit. Each position
permits selection
or rejection of various frequency compo-
nents of the signal used to trigger the delay start.
AC. In this position of the COUPLING switch, the DC
component of the input signal is blocked. Signals with
low-frequency
components below about 30 hertz are
attenuated. In general, AC COUPLING can be used for
most applications. However, if the signal contains unwanted
frequency
components or if the delay is to be triggered at a
low repetition rate or DC level, one of the other switch
positions will provide
better results.
The triggering point in the AC position depends upon
the average voltage level of the input signal. If the input
signal occurs randomly, the average voltage level will vary,
causing
the triggering point to vary also. This shift of the
triggering point may be enough so it is impossible to
maintain a stable delay start; in such cases, use DC
coupling.
AC LF REJ. In
this position, DC is rejected and
low-frequency input signals below about 30 kilohertz are
attenuated. Therefore, the delay is triggered only by the
higher-frequency components of the input signal. The AC
LF REJ position is particularly useful for providing stable
triggering if the input signal contains line-frequency compo-
nents.
AC HF REJ. This COUPLING switch position passes all
low-frequency signals between about 30 hertz and 50
kilohertz. DC is rejected and signals above 50 kilohertz are
attenuated. This position is useful to trigger the delay from
the low-frequency components of a complex waveform.
®

DC. The DC position can be used to provide stable
triggering from low-frequency or low-repetition-rate signals
which would be attenuated in other modes. It can also be
used
to trigger the delay when the input signal reaches a DC
level selected by the setting of the SLOPE/LEVEL control.
When triggering from the internal source, the setting of the
vertical unit position control(s) affects the DC triggering
point.
Trigger Source
The TRIGGER pushbuttons located below the SOURCE
title select the source of the signal connected to the Trigger
circuit.
INT. In this position, the input signal is derived from
the associated vertical unit. Therefore, the 7D 11 must be
installed in a horizontal compartment to use the internal
source.
Further selection of the internal signal may be
provided by the vertical unit and mainframe; see the
instruction manuals for these instruments for further
information.
LINE.
In this SOURCE switch position, a sample of the
power-line voltage from the mainframe is connected to the
Trigger circuit. Line triggering is useful when the input
signal
is time related (multiple or submultiple) to the line
frequency. It is also useful for providing stable triggering
from a line-frequency
component in a complex waveform.
EXT. A signal connected
to the EXT TRIG IN con-
nector can be used to trigger the delay in the EXT position
of
the SOURCE switch. An external signal can be used to
provide a trigger when the internal signal amplitude is too
low.
EXT
-;- 10. Operation in this position is the same as
described for EXT except the external signal is attenuated
10 times. Attenuation of high-amplitude signals is desirable
to extend the range of the LEVEL control.
Trigger Slope/Level
The TRIGGER SLOPE/LEVEL controls determine the
slope and voltage level of the input signal where the Trigger
circuit responds. Generally,
the best point on a waveform
for triggering
the delay is where the slope is steep, and
therefore usually free of noise. Assuming a sine-wave input
waveform,
the steepest slope occurs at the zero-crossing
point. This
is the point selected for triggering when the
LEVEL control is set to 0 (center). A more positive or
negative point on
the waveform is selected as the LEVEL
control is rotated clockwise or counterclockwise respec-
tively from 0 (toward + or -symbols on panel).
Before setting the TRIGGER LEVEL, the desired
SLOPE, MODE, COUPLING, and SOURCE should be
selected. Then adjust the LEVEL control so the delay starts
from
the desired point.
®
Operating Information-7D11 Service
Events Start Trigger
The Events Start Trigger is used in the EVENTS count
mode to differentiate between the event that starts the
delay and the events being counted.
The EVENTS START TRIG IN connector provides the
input to the events-start signal. The EVENTS START
TRIGGER SLOPE and LEVEL controls select
the ampli-
tude point and slope on the input signal where the delay is
triggered.
Delay Time or Events
The DELAY TIME OR EVENTS control selects the
digital delay time in the TIME count mode, and the number
of events counted in the EVENTS count mode. The delay
time
in milliseconds, or integer number of events, selected
is displayed on the CRT readout.
This control
is a spring-return-to-center control that
increases or decreases the count at which a delayed pulse
will occur. The direction of rotation determines whether
the count is increased or decreased. The rate at which the
count increments is determined by the magnitude of
rotation. After either
extreme of the range is reached, the
next count starts from the other end of the range. For
example,
if the delay time is increased above 1000.0000 ms
(one second),
the count will go to 0.0001 ms. Conversely, if
the delay time is decreased past 0.0001 ms, the count will
go to 1000.0000 ms.
Fine Delay
The FINE DELAY (ns) dial selects analog delay time
from zero to 100 nanoseconds in the TIME count mode.
This one-turn control provides added resolution
to the
digital delay time selected by the DELAY TIME OR
EVENTS control. The delay time selected by the FINE
DELAY (ns) dial is read from the calibrated knob as the
analog delay time is not read out on the CRT. Each minor
division on the dial represents two nanoseconds.
B Sweep Delay Mode
The B SWEEP DELAY MODE switch permits the 7Dll,
under specific conditions, to select the delay mode of a
compatible time-base unit.
To use this feature, the 7D 11 is
installed in the A Horizontal compartment and the time-
base in the B Horizontal compartment of a four-plug-in
mainframe. With this arrangement,
the time-base unit can
be controlled through the mainframe interface. Some dual
time-base units are
not compatible with this feature; see the
time-base unit instruction manual for further information.
INDEPENDENT. The 7Dll and the time-base unit
operate independently.
B STARTS AFTER DELAY.
The time-base unit pro-
duces a sweep immediately following the selected delay
interval. This provides the same mode of operation as
triggering the time-base unit with the delayed trigger
output.
1-5

Operating Inform ation - 70ll Service
B
TRIGGERABlE AFTER DElAY . The time·base unit
produces a sw-eep after the first trigger pulse is received
follO'Ning the selected de lay interval. This mode of opera·
tion provides a stable display of a signal having time jitter.
Precision time measurements cannot
be made in this mode
because the actual delay time
is only partially dependent on
the delay interval of the 7011.
OUTPUT S IGN ALS
Front -Panel Output Signals
General. The Delay Interval and Oelaved Trigger ou t-
puts are available al the front·panel Ol Y INTERVAL OUT
and Ol Y'O TRIG OUT connectors respectively. These
outputs can be used to contro l other equipme nt during or
immediatelv following the delav interval, To maintain the
rise and falltime characteristics of these signals, connection
to other equipment should be made with 50-ohm coaxial
cable; the output of the cable should be terminated in 50
ohms.
OlY INTERVAL OUT. This output is a positive'going,
rectangular waveform coincident with the generated delav
interval. In the time mode, the OlY INTERVAL OUT is
approximatelv 20-30 nanoseconds shorler than the indio
cated de lav time because of internal propagation delaVs and
trigger recognition time. In the event mode, the DlY
INTERVAL OUT fswithin 30 naoosec ondso f actual delav,
usuallv 10 nanoseconds.
Ol Y'D TR IG OUT. This signal is generated as a
positive.going rectangular pu lse coincident with the end of
the delay interval.
The front·panel outpu t signals are shown In Fig. 1-3,
along with the input signal.
The input signal, Fig. 1·3(A), is
comprised of one -and ten-microsecond time marker s. The
I v
'v
l-
•
,
..
.
A
•
~
,
I
c I
VI S ,
Fig. "3. Displav shOWIng lime ,.hllionship of : IAI Inpllt signel 10
Ihe fronl p~n.l ; (8) D.I~V I nte , vil l; ;lOd leI Deilived T, igge. Olllpll l ~.
' ·6
70 11 is set for a O.0038·millisecond de lay time after
triggering on the ten·microsecond markers. The resultant
Delay Interval and Delaved Trigger
outputs are shown in
Fig. 1·3(B) and (e)' respectively.
Output Signals to Mainframe
General. Signal outputs are provided to the mainframe
via the interface connector. The fo
ll owing discussion
describes these
sig nals and the operati ng conditi ons neces-
sary for their use.
Delay· lnt erval Pedestal. This output provides an on -
screen display of the approximate delay interval. To vi ew
the pedestal display, the 7011 must be installed in a
vertical plug· in compa rtment and be selected by the
mainframe Vertical Mode switch.
The position of this
display is fixed near the vertical c enter of the graticule area.
The Delay·
lnter val Pedestal display is shown in Fig. 1·4 (A ).
The input signal, shown in Fig. 1· 4(8), is comprised of one ·
and ten·microsecond time markers. The 7011 is set to
trigger
on the ten-microsecond markers, and to generate a
O.0038-millisecond delay time.
..
... .. .. ....
.. ..
A
• •
I
I V
..
,
Fig . 1-4. Wilvefo,m displ ay of , (AI DellV Int erval Plildestal; (8)
input signal.
Delayed Trigger. The Delayed Trigger output provides
an inte(nal Delayed Trigger source for a time·base unit. A
time-base unit can be triggered from the Delay Tr igger
when the 70 11 is in a vertical compa rtment. To use this
output, the 7011 must be selected by the appr op riate
trigger source switch (mainframe).
Z-Axis Blanking. Z·axis blanking provides an on ·screen
display of the approximate delay interval. Th is is accom-
pl ished by blanking out the CAT displaY during the delay
i nt erval. Z-axis blanking can be obtained with the 7011
installed in any plug. in compartment . The Z -a xi s blanking
dislllav is selected by a slide sw itch located inside the unit
(on the left side; see Fig. 1·5).
@

• • • •
• • • •
• e • •
Fig _1-5 . Location of Z· AlIIi s Blanking Oispl ay switch ( on lef! side
of ',,$I,umend. T he switch posit io n towards tho 'ear of Ihl unit
sel ects Z- axis bl anking.
NOTE
At faster sweep speeds (100 nsldiv or faster) care
must be t aken when illterpreting CRT display because
relative propagation delays through th e lOl l and
vertical amplifier plug-ins are not the same. This
appears as a relative rfme s hift between delay in terval
pedeswl or Z-axis blanking generated by the 7011
and the signal(s) viewed through a vertical amplifier
on the CRT. Changing the TRIG SOURCE between
INT and EXT or EXT + 10 will vary this apparent
time shi ft due to differences in propagat ion delays of
th e signal path.
OPER ATING MO DE S
Sweep De lay
The 7D 11 can be used to delay the sta rt of a sweep fo r a
sel ec ted time interval following the receipt of a trigger.
Low· jitter sweep delay can be used for accur ate time, ji tter ,
and stability measurements . Sweep delay can also be used
to select a po rti on of a complex sig nal for display. A sweep
is delayed by triggering the ~ eep from the Delayed Trigger
output of the 70 II , rather than from the signal to be
displayed. Several methods of coupling the Delayed Trigger
to the sweep are possible, depending on the appli cation.
These methods are described in the following discussions.
B Sweep Delay Mode Swi tch . The sweep produced by a
time-base unit can be controlled and delayed by a 701 1 via
the mainframe interface and the 8 SWEEP DELAY MODE
swi tch. To use this mooe 01 sweep delay, the 701 1 must be
installed in
the A Horizontal compartment and the tim e-
base unit in the 8 Horizontal compartmen t of a four .plug-in
mainframe.
For further information, see B Sweep Delay
Mode.
Operating Information- 7D11 Service
NOTE
The logic levels provided to the 7D II from the
mainframe are designed to cont
rol a time-base unit
delaving sweep. For this reason, tIle 7 DI I might
become locked out (no output) when the se tt ing of
either the B-Sweep uni t Time/Division swit ch or rhe
B SWE EP DHA Y MODE sw itch is changed. If this
occurs, a delayed sweep
will not be produced. To
rese t the 7D11, set the B SWEEP DELA Y MODE
swi tch first to INDEPENDENT, then select the
desired delay mode.
I nte rnal Trigger. The sweep produced by a time·base
unit in a horizo nt al co mpartment can be internally trig.
gered from a 7
011 in a vertical co mpartmen t. To use this
sweep delay
mooe, the 70 11 must be selected by the
mainframe trigger so
ur ce switch. Delaying a time·base
sweep from the internal source can be used with the units
installed in
either a three- or four.plug-in mainframe.
External Trigger Source. A sweep can be delayed by
external triggering from the OLY'D TRIG OUT connector .
This
methoo can be used with any triggered sweep.
Echo Delay Ti me Mo de
The Echo dela y time mooe provides a CRT readout of
the "one ·way- trip·' time, or one·hall of the generaled delay
time. Th is mode of ope ra ti on is selected for use by an
internal
swi tch (on leh side of unit. see Fig. 1-6). In the
Echo mode, the delay time is selected by the DELAY TIME
OR EVENTS contro l in 200 ·nanosecond i ncr eme nts. An
insertion delay
of about 160 nanoseconds in this mode
requires adding analog delay
time to the first delay
increm
ent to obtain a 2QO ·nanosecond delay interval. This
can be
acco mplished by displaying the OELAY IN TERVAL
OU T and setting the FI NE DELAY dial fo r a tolal de lay
interval of 200 na no seconds as measured on the graticule.
•
•
•
•
Filii. l~ . l oca tion of No.mal · Echo D elav T.m e Mode swi tc h Ion
left side of unitl. Slit th e sw;te h towa r ds tha fronl of the unit to
sele.;t Normal Mod e.
' ·7

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Section 2-7011 Service
THEORY OF OPERATION
INTRODUCTION
This section provides a general, block diagram descrip-
tion of the 7Dl1. This is followed by the theory of
operation which
is keyed to the schematic diagrams of the
circuits described. If more information is desired on
commonly used circuits, refer to the following textbook:
Jacob Millman and Herbert Taub-, "Pulse, Digital, and
Switching Waveforms", McGraw-Hili, New York, 1965.
Following the theory of operation is a brief discussion of
the readout system used in Tektronix 7000-series Oscillo-
scopes. If more information is required on the readout
system, refer
to the instruction manual for the oscilloscope.
BLOCK DIAGRAM
The block diagram is divided into the following five
main sections: Time/Events Trigger, Phase Lock Loop and
Gated
Countdown, Outputs Processing and Events Start
Trigger, Delaying Counter and Display Generator, and
Readout Encoding.
Time/Events Trigger
The Time/Events Trigger circuit processes the trigger
signal for starting
the delay by time count through the
Phase Lock Loop and Gated Countdown circuit when in
the delay by time mode. In the delay by events mode the
trigger circuit provides the actual count signal, derived from
the signal selected by the SOURCE and COUPLING
switches.
REV. B, FEB. 1977
Phase Lock Loop and Gated Countdown
The Phase Lock Loop and Gated Countdown block
consists
of two main sections. One section is the phase lock
loop
that supplies a stable 500-megahertz clock, phase
locked
to an internal five-megahertz crystal or to an
external one-megahertz reference.
The second section con-
sists of the fine delay and gated countdown circuits. When a
trigger
is received from the trigger section, it is routed
through
the Fine Time Delay Multi-stage where it is delayed
an additional amount, determined by the front panel
control, to the Time Count Switch. Once the Time Count
Switch is opened, it allows the 500-megahertz clock to be
divided
down to 10 megahertz. This 10-megahertz signal is
then presented to the Time/Events Count Source Gate in
the Outputs processing and Events Start Trigger section.
Outputs Processing and Events Start Trigger
The Outputs Processing and Events Start Trigger section
performs several internal and reset functions
in addition to
providing the various outputs of the 7Dll. This circuit
provides B sweep delay, Z-axis intensification during
the
delay interval, the delay interval out pedestal, and the
delayed trigger output. This circuit also contains the Events
Start Trigger, which allows counting of events trigger in the
delay by events mode.
Delaying Counter and Display Generator
The Delaying Counter and Display Generator section
provides the circuitry for setting up the delay by time or
delay by events count.
The delay is set up as the nines
complement of
the delay count in the Reversible Counter
by the DELAY TIME OR EVENTS CONTROL and is
counted by the Delaying Counter. The Delaying Counter
counts time from 100 nanoseconds to one second or counts
events to 10,000,000. When the preset delay count is
completed (the count signal to the Delaying Counter comes
from
the Time/Events Count Source Gate on block 3), the
Nines Arm Gate activates the Output Release Gate on block
3. This simultaneously ends the DLY INTERVAL OUT and
activates
the DL Y'D TRIGGER OUT.
Readout Encoding
The delay time or events setting is encoded by the
Readout Encoding section. These circuits provide necessary
information to the readout system in the associated
mainframe
to allow the delay time or events count to be
displayed on the CRT.
2-1

Theory of Operation-7D11 Service
THEORY OF OPERATION
The following theory of operation discussion is refer-
enced to the schematic diagrams in the diagram section of
this manuaL Each main topic heading
is followed by the
number of the schematic to which it applies.
TRIGGER CIRCUITS0
The trigger circuit consists of two main sections, the
trigger preamp and the trigger generator.
Trigger Preamp
The trigger preamp serves to select trigger source and
coupling for
the trigger generator. This circuit may be
considered as consisting
of the following four elements:
Trigger Source Switching, U60; External Trigger Preamp or
external input amplifier,
032, 037, and 041; Balanced-to-
Single-Ended Converter,
071, 075, and 078; and Trigger
Coupling, 082, 084, and 086.
Trigger Source Switching. U60 receives internal trigger
inputs
at pins 2 and 15 and external trigger signals at pin 7.
U60 determines which input signal is selected by means of a
digital signal (voltage level) at pin 4. A LO on pin 4
activates pins 2 and 15 for internal triggering, while a
HI on
pin 4 switches U60 to activate pins 7 and 10 for external
triggering.
To further examine U60, assume that pin 4 is low,
activating pins 2 and 15 for internal triggering. This input is
a relatively high impedance differential configuration. Pin
15 receives the positive-going trigger signal and pin 2
is the
negativeijoing input. The inputs are biased at the center of
their dynamic range and signal limiting
in the trigger
pickoff circuitry (in
the indicator oscilloscope) ensures that
the inputs will not be driven into cutoff or saturation. R55
and R57 terminate
the internal trigger signal from the
indicator oscilloscope. The analog current source for
internal triggering
is through pins 1 and 16.
The switch output current appears at pins 12 and 13. A
positive-going signal
at pin 15 will cause an increase in
current into pin 13 and out through pin 16, R66, and R69.
Simultaneously, the negative-going signal at pin 2 causes a
decrease
in current into pin 12 and out through pin 1, R68,
and R69.
The net result is that the total current through
pins 12 and
13 and through R69 remains constant.
External Trigger Preamp. This circuit includes
032,037
and 041. The SOU RCE switch (S5) at the input selects
internal, external, or line signals for triggering.
The external
trigger signal may be attenuated
to one-tenth amplitude by
2-2
selecting EXT 710. R6 and R7 (paralleled by R30) form a
10:1 attenuator.
The input impedance for the trigger input is one
megohm, consisting primarily of R12 and R30. This resistor
pair also causes a 2X attenuation of
the input signal as seen
at the gate of 032 A and B. C24 serves to compensate the
input stage and
Cl0 compensates the lOX attenuator.
CR27 and CR28 protect 032 from excessive input signal
by clamping the gate if the signal at the input connector
exceeds approximately plus
or minus 2.5 volts. The signal
at the source of 032 is coupled through emitter follower
037 to the base of 041. 041 is another emitter follower,
which drives U60. The signal at pin 7 of U60 is terminated
in approximately 50 ohms by R46 to preserve the
high-frequency characteristics.
R49 sets
the DC level at pin 10 of U60, which is the
negative side
of the external trigger differential input. This
serves
to match the DC balance of the external trigger input
of U60 to that of the internal trigger input.
Balanced-To-Single-Ended Converter.
071, 078, and
075 convert the balanced (push-pull) output of U60 to a
single-ended signal at
the emitter of 075.
The trigger signal through U60 causes a decrease in
current into pin 12 from R77 and R78 and an increase in
current into pin 13 from R71. This would normally cause
the voltage at pin 12 to swing in a positive direction, while
pin 13 goes in a negative direction. However, the current
through R77 and R78 actually increases
due to the
feedback via R79 and 078, causing the voltage at pin 12 to
swing negative along with pin 13. 078 is connected as a
diode and
is enclosed in the same heat-sink with 071,
providi ng good DC stabiIity.
Trigger Coupling. When
DC coupling is selected by the
front panel COUPLING switch, 086 is turned on by the
+15 volt supply through R92, S95, and R86 to its base. The
triggering signal
is then coupled through R80 and 086 to
the base of 0100.
084 is turned on when AC coupling is selected. The
triggering signal
then passes through 084 and C87 to the
base of 0100. For AC LF REJ coupling, 084 is off and the
triggering signal is coupled through C88 and C87 to
attenuate low frequency signals.
For
AC HF REJ coupling, both 084 and 082 are turned
on.
The high-frequency components are coupled through
®

082 and C83 to ground, while the desired triggering
component is coupled through 084 and C87 (as in AC
coupling).
Trigger Generator
The trigger generator consists of the Slope Selector and
Level Comparator, Trigger Tunnel Diode and Driver,
Triggered
Lamp multi, TRIG'D Lamp Driver, Trigger
Generator Count Interval Schmitt, Events Schmitt, and
Events and
Count Coincident Gate.
Slope Selector and Level Comparator. This stage com-
prises 0100, 0102, 0117, 0121 and 0124. 0100 and
0102 are connected as a differential comparator. The
reference voltage for the comparator is selected by the
setting of the LEVEL control, Rll1. The internal DC
Balance adjustment, R77, sets the level at the base of 0100
so that the delaying counter is triggered at the zero-volt
point of the incoming trigger when the LEVEL control is
set to the center of the positive or negative slope region.
The LEVEL control varies the voltage on the base of 0102
to select the point on the trigger signal where triggering
occurs.
R1
04 establishes the emitter current for 0100 and
0102. Prior to the arrival of a trigger signal, with the
LEVE L control set to the center of the positive or negative
slope, 0100 and 0102 are passing equal currents.
Assume
that a positive-going signal is applied to the EXT
TRIG IN connector and that the LEVEL/SLOPE control is
set to zero on the positive slope.
The signal at the EXT TRIG IN connector is inverted by
the trigger preamp, appearing at the base of 0100 as a
negative-going signal. This will cause a decrease
in current
through 0100, and because of the common emitter source,
Rl04, the current through 0102 will increase. The de-
creased collector current of 0100 biases 0121 in a reverse
direction, while 0117 becomes more forward biased due to
the increased current through 0102.
With the SLOPE switch (S2) in the + position, the
cathode of CR 126 is grounded, forwar"d biasing CR 126,
which reverse biases CR 129.
At the same time, the base of
0124 is at ground and 0124 is off. This causes CR122 to
be reverse biased and CR128 is forward biased through
0117. An increased current is appl ied through 0117 and
CR 128
to the trigger tunnel diode and driver circuit (see
Fig. 2-1).
When
the SLOPE switch is set to the -position, 0124
and CR122 are forward biased and CR128 is reverse biased.
REV. B, OCT. 1974
Theory of Operation-7Dl1 Service
CR
126 is reverse biased and CR 129 is forward biased so
that current flows through 0121 and CR129 to the trigger
tunnel diode and driver circuit.
Trigger Tunnel Diode and Driver.
The trigger tunnel
diode stage shapes the output of the comparator to provide
a trigger pulse with a fast leading edge.
Tunnel diode CR141 is quiescently biased so that it is in
its low-voltage state. Increased trigger current from 0117
and CR128 or 0121 and CR129 through R130, L 130, and
CR141 causes CR141 to switch to the high-voltage state.
The resulting fast-rise positive step is coupled through
emitter-follower 0143 to C182, C145, and C166 in the
auto multi and trigger generator circuits.
Trig'd Lamp Multi.
The Trig'd Lamp Multi stage in-
cludes 0183 and 0188. When no trigger is applied, 0183 is
off and C185 is charged to a positive level (at the collector
of 0183) determined by R184, R190, and R191. The base
of 0192 is more positive than the base of 0194, so 0194 is
conducting.
When a trigger is applied, 0183 and 0188 operate as an
emitter-coupled
monostable multi. 0183 is momentarily
turned on by the positive transistion coupled through
C182.
The collector of 0183 drops and C185 discharges
through R185, turning off 0188. This holds 0183 on for a
period
determined by the charging time-constant of C185.
If the trigger signal has a repetition rate of 20-hertz or
greater,
0183 stays on (see Fig. 2-2). With 0183 on, 0192
is also conducting and 0194 is off.
TRIG'D Lamp Driver. During
the time that 0183 is on,
the increased drop across R 184 forward biases 0192. This
turns on 0198, which drives the TRIG'D lamp, DS197.
Trigger Generator.
The trigger generator includes 0149,
0159, CR169, and CR171. The function of this circuit is to
supply a fast-rise trigger signal to the Count Interval
Schmitt. For normal triggering, this signal is developed after
receipt
of a fast-rise transition from the trigger tunnel diode
and driver stage, except during holdoff.
For the following discussion of operation, assume that a
trigger signal is applied to the EXT TRIG IN connector.
The positive-going transition at the emitter of 0143 is
coupled through C182, causing the TRIG'D lamp, DS197
to be energized as previously described.
2-3

+ 15 V
0,00
}-f------ .JVw -r-+<: R",
- 15V
C102
,
L ____ _
Rl04
-15V
CRl26
- - - - -i LEVEL/SLOPE f- J
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0143

TRIGGER AT
BASE OF 0183
COLLECTOR OF 0183
Fig. 2-2. Auto Multi input and output waveforms with trigger signal
applied.
CR169 and CR171 are both in their high states until the
holdoff signal switches them to the low state. The holdoff
signal
is a positive pulse which forward biases both 0149
and 0159. When these transistors are forward biased, they
divert current from CR171 and CR169, which causes the
tunnel diodes to switch to their low states.
The next trigger after holdoff appears as a positive
transition
at C 145 and C166. The positive transition,
coupled through
R166 and R168 causes CR169 to switch
to its high state. This higher level, through R170, brings
CR171
up to near its switching current. The positive
transition
is also coupled through C145 and R145; and,
after 3.5 nanoseconds of delay, through R 154 and CR 171.
The short delay ensures that CR169 has had time to switch
to its high state, armin!,l CR171 before arrival of the
switching signal at CR171. This prevents extraneous noise
from prematurely activating
CR171. CR171 then switches
to its high state.
The fast rise positive trigger from CR171 is coupled to
the base of 0351 of the fine delay circuit through 0173.
Events Count Mode_ The signal output of CR 141 is used
for events counting.
The output of CR141 is coupled
REFERENCE
FREQUENCY
-
-PHASE
FILTER
DETECTOR
..
~
Theory of Operation-7D11 Service
through a level shifting
Schmitt trigger, 0133 and 0138, to
an input to U640D. To ensure that events are counted only
when holdoff is not present, the output of CR 171 is also
coupled
to an input to U640D through the level shifting
Schmitt trigger formed by 0173 and 0178. Therefore,
U640D is enabled, during the absence of hold off, to output
the events count pulses to 0512, the Events Count Source
Gate.
PHASE LOCK LOOP ~
ANDGATEDCOUNTDOWN~
The phase lock loop and gated countdown circuits
provide
the very accurate time count for the 7D11. In
addition to supplying the timing signal, this circuitry also
provides
the fine delay.
Phase Lock Loop
The phase lock loop is a method of generating a
frequency
that is some multiple of an incoming (reference)
frequency.
The 7n counter divides the local VCO frequency
by some integral number, n.
The phase detector compares
the phase of an incoming signal (see Fig. 2-3) with that of
the divided down local voltage controlled oscillator (VCO)
and generates a voltage proportional to the phase differ-
ence. This voltage is then filtered to remove ripple at the
frequency of phase detection and is applied to the voltage
controlled oscillator
to correct any phase difference. Phase
lock
is established when the reference and divided down
VCO frequencies are constant in phase shift. The local
oscillator frequency
is then an exact multiple (n) of the
reference with the same stability characteristics.
Y200 is a five-megahertz crystal-controlled oscillator. Its
output is routed through U205, where it is divided by five
and presented
to count mode switch 8210 as a one-
megahertz signal for internal timing. If external timing is
selected, the external one-megahertz signal is processed
through
0225 and 0227 to S210. The one-megahertz signal
is then routed from S210 to Phase Detector U230 where it
is compared with the one-megahertz frequency derived
VOLTAGE
-
CONTROLLED
OSCILLATOR
7n
-
Fig. 2-3. Voltage Controlled Oscillator in Phase Locked Loop.
® 2-5

Theory of Operation-7D11 Service
from
the 500-megahertz VCO_ Any phase difference
between the
two signals is detected and presented to error
amplifier U240. U240 presents a correction voltage to
varicap CR252, in parallel with the tank circuit of the
500-megahertz voltage controlled oscillator.
R247, R248, R249, and CR248 form a correction
network
to compensate for the non-linear characteristics of
the varicap. The 500-megahertz voltage-controlled oscillator
is a modified Colpitts configuration. The tank circuit is
formed by L253, integrated into the etched circuit board,
plus CR252, C253, C258, C259, and C260.
The output of the 500-megahertz oscillator is directed
through buffer stage
0261 to the Countdown Buffer,
0383, and to the Phase Lock Buffer, 0265. The output of
0265, 500 megahertz, is applied to a synchronous 100-
megahertz Multi, CR271 and L271, where it is divided by
five. The resultant 100-megahertz signal then enters
the
Phase Lock Ring Counter through the Phase Lock Ring
Counter Driver formed by
0274 and 0277.
Phase Lock Ring Counter Driver. 0274 and 0277 are
connected as an emitter-coupled current switch_ The
output
of the Phase Lock Divide-by-Five Tunnel Diode Multi is
connected to the base of 0274. The output is taken from
the collector of 0277. When the tunnel diode output is HI,
0277 conducts and 0274 is turned off. The output at the
collector of 0277 is, therefore, in phase with the output of
the tunnel diode.
The Phase Lock Ring Counter,
0285 through 0312, also
divides the 100-megahertz signal by five. The operation of
the Phase Lock Ring Counter, except for the reset function,
is identical to the one formed by 0401 through 0424,
which is described later. The signal, which is now 20
megahertz, is routed from the ring counter through the
level shifter (0316, 0319, and 0324), to a 7 20 counter
made up
of U327 and U329. The 20-megahertz signal is
divided by two through U327 and divided by 10 through
U329
to provide a one-megahertz signal, which represents
the 500-megahertz VCO divided by 50. This one-megahertz
signal is then presented to Phase Detector U230, where it is
compared to the one-megahertz (reference frequency)
signal from U205. This feedback method provides the
means by which
the 500-megahertz oscillator is kept
exactly on frequency.
Fine Delay
To compensate for internal propagation delays of the
7D11, the delay time
is calibrated to provide the delay time
indicated by
the readout from the EXT TR I GIN connector
to the DLY'D TRIG OUT connector when R336 is set for
zero.
The fine delay circuit provides an additional 100
nanoseconds delay, adjustable by R336.
2-6
The fine delay stage is a variable pulse width multi. The
delay time is triggered by a pulse from the trigger circuit,
which allows
0364 to conduct for the length of the delay
interval. The trigger pulse formed by the shaping network;
C353, R353, R354, and CR354, interrupts the conduction
of 0356, which raises the base voltage of 0364 to a higher
level than that present at the base of 0347. The positive
transition
at the em itter of 0364 is fed back through C358
to the emitter of 0356. The amplitude of this transition is
dependent upon the relative voltage levels at the bases of
0347 and 0364. The level at the base of 0347 is
determined by the setting of the FINE DELAY control,
R336. C358 discharges through current source 0358
causing the voltage at the emitter of 0356 to drop. 0356
starts conducting as its emitter approaches zero volts, which
then causes
0364 to stop conducting to end the delay
interval.
When 0364 conducts, its collector voltage drops (nega-
tive-going pulse edge-fine delay interval start) then returns
to its normal level (positive-going pulse edge-end of delay
interval) as determined by
the setting of R336. The
positive-going edge of
the pulse is shaped by CR364, R365,
and C366, and routed
to CR370 in the Time Count SWitch.
Gated Countdown
The stage, composed of CR370, 0371, and 0375 in
conjunction with CR386, L378, R377, and R378, form a
gated 100-megahertz oscillator. As
CR370 triggers to its
high state, it trips the
Schmitt trigger formed by 0371 and
0375, allowing CR386 to be biased in its astable region and
operated as a 100-megahertz multivibrator. Within two
nanoseconds,
CR386 "Locks" onto the first available
500-megahertz cycle, effectively dividing the 500-mega-
hertz signal by five. Because the trigger can occur at any
time, a one-count (two nanosecond) uncertainty
is present
in the time required to start dividing down the 500-mega-
hertz reference.
Gated Ring Counter Driver.
0388 and 0391 are con-
nected as an emitter-coupled amplifier to provide isolation
and level shifting for driving the ring counter. When the
tunnel diode output is HI, 0391 conducts and 0388 is
turned off. Therefore, the output at the collector of 0391
is in phase with the output of the tunnel diode.
Gated Ring Counter. The Gated Ring Counter
is made
up
of five DC coupled multivibrators. Each multivibrator
(multi) receives
the input signal, however, the ring counter
configuration
is such that an input will change the state of
only one multi. In turn, this conditions the succeeding
multi to respond to the next input, etc. A simplified
diagram of the ring counter is shown in Fig. 2-4. Each multi
is made up of two transistors. The multis are identified in
Fig. 2-4(A) as multi A, 0401 and 0404; multi B, 0406 and
®