Tektronix 7D15 User manual
Tektronix, Inc.
P.O. Box
500
Beaverton, Oregon
97077
INSTRUCTION M.ANUAL
Serial Number
First Printing SEP
1974
Scans by ArtekMedia © 2007
Tektronix,
Inc.
P.O. Box
500
Beaverton, Oregon
97077
070-1433-00
TEKTRCNI~
7015
UNIVERSAL
COUNTER/TIMER
INSTRUCTION
MANUAL
Serial Number
First
Printing
SEP
t97
4
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ontents
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rm withc
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mayno
lission o
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WARRANTY
All
TEKTRONIX
instruments
are
warranted
against
defective
mater
ials
and
workmanship
for
on
e year.
Any
questions
with
respect
to the
warranty
should
be taken
up
with
your
TEKTRONIX
Field
Engineeror
representative.
All
requests
for
repairs
and
replacement
parts
should
be
directed
to
the
TEKTRONIX
Field
Office
or
representative
in
your
area.
This
will
assure
you
the fastest
possible
service. Please in
clude
the
instrument
Type
Number
or
Part
Number
and
Serial
Numb
er
with
all
requests
for
parts
or
service
.
Specifications
and
price
change
privileges
reserved.
Copyright
t;
1974 by
Tektronix
,
Inc
.,
Beaverton,
Oregon
.
Print
ed in the
United
States
of
Americ
a.
All
rights
reserved.
Contents
of
this
publication
may
not
be r
epro
duced
in
a
ny
form
without
permission
of
Tektronix
,
Inc.
U.S.A. a
nd
foreign
TEKTRONIX
product
s
covered
by
U.S. and
foreign
patents
and/
or
patents
pending
.
TEKTRONIX
is a
registered
trademark
of
Tektronix
,
Inc
.
TABLE
OF
CONTENTS
SECTION
1
SPECIFICATION
Introduction
Electrical Characteristics
Environmental Characteristics
Physical Characteristics
SECTION
2
OPERATING INSTRUCTIONS
Installation
Front Panel Controls and Connectors
Modes of Operation
Operation and Checkout
SECTION
3
CIRCUIT DESCRIPTION
introduction
Block Diagram Description
Generai
input
Clock
Gate
Counters and Readout
Reset
Trigger Input Amplifiers
Time Base
Arm Inputs
Reset Circuitry
Readout Theory
Generai
CH
1
Column and Row Data
CH
2
Column and Row Data
Overflow
-5
v
Supply
SECTION
4
MAINTENANCE
introduction
Preventive Maintenance
Troubleshooting
Corrective Maintenance
Component Replacement
RecalibrationAfter Repair
SECTION
5
CALIBRATION
introduction
Test Equipment Required
Caiibration Procedure
Index to Caiibration Procedure
SECTION
6
ELECTRICAL PARTS LIST
Abbreviations and Symbols
SECTION
7
DIAGRAMS AND CIRCUIT BOARD ILLUSTRATIONS
Symbols and ReferenceDesignators
SECTION
8
MECHANICAL PARTS LIST
CHANGEINFORMATION
Page
1-1
1-1
1-7
1-7
Scans by ArtekMedia © 2007
7015
TABLE OF
CONTENTS
SECTION 1 SPECIFICATION Page
Introduction
1-1
Electrical Characteristics
1-1
Environmental Characteristics 1-7
Physical Characteristics 1-7
SECTION 2 OPERATING INSTRUCTIONS
Installation
2-1
Front Panel Controls and Connectors 2-2
Modes
of
Operation 2-7
Operation and Checkout 2-10
SECTION 3 CIRCUIT DESCRIPTION
Introduction
3-1
Block
Diagram Description
3-1
General
3-1
Input
3-1
Clock
3-1
Gate 3-2
Counters and Readout 3-7
Reset 3-7
Trigger
Input
Amplifiers 3-8
Time Base 3-8
Arm Inputs 3-9
Reset
Circuitry
3-9
Readout Theory 3-10
General 3-10
CH 1 Column and Row Data 3-10
CH 2 Column
and
Row Data 3-12
Overflow 3-13
-5
V Supply 3-14
SECTION 4 MAINTENANCE
Introduction
4-1
Preventive Maintenance
4-1
Troubleshooting
4-1
Corrective Maintenance 4-3
Component Replacement 4-4
Recallbratlon After Repair 4-4
SECTION 5 CALIBRATION
Introduction
5-1
Test Equipment Required
5-1
Calibration Procedure 5-4
Index to Calibration Procedure 5-5
SECTION 6 ELECTRICAL PARTS LIST
Abbreviations and Symbols
SECTION 7 DIAGRAMS AND CIRCUIT BOARD ILLUSTRATIONS
Symbols and Reference DeSignators
SECTION 8 MECHANICAL PARTS LIST
CHANGE INFORMATION
@
Fig.
1-1.
7D15
Universal CounterITimer.
@
Scans by ArtekMedia © 2007
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E
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7015
Fig. 1·1. 7
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@
Section
1-7D15
SPECIFICATIONS
Introduction
The 7D15
is
a digital counter plug-in designed for use with
all
readout-equipped7000-SeriesOscilloscopemainframes.
It
will function in any plug-in compartment; however, in the vertical compartment, a selectable display
is
internally con-
nectedtothe oscilloscope. When used inthe horizontal compartment,mainframetriggers are available tothe 7D15.
The 7D15 has eight modes of operation: Frequency-DC to 225 MHz direct, Frequency Ratio-0 to
lo5
:1, Period-
10ns to
lo5
s,
Period Averaging- 10ps resolution,TIM- 10ns to
lo5
s,
TIM Averaging-I ns accuracy, Totalize-I to
lo8
events, Manual Stop Watch-to 10'
S.
The electrical specifications listed in the Performance Requirement column are valid over the stated environmental range
for instruments calibrated at an ambient temperature of +20°c to +30°c and after a five minute warmup unless otherwise
noted. The electrical specifications listed in the Supplemental Information column indicate typical instrumentoperationand
is not intendedto be construedas
a
requirement for proper instrumentoperation.
,
TABLE
1-1
ELECTRICAL CHARACTERISTICS
Refer to Figs.
1-2
through
1-7
at the rear of this section for additional accuracy information.
Characteristics
MEASUREMENT MODES
Frequency Mode
Range
Resolution
'
Accuracy
PeriodMode
Range
Resolution
'
Accuracy
Time Interval Mode
Range
Resolution
'
Accuracy (nominal)
Performance Requirement
DC to 225 megahertz
0.1 hertz minimum
Efreq (hertz)
=
*
TB X Fin
f
1IT
Efreq
(%)=
100% +TB+-
[
T X Fin
'
I
10 nanoseconds to
lo5
seconds with averaging times of XI to XI000 in decade
steps.
10 picoseconds maximum.
1
x
10-9
+
K
*
pCk
Eper (sec)
=
*
TB X Pin
+
M
[
*1X10-9*K*Pck
Eper
(%)
=
100%
+
TB
+
Pin X M
I
6
nanoseconds to
lo5
seconds with averaging times of X1 to X1000.
0.1 nanosecondusable.
ETI (sec)
=
TB
X
Pin
+
(pck/4~)
*
*
K
(~~~14~)
+
10-9
+
K
ETI
(%)
=
100%
+
TB
f
Pin
The complete expression for Time Interval averaging depends on signal to noise
ratio and statisticaldistribution factors.
Scans by ArtekMedia © 2007
Section
1-7015
SPECIFICATIONS
Introduction
The
7D15
is
a digital counter plug-in designed
for
use
with
all readout-equipped 7000-Series Oscilloscope mainframes.
It
will
function
in any plug-in compartment; however, in the vertical compartment, a selectable display
is
internally con-
nected
to
the oscilloscope.
When
used
in the horizontal compartment, mainframe triggers
are
available
to
the 7D15.
The
7D15
has
eight modes
of
operation:
Frequency-DC
to
225 MHz direct, Frequency
Ratio-O
to
105 :1,
Period-
10
ns
to
105
s,
Period
Averaging-
10
ps
resolution,
TlM-
10
ns
to
105
s,
TIM
Averaging-1
ns
accuracy,
Totalize-1
to
108
events, Manual Stop
Watch-to
105 S.
The electrical specifications listed in the Performance Requirement column
are
valid over the stated environmental
range
for
instruments calibrated at
an
ambient temperature
of
+20°C
to
+30°C and after a five minute warmup unless otherwise
noted. The electrical specifications listed in the Supplemental
Information
column indicate typical instrument operation and
is
not
intended
to
be
construed
as
a requirement
for
proper instrument operation.
Characteristics
MEASUREMENT
MODES
Frequency Mode
Range
Resolution
1 Accuracy
Period Mode
Range
Resolution
1 Accuracy
Time Interval Mode
Range
Resolution
1 Accuracy (nominal)
TABLE
1-1
ElECTR
ICAl
CHARACTERISTICS
Performance Requirement
DC
to
225 megahertz
0.1
hertz
minimum
Efreq (hertz) = ± TB X Fin ± 1/T
Efreq
(%)
= 100%
[±
TB ±T X1FinJ
10 nanoseconds
to
105 seconds
with
averaging times
of
X1
to
X1000 in decade
steps.
10 picoseconds maximum.
_
1X10-
9
±K±P
ck
Eper
(sec)
- ±
TB
X Pin ±
-----:-M:----=>-
Eper
(%)
= 100%
f±
TB + ± 1 X
10-
9 ± K ±
pckl
L Pin X M J
6 nanoseconds
to
105 seconds
with
averaging times
of
X1
to
X 1000.
0.1
nanosecond usable.
ETI
(sec)
= TB X Pin ±
(Pck/VM)
±
10-
9 ± K
(Pck/VM)
±
10-
9 ± K
ETI
(%)
=100% ± TB ± Pin
The complete expression
for
Time Interval averaging depends on signal
to
noise
ratio and statistical
distribution
factors.
1 Refer
to
Figs. 1-2
through
1-7
at
the
rear
of
this
section
for
additional
accuracy
information.
@
1-1
TABLE
1-1
(cont)
NOTE
Characteristics
Frequency Ratio
CH B/EXT clock
Range
Totalize, CH
B:
Range
Manual Stop Watch
Range
Formulas given where
TB
(dec
%)
is the time base accuracy; Pin is the period or time interval of the unknown
signal (whichever is applicable);
M
is the number ofaverages taken; Pck is the measurementclock period;
T
is the
gate time; Fin is the frequency of the unknown signal; Enpk is equal to thepeak noise amplitude at the input to
thecounter gate circuit; dv/dt is the signalslopeat the input to thegate;
K
is equal to2Enpk/dv/dt.
PerformanceRequirement
lo-'
to
lo4
0
to
lo8
counts
(ManualON-OFF control or electrical control from CH A.)
0
to
1
O5
seconds
SupplementalInformation
E max
=
20
+
180
(1
-
Fin(MHz)/200
Characteristics
INPUTSIGNALS CH A
&
B
Frequency Range (CH Bonly)
DC Coupled
AC Coupled
Sensitivity
CH A
&
B
Inputs
TRIG SOURCE
Input Resistanceand
Capacitance
Minimum Pulse Width
Minimum gate "OFF" time
BetweenSamples During
TIM Averaging Operation
Maximum InputVoltage
Performance Requirements
DC to
225
megahertz
5
hertzto
225
megahertz
100
millivolts peak-to-peak
0.5
divisionsof vertical deflection derated
at higher frequencies.
Approximately
1
megohm,
22
picofarads
5
nanoseconds
10
nanoseconds
200
volts DC linearly derated to
20
volts
at
200
megahertz
Scans by ArtekMedia © 2007
Specifications-7D15
Characteristics
Frequency Ratio
CH
B/EXT clock
Range
Totalize,
CH
B:
Range
Manual
Stop
Watch
Range
TABLE
1-1
(conti
Performance Requirement
10-
7
to
104
o
to
108 counts
(Manual
ON-OFF
control or electrical control from
CH
A.)
o
to
10
5 seconds
NOTE
Formulas given where
TB
(dec %)
is
the time base accuracy;
Pin
is
the period or time interval
of
the unknown
signal (whichever
is
applicable); M
is
the number
of
averages taken; Pck
is
the measurement clock period; T
is
the
gate time;
Fin
is
the frequency
of
the unknown signal; E
npk
is
equal
to
the peak noise amplitude
at
the input
to
the counter gate circuit; dv/dt
is
the signal slope
at
the input
to
the gate; K
is
equal
to
2E
np
k/
dv/dt.
Characteristics Performance Requirements Supplemental Information
INPUT SIGNALS
CH
A & B
Frequency Range
(CH
Bonly)
DC
Coupled
DC
to
225
megahertz
AC
Coupled 5 hertz
to
225 megahertz
Sensitivity
CH
A & B Inputs 100 millivolts peak-to-peak
TRIG SOURCE 0.5 divisions
of
vertical deflection derated
at
higher frequencies.
Input Resistance and Approximately 1
megohm,22
picofarads
Capacitance
Minimum Pulse Width 5 nanoseconds
Minimum gate
"OFF"
time 10 nanoseconds
Between Samples During
TIM
Averaging Operation
Maximum Input Voltage
200
volts
DC
linearly derated
to
20
volts E max =
20
+ 180
(1
-Fin(MHz)/200
at
200
megahertz
1-2 @
Specifications-7D15
TABLE
1-1(cont)
Supplemental
l
nformation
10
nanoseconds
Characteristics
Minimum Signal Period in
"PER" Mode
Minimum CH A Input Pulse
Width in "FREQ B-CHA
Gate" Mode
Triggering
Preset Position
Level Control
Range: (CH A and CH B)
Range: TRIG SOURCE
Arming Inputs
Input R and C
Lead Time for Pulse to
become effective
Lead Time to Negate
effect of "ARM"
Minimum rise and fall rate
Sensitivity A ARM
BARM
Maximum Operating Voltage
Maximum Input Voltage
External Clock In
Input Requirements
Minimum Amplitude
Coupling
Performance Requirements
10
nanoseconds
Automatically triggers at
0
volts
.I
V,
f500
millivolts;
1
V,
f5
volts;
10
V,
+50
volts
Approximately
f2.5
divisions
Approximately
10
kilohm,
20
picofarads
5
nanoseconds
5
nanoseconds
dv/dt
2
10
Volts per microsecond
A logical
"1"
occurswith either no signal
applied or with
+0.5
volt or greater. A
logical
"0"
occurswith less than
+0.2
volt
@
I
sink
<
0.2
milliampere
Logic
"1"
<
0.2
volt or no signal applied
Logic
"0"
2
+0.5
volt
+I0
volts to
-5
volts
*I5
volts
Internal switch selectable
0.8
volt peak-to-peak sine wave or pulse
with
30%
to
70%
duty cycle
AC
Scans by ArtekMedia © 2007
Specifications-7D15
TABLE
1-1
(cont)
Characteristics Performance Requirements Supplemental
Information
Minimum
Signal Period in 10 nanoseconds
"PE
R"
Mode
Minimum
CH
A
Input
Pulse 10 nanoseconds
Width in
"FREQ
B-CH A
Gate"
Mode
Triggering
Preset Position
Automatically
triggers at avolts
Level
Control
Range: (CH A and
CH
B)
.1
V,
±500
millivolts;
1
V,
±5
volts; 10
V,
±50
volts
Range:
TRIG
SOURCE
Approximately
±2.5 divisions
Arming
Inputs
Input
Rand
C
Approximately
10
kilohm,
20
picofarads
Lead
Time
for
Pulse
to
5 nanoseconds
become effective
Lead
Time
to
Negate 5 nanoseconds
effect
of
"ARM"
Minimum
rise and fall rate
dv/dt;;;'
10
Volts
per microsecond
Sensitivity A
ARM
A logical
"1"
occurs
with
either no signal
applied
or
with
+0.5
volt
or
greater. A
logical
"0"
occurs
with
less
than +0.2
volt
@ I sink';;;; 0.2 milliampere
BARM
Logic
"1"
,;;;;
0.2
volt
or no signal applied
Logic
"0"
;;;.
+0.5
volt
Maximum
Operating Voltage +10 volts
to
-5
volts
Maximum
Input
Voltage
±15
volts
External Clock
In
Input
Requirements Internal switch selectable
Minimum
Amplitude
0.8
volt
peak-to-peak sine wave
or
pulse
with
30%
to
70%
duty
cycle
Coupling AC
@ 1-3
Specifications-7D
15
TABLE
1-1
(cont)
SupplementalInformation
Negative-goingtransition TTL compatible
pulse
<
100 nanoseconds
2
500 nanoseconds
TTL compatible, negative-logicsignal
<
200 nanoseconds
<
100 nanoseconds
Characteristics
Maximum lnput Voltage
Frequency Range
RESET-Front Panel
Input Rand
C
lnput Requirements
Amplitude
Pulse Width
MaximumOperating
lnput Voltage
Rise and Falltime
Maximum lnput Voltage
Reset (locatedon Rear
Interface B13)
Rise and Falltime
Width
Hold Signal (locatedon
Rear lnterface 822)
Rise and Falltime
Propagation Delay for
Signal to become
effective or ineffective
PerformanceRequirements
+50 volts
DC,
20 volts peak-to-peak
1 megahertz *5%; Phase Lock Opera-
tional. 10 nanoseconds, 100 nanoseconds
clock available.
20 hertz to 5 megahertz; Phase Lock
Nonoperational.
Reset initializes the instrument. All
counters are affected, includingaveraging
circuits.
Approximately 10 kilohms, 30 picofarads
Logic "1"
+
2 volts or greater
Logic "0"
+
0.5 volt or less
2
500 nanoseconds
+10 volts to -10 volts
100 nanoseconds or less
+
15volts
Scans by ArtekMedia © 2007
Specifications-7D
15
TABLE 1-1 (cont)
Characteristics Performance
Requirements
Supplemental
Information
Maximum
Input
Voltage
±50
volts DC,
20
volts peak-to-peak
Frequency Range 1 megahertz ±5%; Phase Lock Opera-
tional.
10
nanoseconds,
100
nanoseconds
clock available.
20
hertz
to
5 megahertz; Phase Lock
Nonoperational.
RESET
-Front
Panel Reset initializes
the
instrument.
All
counters
are
affected,
including averaging
circuits.
Input
Rand
C
Approximately
10 kilohms,
30
picofarads
Input
Requirements
Amplitude Logic
"1"
+ 2 volts
or
greater
Logic
"0"
+
0.5
volt
or
less
Pulse Width ~
500
nanoseconds
Maximum Operating
+10
volts
to
-10
volts
Input
Voltage
Rise and Falltime
100
nanoseconds
or
less
Maximum
Input
Voltage
±15volts
Reset (located
on
Rear Negative-going transition
TTL
compatible
Interface B13) pulse
Rise
and
Falltime
:;;;;
100
nanoseconds
Width
~
500
nanoseconds
Hold Signal (located
on
TTL
compatible,
negative-logic signal
Rear Interface B22)
Rise and Falltime
:;;;;
200
nanoseconds
Propagation Delay for
:;;;;
100
nanoseconds
Signal
to
become
effective
or
ineffective
1-4 @
TABLE
1-1
(cont)
Characteristics
.
INTERNALTIME BASE
Crystal Oscillator
Frequency
Accuracy
O"C
to +50°c
LongTerm Drift
OUTPUTSIGNALS
Monitor Signals
Clock Out
A and BTrigger Level
Externally Programable
with +5 volt Signal
maximum and inthe
Preset Position
Analog Display (Internally
Connected)
Position
Amplitude
Rise and Falltime
Propagationdelay: Input
BNC's to plug-ininterface
PerformanceRequirements
Within 0.5 part per million
1part or less in
lo7
per month
Logic "1"
=
+0.5 volt *lo% into 50 ohms
Logic "0"
<
0 volt into 50 ohms. TTL
compatible without 50 ohm load (1.6
milliamper current capacity)
ZOut
%
1kilohm
VOut
=
+0.5 volt into
1
megohm
(10X scaling)
Front panel switch selects either "True
Gate" signal, "Pseudo Gate", or "Channel
"B" out
Controlled by front panel screwdriver
control
1.0 division. Can be set from 0.2 to 1div
+20%.
Less than 2 nanoseconds
Supplemental Information
5 megahertz
ZOut 430 ohms
The Pseudo Gate signal is
a
high-speed
representationof the 7D15 gate signal
Changed by resistor alteration
True Gate:
%
20 nanoseconds
Pseudo Gate:
x
18nanoseconds
CH
B:
x
16nanoseconds
Scans by ArtekMedia © 2007
Specifications-7D15
TABLE
1-'
(cont)
Characteristics Performance
Requirements
Supplemental
Information
INTERNAL TIME BASE
Crystal Oscillator
Frequency
5 megahertz
Accuracy
O°C
to
+50°C
-Within
0.5
part
per million
Long
Term
Drift 1
part
or
less
in
107 per
month
OUTPUT SIGNALS
Monitor Signals
Clock
Out
Logic
"1"
=+0.5 volt ±10%
into
50
ohms
Zout
430
ohms
Logic
"0"
.;;;;
0 volt into
50
ohms.
TTL
compatible
without
50
ohm
load (1.6
milliamper
current
capacity)
A and B Trigger Level
Zout"'"
1 kilohm
V
out
=±0.5 volt into 1 megohm
Externally Programable (lOX scaling)
with
±5
volt Signal
maximum
and
in
the
Preset Position
Analog Display (I nternally
Front
panel switch selects
either
"True
The
Pseudo Gate signal
is
a high-speed
Connected)
Gate"
signal,
"Pseudo
Gate",
or
"Channel
representation
of
the
7D15
gate signal
"B"
out
Position Controlled by
front
panel screwdriver
control
Amplitude 1.0 division. Can be set from
0.2
to
1 div Changed by resistor
alteration
±20%.
Rise and Falltime Less
than
2 nanoseconds
Propagation
delay:
Input
True
Gate:
"'"
20
nanoseconds
BNC's
to
plug-in interface Pseudo Gate:
"'"
18
nanoseconds
CH
B:
"'"
16
nanoseconds
@ 1-5
Specifications-7D15
TABLE
1-1(cont)
SupplementalInformation
Matches to within
1
nanosecond;depends
on correct calibration of horizontal time
base used
>
I
nanosecond
True Gate:
x
21
nanoseconds
Pseudo Gate:
el9
nanoseconds
CH B
x
17
nanoseconds
Matchesto within
1
nanosecond
Nominally TTL compatibility, positive
logic
100
nanoseconds maximum
150
nanoseconds maximum
A LED lamp indicates internal gate
condition
Continuously variable from
0.1
second or
less
to approximately
5
seconds. With
control in maximum clockwise position,
the display
is
held indefinitely
Characteristics
Displayedgate width to
"effective" gate width
In"Freq" or "events":
operation, lead time required
of gate display over CH
B
display toguarantee
proper accumulationor
non-accumulationof count.
External Display
Amplitude
Rise and Falltime
Propagationdelay from
input BNC's to display
"True Gate"
&
"Pseudo
Gate" output pulsewidth
to "Effective Gate"
Busy Signal (locatedon
Rear InterfaceA22)
Rise and Falltime
Delay After Reset Command
DISPLAYS
Gate Indicator
Display ModeSwitch
Display Time Control
Performance Requirements
Located on front panel, same as "analog
display" except position and amplitude
controls have no effect
Logic
"1"
=
+0.5
volt
+lo%
into
50
ohms.
Logic
"0"
d
0
volt into
50
ohm TTL
compatible without
50
ohm load
(1.6
milliamper current capability)
2
1.5
nanosecondswith
50
ohm load
Front panel switchallows selection
of readout "follow or store"
Scans by ArtekMedia © 2007
Specifications-7D15
TABLE
1-1
(cont)
Characteristics Performance Requirements Supplemental Information
Displayed gate width
to
Matches
to
within 1 nanosecond; depends
"effective" gate width on correct calibration of horizontal time
base used
In
"Freq"
or
"events":
;;;;.
1 nanosecond
operation,
lead
time
required
of gate display over
CH
B
display
to
guarantee
proper accumulation or
non-accumulation of
count.
External Display Located on
front
panel, same
as
"analog
display" except position and amplitude
controls have no effect
Amplitude Logic
Ul"
'"
+0.5 volt ±10% into
50
ohms.
Logic
"0"
.;;;;
0 volt into
50
ohm
TTL
compatible
without
50
ohm
load (1.6
milliamper
current
capability)
Rise and Falltime
;;;;.
1.5 nanoseconds with
50
ohm
load
Propagation delay from True Gate:
""
21
nanoseconds
input BNC's
to
display Pseudo Gate: ""19 nanoseconds
CH
B""
17
nanoseconds
"True
Gate"
& "Pseudo Matches
to
within 1 nanosecond
Gate"
output
pulse width
to
"Effective
Gate"
Busy Signal (located
on
Nominally TTL compatibility, positive
Rear Interface A22) logic
Rise and Falltime
100
nanoseconds maximum
Delay After Reset Command
150
nanoseconds maximum
DISPLAYS
Gate Indicator A LED lamp indicates internal gate
condition
Display Mode Switch
Front
panel switch allows selection
of
readout "follow or
store"
Display Time Control Continuously variable from 0.1 second or
less
to
approximately 5 seconds. With
control
in
maximum clockwise position,
the
display
is
held indefinitely
1-6 @
Specifications-7D
15
TABLE
1-1
(cont)
Readout
Resolution, Minimum
SupplementalInformation
.
Characteristics
8
digits of display, the four most signifi-
cant digits have zero suppression.
Overflow by
">"
arrow. Legend located
on Channel
2
of readout system
Performance Requirements
TABLE
1-2
Frequency
Per, TIM
Multi-per
Multi-TIM
ENVIRONMENTAL CHARACTERISTICS
Refer tothe specification for the associated oscilloscope.
0.1 hertz
10 nanoseconds
10 picoseconds
100picoseconds (limited)
TABLE
1-3
PHYSICALCHARACTERISTICS
Size
Weight
Fitsall 7000-Seriesplug-incompartments.
3.1 Pounds (1.4 kilograms)
Scans by ArtekMedia © 2007
Specifications-7D
15
TABLE 1-1 (cont)
Characteristics Performance
Requirements
Supplemental
Information
Readout 8 digits
of
display,
the
four
most
signifi-
cant
digits
have zero suppression.
Overflow
by">"
arrow.
Legend located
on
Channel 2
of
readout
system
Resolution, Minimum
Frequency 0.1 hertz
Per, TIM
10
nanoseconds
Multi-per
10
picoseconds
Multi-TIM
100
picoseconds (limited)
TABLE 1-2
ENVIRONMENTAL CHARACTERISTICS
Refer
to
the
specification for
the
associated oscilloscope.
TABLE 1-3
PHYSICAL CHARACTERISTICS
Size Fits all 7000-Series plug-in
compartments.
Weight 3.1 Pounds (1.4 kilograms)
@ 1-7
l
KHz
Fig.
1-2.
7D15
Frequency modeaccuracy stated
in
percent.
Scans by ArtekMedia © 2007
.0001%
"
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CALIBRATED
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I
KHz
10
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100
KHz
1
MHz
10
MHz
100
MHz
1
GHz
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Fig.
1-2_
7015
Frequency
mode
accuracy
stated
in percent_
CONDITIONS:
"USING INTERNAL OSCILLATOR
"INSTRUMENT CALIBRATEDWITHIN
SIX MONTHS
*INSTRUMEFT OPERATING WITHIN
O'C
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4
5.
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Frequency mode accuracy stated in hertz.
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1000
Hz
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1
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10
KHz
100
KHz
1
MHz
10
MHz
100
MHz
1 GHz
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FREQUENCY
Fig.
1-3.7015
Frequency
mode
accuracy stated
in
hertz.
'USING INTERNAL OSCILLATOR
'INSTRUMENT CALIBRATEDWITHIN
SIX MONTHS
'INSTRUMENT OPERATING WITHIN
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PS
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PS
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ms 10 ms 100 ms
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1-4.
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ns
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ns
100
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1 ms 10
ms
INPUT
PERIOD
Fig.
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Period
mode
accuracy
stated
in
percent.
!
C(
I
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ms
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10s
CLOCK
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ms
AVERG
=
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"USING INTERNAL OSCILLATOR
*INSTRUMENT CALIBRATEDWITHIN
SIX MONTHS
*INSTRUMENT OPERATING WITHIN
O'C
TO +50°c RANGE
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EXCEED EFFECTIVE COUNTER
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PS
100
/As
1
ms
10
ms
100
ms
INPUTPERIOD
Fig.
1-5. 7D15 Period mode accuracy stated
in
time.
Scans by ArtekMedia © 2007
@
....
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a:
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a:
w
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J,lS
CLOCK
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10
J,lS
AVERG
=
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CLOCK
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J,lS
AVERG
=
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1 J,lS
CLOCK
=
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ns
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=
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100
ns
CLOCK
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ns
AVERG
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X1
10
ns
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AVERG
=
X10
~
CLOCK
=
10
ns
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...
100
ps
CLOCK
=
10
ns
AVERG
=
X100
.,
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CLOCK
= 10
ns
AVERG
=
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10 ps
10
ns
100
ns
1
J,lS
100J,ls
1 ms
INPUT
PERIOD
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mode
accuracy
stated
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time
.
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Iii
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MONTHS
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OoC
TO
+50
oC
RANGE
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NOISE
LEVEL
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EFFECTIVE
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HYSTERESIS
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RISETIMES
ARE
AS EN-
COUNTERED
IN
TYPICAL
TTL
ENVIRONMENT
II
10 ms 100 ms 1 s 10 s
ONDITIONS:
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"INSTRUMENT CALIBRATED WITHIN
SIX MONTHS
'IYSTRUMENT OPERATING WITHIN
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CTO +50°c RANGE
"PEAK NOISE LEVELDOES NOT
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HYSTERESIS
*SYNCHRONIZATION DOES NOT
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ENCOUNTERED INTYPICAL
VlRONMENT
INPUTTIME INTERVAL
Fig.
1-6.
7D15
Time Interval mode accuracy stated inpresent.
Scans by ArtekMedia © 2007
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10
ns
100
ns
1
/J.S
100/J.s 1 ms 10 ms
100
ms 1 s
INPUT
TIME
INTERVAL
Fig.
1-6.7015
Time
Interval
mode
accuracy
stated
in
present.
*INSTRUMENT CALIBRATEDWITHIN
I~STRUME~T
OPERATING WITHIN
10
ns
o
c
TO
150
c
RANGE
'PEAK NOISE LEVEL DOES NOT
EXCEED EFFECTIVE COUNTER
HYSTERESIS
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OCCUR
Ill
I
1
,
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,
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1111111
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CLOCK
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ns
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COUNTERED
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TYPICAL
TTL
ENVIRONMENT
1
ns
1
ns
10
ns
100
ns
1
@S
10
ps
100
ps
1
rns
10
ms
100
ms
I
s
10
s
INPUT TIME INTERVAL
Fig.
1-7.
7D15
Time
Interval mode accuracy stated
in
time.
Scans by ArtekMedia © 2007
...
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1 ms
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11111
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1 ms
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CLOCK
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AVERG
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CLOCK
1
j.LS
AVERG
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100 ns
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X1
CLOCK
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CLOCK
10 ns
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CLOCK
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=
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100
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10
j.LS
100
j.Ls
1 ms
INPUT
TIME
INTERVAL
Fig.
1·7.7015
Time Interval
mode
accuracy stated in
time.
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~
·INSTRUMENT
CALIBRATED
WITHIN
SIX
MONTHS
~,..
"INSTRUMENT
OPERATING
WITHIN
Ot
~
"INSTRUMENT
OPE
RATING
WITHIN
~
aOc
TO
+50°C
RANGE
·PEAK
NOISE
LEVEL
DOES
NOT
EXCEED
EFFECTIVE
COUNTER
HYSTERESIS
"SYNCHRONIZATION
DOES
NOT
OCCUR
"SIGNAL
RISETIMES
ARE
AS
EN
COUNTERED
IN
TYPICAL
TTL
ENVI
RON
ME
NT
10 ms
100
ms 1 s 10 s
ArtekMedia
Digitally signed by ArtekMedia
Date: 2008.11.30 11:46:08 -06'00'
Section
2-7D15
OPERATING INSTRUCTIONS
GENERAL
The 7D15 Universal CounterfTimer plug-in unit operates with the readout system of
Tektronix 7000-series Oscilloscopes to measure frequency or frequency ratio, and to
totalize (count number of events).
To effectively use the 7D15, the operationand capabilities of the instrument must be
known. This section describes front-panel control functions and general information on
signal input connections.
Installation
The 7D15 is calibrated and ready for use as received.
It
can be installed inany com-
partment of Tektronix 7000-Series Oscilloscopes; however, if a displayed waveform
is
desired, it should be used in one of the vertical compartments. Mainframe triggers are
furnished the 7015when installedinahorizontal compartment.
To
install, align the upper and lower railsof the 7D15 with the oscilloscope tracks and
slide
it
in. The front panel will be flush with the front of the oscilloscope and the latch at
the bottom left corner will be in place against the front panel when the 7015
is
fully
installed. To remove, pull on the latch (inscribed with the unit identification "7D15")
and the 7015will unlatch. Continue pulling to slide the 7D15 out of the oscilloscope.
Scans by ArtekMedia © 2007
@
OPERATING
INSTRUCTIONS
GENERAL
The
7015
Universal Counter/Timer plug-in unit operates with the readout system
of
Tektronix 7000-series Oscilloscopes
to
measure frequency
or
frequency ratio, and
to
totalize (count number
of
events)_
To effectively use the
7015,
the operation and capabilities
of
the instrument must
be
known. This section describes front-panel control functions and general information on
signal input connections.
Installation
The
7015
is
calibrated and ready for use
as
received. It can be installed in any com-
partment of Tektronix 7000-Series Oscilloscopes; however,
if
a displayed waveform
is
desired, it should
be
used
in
one
of
the vertical compartments. Mainframe triggers are
furnished
the
7015
when installed
in
a horizontal compartment.
To
install, align
the
upper and lower rails
of
the
7015
with
the
oscilloscope tracks and
slide it in. The
front
panel will be flush with
the
front
of
the
oscilloscope and
the
latch
at
the
bottom
left corner will be
in
place against
the
front panel when
the
7015
is
fully
installed.
To
remove, pull on
the
latch (inscribed with
the
unit identification
"7015")
and
the
7015
will unlatch. Continue pulling
to
slide
the
7015
out
of
the
oscilloscope.
Section
2-7015
2-1
Operating Instructions-7D15
A TRIGGER
FRONT PANEL CONTROLS AND CONNECTORS
A InputConnector: When selected, provides a meansfor connectingthe trigger signal.
A ARMJack: Gates the A Input. A logical Logates the A lnputoff and a logical
Hi
gates the
A
lnputon.
SLOPE Switch: Selectswhether the positive- or negative-goingslope ofthe signal is to beused as a trigger. The
inward position of the SLOPE switch selects the positiveslope and the outward positionoftheSLOPE switch
selects the negative slope.
COUPL Switch: Selects the input coupling to be used. The outward position ofthe COUPL switch connects
boththe DCandAC component oftheA lnputtothe attenuator. The inward position allows only frequencies
above approximately
5
Hz
to pass.
1
P-PSENS
.1V, IV, 10VPositions: Selectsthe sensitivity ofchannel
A
trigger amplifier.
TRlG SOURCE Position: Selects the internal vertical amplifier trigger signal when installed inthe horizontal
compartment.
LEVEL Control: Controls the DC trigger level of the channel A trigger amplifier. The PRESET position
(LEVEL control fully clockwise) sets the DC trigger level to 0 volts.
TRlG LEVELJack: May beused to monitor the DCtrigger level or, when the P-P SENSswitch is inthe TRlG
SOURCE position, theTRlG LEVELjack can beused toexternally set the DCtrigger level.
1432-8
Figure
2-1
Scans by ArtekMedia © 2007
Operating I
nst
r
uctions
-7D15
FRONT
PANEL
CONTROLS
ANO
CONNECTORS
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COUNTER
/
TIMER
A TRIGGER
7015
2-2
A I
nput
Connector:
W
hen
sel
ected,
pro
v
id
es
a
means
for
connecting
the
trigger signa
l.
A ARM
Jack
:
Gates
the
A I
nput
. A 10gicaiLo gates
the
A I
nput
off
and a logical
Hi
gates
th
e A Inp
ut
on.
SLOPE
Switch:
Se
lects wheth
er
the
po
sitive-
or
negative-going slope
of
the
signal
is
to
be used as a trigger.
The
inward
posit
i
on
of
the
SLOPE switch sel
ects
the
positive sl
ope
and
the
outward
position
of
th
e SLOPE switch
sel
ects
the negative slope.
COUPL
Switch
:
Se
l
ects
the
input
coupling
to
be used.
The
outward
position
of
the
COUPL switch
connects
both
the
DC
and AC
component
of
the
A
Input
to
the
attenuator.
The
inward
po
sition allows
only
frequencies
above
approximately
5 Hl to pn
ss.
POp
SENS
.
1V,
lV,
10V
Position
s:
Selects
the sensitivity
of
channe
l A trigger amplifier_
TRIG SOURCE Position: Selects
the
internal vertical amplifier trigger signlll
when
installed in
the
horizonta
l
compartment.
LEVEL
Contro
l:
Controls
the
DC
trigger
lev
el
of
the
channel A trigger amplifier.
The
PRESET
position
(LEVEL
contro
l fu
ll
y clocl<wise) sets
the
DC
trigger level to 0 vo lts.
TRIG
LEVEL Jack: May be used
to
moni
t
or
the DC trigger level or, when
the
pop
SENS switch
is
in
the
TRIG
SOURCE position, the TR IG LEVEL jack can be used
to
exter
nally
se
t
the
DC
trigger
le
ve
l.
1432-8
Figure
2-1
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