TeleChips TCC720 User manual

USER’S MANUAL
TCC720
32-bit RISC
Microprocessor
For
Digital Media Player
Preliminary Rev 0.51

TCC720 TABLE OF CONTENTS
32-bit RISC Microprocessor for Digital Media Player
Dec. 16. 2002 Preliminary Spec 0.51
2
TABLE OF CONTENTS
1. INTRODUCTION
1.1 Features
1.2 Pin Description
1.3 Package Diagram
2. ADDRESS & REGISTER MAP
3. DAI (Digital Audio Interface) & CDIF (CD-DSP Interface)
4. INTERRUPT CONTROLLER
5. TIMER / COUNTER
6. GPIO
7. CLOCK GENERATOR
8. USB (Universal Serial Bus) CONTROLLER
9. UART / IrDA
10. GSIO (General Purpose Serial Input/Output)
11. MISCELLANEOUS PERIPHERALS
11.1 ADC
11.2 CODEC
12. DMA CONTROLLER
13. MEMORY CONTROLLER
13.1 Overview
13.2 SDRAM Controller
13.3 Miscellaneous Configuration
13.4 External Memory Controller
13.5 Internal Memories
14. BOOT ROM
14.1 External ROM Boot
14.2 UART Boot
14.3 NAND Boot
14.4 NOR Boot with Security
14.5 HPI Boot
14.6 Development Mode
15. JTAG DEBUG INTERFACE
16. PACKAGE DIMENSION

CHAPTER 1
INTRODUCTION

TCC720 INTRODUCTION
32-bit RISC Microprocessor for Digital Media Player
Dec. 16. 2002 Preliminary Spec 0.51
1 - 1
1 INTRODUCTION
TCC720 is system LSI for digital media player which based on ARM940T, ARM’s proprietary 32-
bit RISC CPU core. It can decode and encode MP3 or other types of audio/voice compression /
decompression standards by software based architecture.
The on-chip USB controller enables the data transmission between a personal computer and
storage of device such as NAND flash, HDD, CD etc, which can be controlled by TCC720.
TCC720 also includes on-chip stereo audio CODEC eliminates the need of expensive external
audio CODEC. Using I2S port, TCC720 can also use the external audio CODEC by
performance or other reason.

TCC720 INTRODUCTION
32-bit RISC Microprocessor for Digital Media Player
Dec. 16. 2002 Preliminary Spec 0.51
1 - 2
1.1 FEATURES
 32bit ARM940TDMI RISC CPU core
 8KB instruction/data cache
 Internal boot ROM of 4Kbytes for various boot procedure(NAND, UART) and security
 Internal SRAM of 64K bytes for general usage
 On-chip peripherals
- Memory controller for various memories such as PROM, FLASH, SRAM, SDRAM
- IDE Interface for HDD or USB device
- 4 external interrupts, 9 internal interrupts
- 4 timer/counters, 2 timers
- USB1.1 device (Full speed)
- UART(IrDA) for serial Host I/F
- GPIO, GSIO
- I2S interface for internal and external audio CODEC
- I2S interface for CD-DSP
- On chip audio CODEC with MIC input
- General purpose ADC (3 input)
- 1 Channel DMA for transferring a bulk of data
- JTAG interface for code debugging
 0.25um low power CMOS process
 2.5V for core, 3.3V for I/O port
 128-pin TQFP
 Operating up to 120MHz
1.2 APPLICATIONS
 Portable Digital Audio Encoder/Decoder
 MP3 Juke Box
 Digital Audio Encoder/Decoder
 Digital Internet Radio Server
 Multimedia Storage Device

TCC720 INTRODUCTION
32-bit RISC Microprocessor for Digital Media Player
Dec. 16. 2002 Preliminary Spec 0.51
1 - 3
Timer /
Counter
Timer /
Counter
Timer /
Counter
Timer /
Counter
Timer /
Counter
JTAG
Timer /
Counter
ARM940T
Boot ROM
(512 x 32)
CLK Generator
Power Manager
Ext. Memory &
IDE Interface
Interrupt
Controller
AHB Wrapper
DAI (I2S)
for CODEC
USB1.1
UART/IrDA
GPIO
16bit Audio
CODEC
APB
Bridge
AHB
APB
ETC logic
SRAM
(64K x 8)
8 Input ADC
(8bit)
AHB Arbiter
AHB Test
Controller
1 Channel
DMA
DAI (I2S)
for CD-DSP
XA21 / DQM0
XA20 / DQM1
XA[19:18]
XA17 / ND_CLE
XA16 / ND_ALE / SD_nRAS
XA15 / SD_nCAS
XA14 / SD_BA1
XA13 / SD_BA0
XA[12:0]
XD[15:0]
nOE
nWE
nCS[3:0] / GPIO_B[5:2]
SD_nCS / GPIO_B1
SD_CKE / GPIO_B0
SD_CLK
ND_nWE / GPIO_B7
IDE_nCS1 / GPIO_B9
TDI
TMS
TCK
nTRST
TDO
XIN, XOUT, XTIN, XTOUT, XFILT
ADIN[7:0]
LCH_OUT
RCH_OUT
RCH_IN
MIC_IN
LCH_IN
CDAI / GPIO_A3
CLRCK / GPIO_A2
CBCLK / GPIO_A1
BCLK / GPIO_B21
LRCK / GPIO_B22
MCLK / GPIO_B23
DAO / GPIO_B24
DAI / GPIO_B25
UT_TX / GPIO_B8
UT_RX / GPIO_B9
GPIO_A[15:0]
GPIO_B[29:21]
GPIO_B[9:7]
GPIO_B[5:0]
GSIO
GSIO
GSIO
GSIO2[3:0] / GPIO_A[11:8]
GSIO1[3:0] / GPIO_A[7:4]
GSIO0[3:0] / GPIO_A[3:0]
EXINT3 / GPIO_A15
EXINT2 / GPIO_A14
EXINT1 / GPIO_A13
EXINT0 / GPIO_A12
TCO2 / GPIO_A11
TCO5 / GPIO_A8
TCO1 / GPIO_A7
TCO4 / GPIO_A4
TCO0 / GPIO_A3
TCO3 / GPIO_A0
USB_DP / GPIO_B26, USB_DN / GPIO_B27
Figure 1.1 Functional Block Diagram

TCC720 INTRODUCTION
32-bit RISC Microprocessor for Digital Media Player
Dec. 16. 2002 Preliminary Spec 0.51
1 - 4
1.2 Pin Description
JTAG Interface
Signal Name NUM Type Description
TDI 99 I JTAG serial data input for ARM940T
TMS 100 I JTAG Test mode select for ARM940T
TCK 101 I JTAG test clock for ARM940T
TDO 102 O JTAG serial data output for ARM940T
nTRST 103 I Reset signal for boundary scan logic. Active low.
External Memory Interface
Signal Shared Signal NUM Type Description
SD_CKE GPIO_B0 56 O Clock enable signal for SDRAM, Active high. / GPIO_B1
SD_CLK GPO 44 O SDRAM clock
SD_nCS GPIO_B1 46 O Chip select signal for SDRAM, Active low. / GPIO_B0
XA[6:0] - 23:17 O
XA[12:7] - 31:26 O
Address bus for external memories.
XA[13] SD_BA0 34 O Bank Address 0 for SDRAM / XA[13]
XA[14] SD_BA1 35 O Bank Address 1 for SDRAM / XA[14]
XA[15] SD_nCAS 36 O CAS for SDRAM / XA[15]
XA[16] ND_ALE, SD_nRAS 37 O ALE for NAND flash / RAS for SDRAM / XA[16]
XA[17] ND_CLE 38 O CLE for NAND flash / XA[17]
XA[19:18] - 40:39 O XA[19:18] for static memory / Bus Width configuration
XA[21:20] DQM[0:1] 43:42 O XA[21:20] / Data I/O mask
XD[15:9],
XD[8:4],
XD[3:0]
XD[15:9],
XD[8:4],
XD[3:0]
15:9,
6:2,
128:125
I/O Data bus for external memory
nCS0 / ND_nOE0 GPIO_B2 47 O External chip select 0 / NAND flash 0 OE / GPIO_B2
nCS1 / ND_nOE1 GPIO_B3 48 O External chip select 1 / NAND flash 1 OE / GPIO_B3
nCS2 / ND_nOE2 GPIO_B4 49 O External chip select 2 / NAND flash 2 OE / GPIO_B4
nCS3 / ND_nOE3 GPIO_B5 50 O External chip select 3 / NAND flash 3 OE / GPIO_B5
IDE_nCS1 GPIO_B9 / UT_RX 61 O IDE chip select 1. Active low. / GPIO_B9 / UART RX
ND_nWE GPIO_B7 57 O NAND flash WE. Active low. / GPIO_B7
nWE nWE 58 O Static memory write enable signal. Active low.
nOE nOE 59 O Static memory output enable signal. Active low.
READY - 73 I Ready information from external device.
*) XA[21:0] is used as system address bus for external memories such as SRAM, ROM.
XA[12:0] can be also used as RAS and CAS signals for SDRAM.
XD[15:0] is used as system data bus for all types of external memories contained.
SD_CLK is also used as general purpose output port by setting clock control flag. Refer to the
chapter of memory controller for detail.

TCC720 INTRODUCTION
32-bit RISC Microprocessor for Digital Media Player
Dec. 16. 2002 Preliminary Spec 0.51
1 - 5
General Purpose I/O
Signal Shared Signal NUM Type Description
GPIO_A[15:12] EXINT[3:0] 124:121 I/O GPIO_A[15:12] / External Interrupt Source 3 ~ 0
GPIO_A[11:8]
GSIO2[3:0]
(SDI_2, FRM_2,
SCK_2, SDO_2)
118:115 I/O GPIO_A[11:8] / General Purpose Serial I/O 2
GPIO_A[7:4]
GSIO1[3:0]
(SDI_1, FRM_1,
SCK_1, SDO_1)
114:113
111
108
I/O GPIO_A[7:4] / General Purpose Serial I/O 1
GPIO_A[3:1]
GSIO0[3:1] (SDI_0,
FRM_0, SCK_0) /
CDIF[2:0] (CDAI,
CLRCK, CBCLK)
107:105 I/O GPIO_A[3:1] / General purpose serial I/O 0 /
CD interface signals
GPIO_A[0] GSIO0[0] (SDO_0) 104 I/O GPIO_A[0] / General purpose serial out 0
GPIO_B[29:28] - 54:53 I/O GPIO_B[29:28]
GPIO_B[27:26] USB_DP, USB_DN 52:51 I/O GPIO_B[27:26] / USB_DP, USB_DN
GPIO_B[25:21]
DAI
DAO
MCLK
LRCK
BCLK
68
67
66
63
62
I/O GPIO_B[25:21] / I2S Interface Signals
GPIO_B[9:8] UT_RX / IDE_nCS1
UT_TX
61
60 I/O GPIO_B[9:8] / UART Interface Signals IDE chip select 1
GPIO_B7 ND_nWE 57 I/O GPIO_B7 / Write enable for NAND flash
GPIO_B[5:2] nCS[3:0] 50:47 I/O GPIO_B[5:2] / External Chip Select 3 ~ 0
GPIO_B1 SD_nCS 46 I/O GPIO_B1 / Chip select for SDRAM
GPIO_B0 SD_CKE 56 I/O GPIO_B0 / SDRAM clock control

TCC720 INTRODUCTION
32-bit RISC Microprocessor for Digital Media Player
Dec. 16. 2002 Preliminary Spec 0.51
1 - 6
USB / UART / IrDA Interface
Signal Shared Signal NUM Type Description
USB D+ GPIO_B26 51 I/O USB Function D+ pin / GPIO_B26
USB D- GPIO_B27 52 I/O USB Function D- pin / GPIO_B27
UART_TXD GPIO_B8 60 I/O UART or IrDA TX data pin / GPIO_B8
UART_RXD GPIO_B9 /
IDE_nCS1 61 I/O UART or IrDA RX data pin / GPIO_B9 IDE chip select 1
Audio Interface
Signal Shared Signal NUM Type Description
GPIO_B21 BCLK 62 I/O I2S Bit clock (64fs) / GPIO_B21
GPIO_B22 LRCK 63 I/O I2S Word clock / GPIO_B22
GPIO_B23 MCLK 66 I/O I2S system clock (256fs or 384fs) / GPIO_B23
GPIO_B24 DAO 67 I/O I2S digital audio data output / GPIO_B24
GPIO_B25 DAI 68 I/O I2S digital audio data input / GPIO_B25
LCH_IN LCH_IN 90 I ADC left channel input of internal audio CODEC
RCH_IN RCH_IN 91 I ADC right channel input of internal audio CODEC
MIC_IN MIC_IN 92 I Mic input of internal audio CODEC
LCH_OUT LCH_OUT 93 O DAC left channel output of internal audio CODEC
RCH_OUT RCH_OUT 94 O DAC right channel output of internal audio CODEC
VREF VREF 95 O Reference voltage of internal audio CODEC
CD DSP Interface
Signal Shared Signal NUM Type Description
CBCLK GPIO_A1 105 I/O CD Data Bit Clock Input / GPIO_A1
CLRCK GPIO_A2 106 I/O CD Data Word Clock Input / GPIO_A2
CDAI GPIO_A3 107 I/O CD Data input / GPIO_A3
Clock Interface
Signal Shared Signal NUM Type Description
XIN - 74 I Main clock input for PLL
XOUT - 75 O Main clock output for PLL
XFILT - 78 O PLL filter output
XTIN - 69 I Sub clock input
XTOUT - 70 O Sub clock output
External Interrupt Interface
Signal Shared Signal NUM Type Description
EXINT[3:0]
GPIO_A15
GPIO_A14
GPIO_A13
GPIO_A12
124
123
122
121
I/O External interrupt request [3:0] / GPIO_A[15:12]

TCC720 INTRODUCTION
32-bit RISC Microprocessor for Digital Media Player
Dec. 16. 2002 Preliminary Spec 0.51
1 - 7
General Purpose ADC Interface
Signal Shared Signal NUM Type Description
ADIN[2:0] - 84:82 I General purpose multi-channel ADC input
Mode Control
Signal Shared Signal NUM Type Description
MODE1 - 98 I Mode Setting Input 1
nRESET - 72 I System Reset
Power
Signal NUM Type Description
VDD3
112
76
64
33
16
PWR Digital Power for I/O (3.3V)
VDD2D
119
109
87
71
41
24
7
PWR Digital Power for Internal (2.5V)
VDD2A
89
81
77
PWR Analog Power (2.5V)
VSS3D
97
65
45
32
1
PWR Digital Ground for I/O
VSS2D
120
110
88
55
25
8
PWR Digital Ground for Internal
VSSA
96
86
85
80
79
PWR Analog Ground

TCC720 INTRODUCTION
32-bit RISC Microprocessor for Digital Media Player
Dec. 16. 2002 Preliminary Spec 0.51
1 - 8
1.3 Package Diagram
TCC720
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
53
54
55
56
57
58
59
60
61
62
63
64
52
51
50
49
46
47
48
45
44
43
42
41
40
39
36
37
38
35
34
33
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96
97
98
99
100
101
102
103
104
VSSIO
XD4 XD5 XD6 XD7 XD8
VDDI
VSSI
XD9
XD10 XD11 XD12 XD13 XD14 XD15
VDDIO
XA0 XA1 XA2 XA3 XA4 XA5 XA6 XA7 XA8
VDDI
VSSI
XA9
XA10 XA11 XA12
VSSIO
VDDIO
XA13/BA0
XA14/BA1
XA15/nCAS
XA16/nRAS/ALE
XA17/CLE
XA18
XA19
VDDI
XA20/DQM1
XA21/DQM0
SD_CLK/GPO
VSSIO
SD_nCS/GPIO_B1
nCS0/nOE0/GPIO_B2
nCS1/nOE1/GPIO_B3
nCS2/nOE2/GPIO_B4
nCS3/nOE3/GPIO_B5
USB_DP/GPIO_B26
USB_DN/GPIO_B27
GPIO_B28
GPIO_B29
VSSI
SD_CKE/GPIO_B0
ND_nWE/GPIO_B7
nWE
nOE
UT_TX/GPIO_B8
UT_RX/IDE_nCS1/GPIO_B9
BCLK/GPIO_B21
LRCK/GPIO_B22
VDDIO
VSSIO MCLK/GPIO_B23 DAO/GPIO_B24 DAI/GPIO_B25 XTIN XTOUT VDDI nRESET READY XIN XOUT VDDIO VDDA_PLL XFILT VSSA_PLL VBBA_PLL VDDA_ADC ADIN0 ADIN2 ADIN4 VSSA_ADC VBBA_ADC VDDI_AIP VSSI_AIP VDDA_CDC LCH_OUT RCH_IN RCH_OUT MIC_IN VREF LCH_IN VSSA_CDC
VSSIO
MODE1
TDI
TMS
TCK
TDO
nTRST
VDDI
VSSI
SDO0/GPIO_A0
SCK0/GPIO_A1
SFRM0/GPIO_A2
SDI0/GPIO_A3
SDO1/GPIO_A4
SCK1/GPIO_A5
VDDIO
SFRM1/GPIO_A6
SDI1/GPIO_A7
SDO2/GPIO_A8
SCK2/GPIO_A9
SFRM2/GPIO_A10
SDI2/GPIO_A11
VDDI
VSSI
EXINT0/GPIO_A12
EXINT1/GPIO_A13
EXINT2/GPIO_A14
EXINT3/GPIO_A15
XD0
XD1
XD2
XD3
Figure 1.2 Package Diagram (128-TQFP-1414)

CHAPTER 2
ADDRESS & REGISTER MAP

TCC720 ADDRESS & REGISTER MAP
32-bit RISC Microprocessor for Digital Media Player
Dec. 16. 2002 Preliminary Spec 0.51
2 - 1
2 ADDRESS & REGISTER MAP
2.1 Address Map
The TCC720 has fixed address maps for digital audio en-decoder system. The address space is
separated MSB 4bits of address bus, the following table represents overall address space of
TCC720 system.
Table 2.1 Address Allocation Map of TCC720
Address Space Device Name
0x00000000 ~ 0x0FFFFFFF
internal or external ROM of chip select 3 (Remap == 0)
Other type memory according to base value (Remap = 1)
Internal SRAM when any other memory is not assigned.
0x10000000 ~ 0x1FFFFFFF Not Used
0x20000000 ~ 0x2FFFFFFF Initial area for SDRAM
0x30000000 ~ 0x3FFFFFFF Area of internal SRAM
0x40000000 ~ 0x4FFFFFFF Initial area for chip select 0
Initial configuration is for SRAM
0x50000000 ~ 0x5FFFFFFF Initial area for chip select 1
Initial configuration is for IDE type device
0x60000000 ~ 0x6FFFFFFF Initial area for chip select 2
Initial configuration is for NAND flash
0x70000000 ~ 0x7FFFFFFF Initial area for chip select 3
Initial configuration is for ROM
0x80000000 ~ 0x8FFFFFFF Various internal peripheral devices
0x90000000 ~ 0x9FFFFFFF
0xA0000000 ~ 0xAFFFFFFF
0xB0000000 ~ 0xBFFFFFFF
0xC0000000 ~ 0xCFFFFFFF
0xD0000000 ~ 0xDFFFFFFF
Not Used
0xE0000000 ~ 0xEFFFFFFF Area for internal boot ROM
0xF0000000 ~ 0xFFFFFFFF Area for memory controller configuration register space
The address space (0x00000000 ~ 0x0FFFFFFF) is initially allocated to internal or external
PROM for booting procedure, and a special flag is exist in memory controller unit for remapping
lower half space to other type memories. Refer to the description of memory controller for

TCC720 ADDRESS & REGISTER MAP
32-bit RISC Microprocessor for Digital Media Player
Dec. 16. 2002 Preliminary Spec 0.51
2 - 2
detailed operation.
TCC720 has only one chip select for SDRAM, so its address space is dependent on SDRAM
size attached to TCC720.
TCC720 has various peripherals for controlling a digital audio en-decoder system. These
peripherals can be configured appropriately by it’s own registers that can be accessed through
specially allocated address. These address maps are represented in the following table. In case
of memory controller, its space is separated for preventing illegal accessing.
Refer to corresponding sections for detail information of each peripheral.
Table 2.2 Address Allocation for Internal Peripherals (Base Address = 0x80000000)
Offset Address Space Peripheral
0x000 ~ 0x0FF DAI & CDIF
0x100 ~ 0x1FF Interrupt Controller
0x200 ~ 0x2FF Timer Counter
0x300 ~ 0x3FF GPIO
0x400 ~ 0x4FF Clock Generator & Power Management
0x500 ~ 0x5FF USB Function
0x600 ~ 0x6FF UART/IrDA
0x700 ~ 0x7FF GSIO (General Purpose Serial Input/Output)
0x800 ~ 0x8FF -
0x900 ~ 0x9FF -
0xA00 ~ 0xAFF Analog Control & Etc.
0xB00 ~ 0xBFF -
0xC00 ~ 0xCFF -
0xD00 ~ 0xDFF -
0xE00 ~ 0xEFF DMA Controller
0xF00 ~ 0xFFF -
*) Address decoding logic only monitors base address (i.e. 0x8xxxxxxx), and bit11~bit8 of
accessing address bus. So care must be taken not to modify these registers unintentionally.

TCC720 ADDRESS & REGISTER MAP
32-bit RISC Microprocessor for Digital Media Player
Dec. 16. 2002 Preliminary Spec 0.51
2 - 3
2.2 Register Map
DAI & CDIF Register Map (Base Address = 0x80000000)
Name Address Type Reset Description
DADI_L0 0x00 R - Digital Audio Left Input Register 0
DADI_R0 0x04 R - Digital Audio Right Input Register 0
DADI_L1 0x08 R - Digital Audio Left Input Register 1
DADI_R1 0x0C R - Digital Audio Right Input Register 1
DADO_L0 0x10 R/W - Digital Audio Left Output Register 0
DADO_R0 0x14 R/W - Digital Audio Right Output Register 0
DADO_L1 0x18 R/W - Digital Audio Left Output Register 1
DADO_R1 0x1C R/W - Digital Audio Right Output Register 1
DAMR 0x20 R/W 0x0000 Digital Audio Mode Register
DAVC 0x24 R/W 0x0000 Digital Audio Volume Control Register
CDDI_0 0x80 R - CD Digital Audio Input Register 0
CDDI_1 0x84 R - CD Digital Audio Input Register 1
CICR 0x88 R/W 0x0000 CD Interface Control Register
Interrupt Controller Register Map (Base Address = 0x80000100)
Name Address Type Reset Description
IEN 0x00 R/W 0x0000 Interrupt Enable Register
CREQ 0x04 W - Clear Interrupt Request Register
IREQ 0x08 R 0x0000 Interrupt Request Flag Register
IRQSEL 0x0C R/W 0x0000 IRQ/FIQ Select Register
ICFG 0x10 R/W 0x0000 External Interrupt Configuration Register
MREQ 0x14 R 0x0000 Masked Interrupt Request Flag Register
IRQREQ 0x18 R 0x0000 IRQ Interrupt Request Flag Register
FIQREQ 0x1C R 0x0000 FIQ Interrupt Request Flag Register

TCC720 ADDRESS & REGISTER MAP
32-bit RISC Microprocessor for Digital Media Player
Dec. 16. 2002 Preliminary Spec 0.51
2 - 4
Timer/Counter Register Map (Base Address = 0x80000200)
Name Address Type Reset Description
TCFG0 0x0000 R/W 0x00 Timer/Counter 0 Configuration Register
TCNT0 0x0004 R/W 0x0000 Timer/Counter 0 Counter Register
TREF0 0x0008 R/W 0xFFFF Timer/Counter 0 Reference Register
TMREF0 0x000C R/W 0x0000 Timer/Counter 0 Middle Reference Register
TCFG1 0x0010 R/W 0x00 Timer/Counter 1 Configuration Register
TCNT1 0x0014 R/W 0x0000 Timer/Counter 1 Counter Register
TREF1 0x0018 R/W 0xFFFF Timer/Counter 1 Reference Register
TMREF1 0x001C R/W 0x0000 Timer/Counter 1 Middle Reference Register
TCFG2 0x0020 R/W 0x00 Timer/Counter 2 Configuration Register
TCNT2 0x0024 R/W 0x0000 Timer/Counter 2 Counter Register
TREF2 0x0028 R/W 0xFFFF Timer/Counter 2 Reference Register
TMREF2 0x002C R/W 0x0000 Timer/Counter 2 Middle Reference Register
TCFG3 0x0030 R/W 0x00 Timer/Counter 3 Configuration Register
TCNT3 0x0034 R/W 0x0000 Timer/Counter 3 Counter Register
TREF3 0x0038 R/W 0xFFFF Timer/Counter 3 Reference Register
TMREF3 0x003C R/W 0x0000 Timer/Counter 3 Middle Reference Register
TCFG4 0x0040 R/W 0x00 Timer/Counter 4 Configuration Register
TCNT4 0x0044 R/W 0x00000 Timer/Counter 4 Counter Register
TREF4 0x0048 R/W 0xFFFFF Timer/Counter 4 Reference Register
TCFG5 0x0050 R/W 0x00 Timer/Counter 5 Configuration Register
TCNT5 0x0054 R/W 0x00000 Timer/Counter 5 Counter Register
TREF5 0x0058 R/W 0xFFFFF Timer/Counter 5 Reference Register
TIREQ 0x0060 R/W 0x0000 Timer/Counter n Interrupt Request Register
TWDCFG 0x0070 R/W 0x0000 Watchdog Timer Configuration Register
TWDCLR 0x0074 W - Watchdog Timer Clear Register

TCC720 ADDRESS & REGISTER MAP
32-bit RISC Microprocessor for Digital Media Player
Dec. 16. 2002 Preliminary Spec 0.51
2 - 5
GPIO Register Map (Base Address = 0x80000300)
Name Addr Type Reset Description
GDATA_A 0x00 R/W 0xFFFFFFFF GPIO_A Data Register
GIOCON_A 0x04 R/W 0xFFFF0000 GPIO_A Direction Control Register
GSEL_A 0x08 R/W 0x00000000 GPIO_A Function Select Register
GTSEL_A 0x0C R/W 0x00000000 GPIO_A Function Select Register 2
GDATA_B 0x10 R/W 0x3FFFFFFF GPIO_B Data Register
GIOCON_B 0x14 R/W 0x001FFCFF GPIO_B Direction Control Register
GSEL_B 0x18 R/W 0x3C0000BF GPIO_B Function Select Register
GTSEL_B 0x1C R/W 0x00000000 GPIO_B Function Select Register 2
Clock Generator Register Map (Base Address = 0x80000400)
Name Address Type Reset Description
CKCTRL 0x00 R/W 0x0003FFE Clock Control Register
PLLMODE 0x04 R/W 0x03806 PLL Control Register
SCLKmode 0x08 R/W 0x082000 System Clock Control Register
DCLKmode 0x0C R/W 0x0800 DCLK (DAI/CODEC) Control Register
EXTCLKmode 0x14 R/W 0x0000 EXTCLK (CD/Other) Control Register
UTCLKmode 0x18 R/W 0x01BE UTCLK (UART) Control Register
UBCLKmode 0x1C R/W 0x000 UBCLK (USB) Control Register
TCLKmode 0x24 R/W 0x000 TCLK (Timer) Control Register
GCLKmode 0x28 R/W 0x000 GCLK (GSIO) Control Register
SW_nRST 0x3C R/W 0x000 Software Reset Control Register

TCC720 ADDRESS & REGISTER MAP
32-bit RISC Microprocessor for Digital Media Player
Dec. 16. 2002 Preliminary Spec 0.51
2 - 6
USB Register Map (Base Address = 0x80000500)
Name Address Type Reset Description
UBFADR 0x00 Function Address Register
UBPWR 0x04 Power Management Register
UBIIR 0x08 In-Interrupt Register
UBOIR 0x10 Out-Interrupt Register
UBIR 0x18 Interrupt Register
UBIIEN 0x1C In-Interrupt Enable Register
UBOIEN 0x24 Out-Interrupt Enable Register
UBIEN 0x2C Interrupt Enable Register
UBFRM1 0x30 Frame Number 1 Register
UBFRM2 0x34 Frame Number 2 Register
UBIDX 0x38 Index Register
INMXPn 0x40 IN Max Packet Register
INCSR1n 0x44 IN CSR1 Register
INCSR2n 0x48 IN CSR2 Register
OMXPn 0x4C OUT Max Packet Register
OCSR1n 0x50 OUT CSR1 Register
OCSR2n 0x54 OUT CSR2 Register
OFIFO1n 0x58 OUT FIFO Write Count 1 Register
OFIFO2n 0x5C OUT FIFO Write Count 2 Register
EP0FIFO 0x80 EP0 FIFO Register
EP1FIFO 0x84 EP1 FIFO Register
EP2FIFO 0x88 EP2 FIFO Register

TCC720 ADDRESS & REGISTER MAP
32-bit RISC Microprocessor for Digital Media Player
Dec. 16. 2002 Preliminary Spec 0.51
2 - 7
UART/IrDA Register Map (Base Address = 0x80000600)
Name Address Type Reset Description
RB 0x00 R - Receiver Buffer Register
THR 0x00 W - Transmitter Holding Register
DL 0x04 W 0x0000 Divisor Latch Register
IR 0x08 R/W 0x000 Interrupt Register
CR 0x0C R/W 0x000 UART Control Register
LSR 0x10 R 0x0101 Status Register
IrDACFG1 0x14 R/W 0x0003 IrDA Configuration Register 1
IrDACFG2 0x18 R/W 0x4da1 IrDA Configuration Register 2
GSIO Register Map (Base Address = 0x80000700)
Name Address Type Reset Description
GSDO0 0x00 R/W GSIO0 Output Data Register
GSDI0 0x04 R/W GSIO0 Input Data Register
GSCR0 0x08 R/W GSIO0 Control Register
GSICR 0x0C R/W GSIO Interrupt Control Register
GSDO1 0x10 R/W GSIO1 Output Data Register
GSDI1 0x14 R/W GSIO1 Input Data Register
GSCR1 0x18 R/W GSIO1 Control Register
GSDO2 0x20 R/W GSIO2 Output Data Register
GSDI2 0x24 R/W GSIO2 Input Data Register
GSCR2 0x28 R/W GSIO2 Control Register
GSDO3 0x30 R/W GSIO3 Output Data Register
GSDI3 0x34 R/W GSIO3 Input Data Register
GSCR3 0x38 R/W GSIO3 Control Register

TCC720 ADDRESS & REGISTER MAP
32-bit RISC Microprocessor for Digital Media Player
Dec. 16. 2002 Preliminary Spec 0.51
2 - 8
Analog Interface & ETC Register Map (Base Address = 0x80000A00)
Name Address Type Reset Description
ADCTR 0x00 R/W 0 ADC Control Register
ADDATA 0x04 R - ADC Data Register
CDCTR 0x08 R/W 0 Codec Control Register
CDCGAIN 0x0C R/W 0 Codec Gain Register
LZC 0x10 R/W - Leading Zero Counter Register
USBCTR 0x14 R/W 0 USB Port Control Register
TSTSEL 0x18 R/W 0 Test Mode Register (must be remained zero)
DMA Controller Register Map (Base Address = 0x80000E00)
Name Address Type Reset Description
ST_SADR 0x00 R/W - Start Address of Source Block
SPARAM 0x04/0x08 R/W - Parameter of Source Block
C_SADR 0x0C R - Current Address of Source Block
ST_DADR 0x10 R/W - Start Address of Destination Block
DPARAM 0x14/0x18 R/W - Parameter of Destination Block
C_DADR 0x1C R - Current Address of Destination Block
HCOUNT 0x20 R/W 0x00000000 Initial and Current Hop count
CHCTRL 0x24 R/W 0x00000000 Channel Configuration
Memory Controller Register Map (Base Address = 0xF0000000)
Name Address Type Reset Description
SDCFG 0x00 R/W 0x4268A020 SDRAM Configuration Register
SDFSM 0x04 R - SDRAM FSM Status Register
MCFG 0x08 R/W 0xZZZZ_02 Miscellaneous Configuration Register
TST 0x0C W 0x0000 Test mode register (must be remained zero)
CSCFG0 0x10 R/W
0x0B405601 External Chip Select 0 Configuration
Register (Initially set to SRAM)
CSCFG1 0x14 R/W
0x0150569A External Chip Select 1 Configuration
Register (Initially set to IDE)
CSCFG2 0x18 R/W
0x0060569A External Chip Select 2 Configuration
Register (Initially set to NAND)
CSCFG3 0x1C R/W
0x0A70569A External Chip Select 3 Configuration
Register (Initially set to NOR)