Intel SL8K2 - Pentium 4 3.20EGHz 800MHz 1MB Socket 478... User manual

Intel®Pentium®4 Processor on
90 nm Process
Specification Update
September 2006
R
Notice: The Intel®Pentium®processor may contain design defects or errors known
as errata which may cause the product to deviate from published specifications.
Current characterized errata are documented in this Specification Update.
Document Number: 302352-031

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2 Intel®Pentium®4 Processor on 90 nm Process Specification Update
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL®PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY
ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN
INTEL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL
DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR
WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT,
COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or life sustaining
applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The Intel®Pentium®processor may contain design defects or errors known as errata which may cause the product to deviate from published
specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
1Hyper-Threading Technology requires a computer system with an Intel®Pentium®4 processor supporting HT Technology and a Hyper-Threading
Technology enabled chipset, BIOS and operating system. Performance will vary depending on the specific hardware and software you use. See
http:// www.intel.com/info/hyperthreading/ for more information including details on which processors support HT Technology.
Intel® Virtualization Technology requires a computer system with an enabled Intel® processor, BIOS, virtual machine monitor (VMM) and for some
uses, certain platform software enabled for it. Functionality, performance or other benefits will vary depending on hardware and software
configurations. Intel Virtualization Technology-enabled BIOS and VMM applications are currently in development.
ΔIntel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across
different processor families. See http://www.intel.com/products/processor_number for details.
ΦIntel®Extended Memory 64 Technology (Intel®EM64T) requires a computer system with a processor, chipset, BIOS, operating system, device
drivers and applications enabled for Intel EM64T. Processor will not operate (including 32-bit operation) without an Intel EM64T-enabled BIOS.
Performance will vary depending on your hardware and software configurations. See www.intel.com/info/em64t for more information including
details on which processors support EM64T or consult with your system vendor for more information.
Not all specified units of this processor support Enhanced HALT State and Enhanced Intel SpeedStep® Technology. See the Processor Spec
Finder at http://processorfinder.intel.com or contact your Intel representative for more information.
Intel, Pentium, Celeron, Xeon, Intel SpeedStep, Intel Core, VTune and the Intel logo are trademarks or registered trademarks of Intel Corporation or
its subsidiaries in the United States and other countries.
*Other names and brands may be claimed as the property of others.
Copyright © 2004–2006, Intel Corporation

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Intel®Pentium®4 Processor on 90 nm Process Specification Update 3
Contents
Revision History..................................................................................................................4
Preface................................................................................................................................6
Summary Tables of Changes .............................................................................................8
General Information ..........................................................................................................21
Identification Information...................................................................................................23
Errata ................................................................................................................................30
Specification Changes......................................................................................................73
Specification Clarifications................................................................................................74
Documentation Changes ..................................................................................................75
§

Revision History
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4 Intel®Pentium®4 Processor on 90 nm Process Specification Update
Revision History
Revision
Number Description Date
-001 •Initial Release June 2004
-002 •Added content for Intel®Pentium®4 processor on 90 nm process
in 775-land package
•Added 775-land package processor upside marking diagram
in Figure 2
•Added processor identification information for 775-land
package to Table 1
•Notes added to clarify that C0 errata only apply to 478 pin
package
•Modified for Processor Identification information Table Notes
“Out-of-Cycle”
June 21 2004
-003 •Repaired drawings in Figures 1 and 2; reformatted document
layout “Out-of-Cycle”
June 22, 2004
-004 •Separated the D0 column in Summary Tables of Changes into
D0 and LD0 (L=LGA775) columns
•Updated errata R23 in summary table of changes
•Added errata R32-R38
Aug 2004
-005 •Updated Processor Identification Table, and Summary Table of
Changes
•Added errata R39-R54 Sept 2004
-006 •Updated Processor Identification Table, and Summary Table of
Changes
•Added E-stepping information
•Added errata R55-R68
Out of Cycle
9/23/2004
-007 •Updated and sorted Processor Identification Table
•Added errata R69-R74 October 2004
-008 •Updated Processor Identification Table
•Added errata R75-R77 November 2004
-009 •Updated Processor Identification Table
•Added errata R78, R79 December 2004
-010 •Updated Processor Identification Table December 2004
-011 •Updated Processor Identification Table and Summary Table of
Changes
•Added errata R80, R81, and R82 January 2005

Revision History
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Intel®Pentium®4 Processor on 90 nm Process Specification Update 5
Revision
Number Description Date
-012 •Updated Processor Identification Table and its notes and
updated summary table of changes
•Added errata R83, R84, R85 February 2005
-013 •Updated Processor Identification Table, and Summary Table of
Changes, and processor upside marking for 660, 650, 640, and
630Δprocessor
•Added N-stepping information
•Added Errata R86
“Out of Cycle”
February 22, 2005
-014 •Updated Processor Identification Table, and Summary Table of
Changes
•Added Errata R87, R88, R89, R90 March 2005
-015 •Updated Summary Table of Changes, and affected documents
•Updated R31, R37, and added R91 April 2005
-016 •Updated R32 in Summary Table of Changes May 2005
-017 •Updated affected documents, added/updated 5x1 and 670 part
and processor upside marking, updated processor identification
table,
“Out of Cycle” May
26, 2005
-018 •Updated errata R36 and R41, and added specification changes
R1, and updated processor identification table June 2005
-019 •Added erratum R92 and updated related document July 2005
-020 •Added erratum R93, and updated processor identification table August 2005
-021 •Added errata R94, R95, and updated processor identification
table September 2005
-022 •Added G1-stepping info, updated processor identification table
and added errata R96, R97, R98 October 2005
-023 •Added R0-stepping info, updated affected document, updated
processor identification table and added errata R99-R109 “Out of Cycle”
November 14, 2005
-024 •Updated summary table of changes, updated processor
identification table and added erratum R110 December 2005
-025 •Updated erratum R17 and added errata R111-R114, updated
processor identification table, updated figure 3 and figure 4 to
show Pb-free marking January 2006
-026 •Updated related documents, updated processor identification
table, added erratum R115 February 2006
-027 •Added errata R116, R117 March 2006
-028 •Added errata R118, R119, R120 April 2006
-029 •Added erratum R121 May 2006
-030 •Added erratum R122, updated processor identification table June 2006
-031 •Updated R93, added R123, and updated processor identification
table September 2006
§

Preface
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6 Intel®Pentium®4 Processor on 90 nm Process Specification Update
Preface
This document is an update to the specifications contained in the documents listed in the
following Affected Documents/Related Documents table. It is a compilation of device and
document errata and specification clarifications and changes, and is intended for hardware system
manufacturers and for software developers of applications, operating system, and tools.
Information types defined in the Nomenclature section of this document are consolidated into this
update document and are no longer published in other documents. This document may also
contain information that has not been previously published.
It is intended for hardware system manufacturers and software developers of applications,
operating systems, or tools. It contains S-Specs, Errata, Documentation Changes, Specification
Clarifications and Specification Changes.
Affected Documents
Document Title Document Number
Intel®Pentium®4 Processor on 90 nm Process Datasheet 300561-003
http://developer.intel.com/design/p
entium4/datashts/300561.htm
Intel®Pentium®4 Processors 570/571, 560/561, 550/551, 540/541,
530/531 and 520/521∆Supporting Hyper-Threading Technology
Datasheet On 90 nm Process in 775-land LGA Package and
supporting Intel®Extended Memory 64 TechnologyΦ
302351-004
http://developer.intel.com/design/p
entium4/datashts/302351.htm
Intel®Pentium®4 Processor 6xxΔSequence and Intel®Pentium®4
Processor Extreme Edition Datasheet On 90 nm Process in the 775-
land LGA Package and supporting Intel®Extended Memory 64
TechnologyΦ, and supporting Intel®Virtualization Technology
306382-003
http://developer.intel.com/design/p
entium4/datashts/306382.htm
Related Documents
Document Title Document Number
IA-32 Intel®Architecture Software Developer's Manual Volume 1:
Basic Architecture, document 253665
IA-32 Intel®Architecture Software Developer's Manual Volume 2A:
Instruction Set Reference Manual A–M, document 253666
IA-32 Intel®Architecture Software Developer's Manual Volume 2B:
Instruction Set Reference Manual, N–Z, document 253667
IA-32 Intel Architecture Software Developer's Manual Volume 3A:
System Programming Guide, document 253668
IA-32 Intel Architecture Software Developer's Manual Volume 3B:
System Programming Guide, document 253669
http://developer.intel.com/design/p
entium4/manuals/index_new.htm

Preface
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Intel®Pentium®4 Processor on 90 nm Process Specification Update 7
Nomenclature
S-Spec Number is a five-digit code used to identify products. Products are differentiated by their
unique characteristics, e.g., core speed, L2 cache size, package type, etc. as described in the
processor identification information table. Care should be taken to read all notes associated with
each S-Spec number
Errata are design defects or errors. Errata may cause the Intel®Pentium®processor’s behavior to
deviate from published specifications. Hardware and software designed to be used with any given
stepping must assume that all errata documented for that stepping are present on all devices.
Specification Changes are modifications to the current published specifications. These changes
will be incorporated in the next release of the specifications.
Specification Clarifications describe a specification in greater detail or further highlight a
specification’s impact to a complex design situation. These clarifications will be incorporated in
the next release of the specifications.
Documentation Changes include typos, errors, or omissions from the current published
specifications. These changes will be incorporated in the next release of the specifications.
§

Summary Tables of Changes
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8 Intel®Pentium®4 Processor on 90 nm Process Specification Update
Summary Tables of Changes
The following table indicates the Errata, Documentation Changes, Specification Clarifications, or
Specification Changes that apply to Pentium 4 processors on 90 nm process. Intel intends to fix
some of the errata in a future stepping of the component, and to account for the other outstanding
issues through documentation or specification changes as noted. This table uses the following
notations:
Codes Used in Summary Table
Stepping
X: Erratum, Specification Change or Clarification that applies to
this stepping.
(No mark) or (Blank Box): This erratum is fixed in listed stepping or specification change
does not apply to listed stepping.
Status
Doc: Document change or update that will be implemented.
Plan Fix: This erratum may be fixed in a future stepping of the product.
Fixed: This erratum has been previously fixed.
No Fix: There are no plans to fix this erratum.
PKG: This column refers to errata on the Intel®Pentium®4
processor on 90 nm process substrate.
AP: APIC related erratum.
Shaded: This item is either new or modified from the previous version
of the document.
Note: Each Specification Update item is prefixed with a capital letter to distinguish the product. The key
below details the letters that are used in Intel’s microprocessor Specification Updates:
A = Intel®Pentium®II processor
B = Mobile Intel®Pentium®II processor
C = Intel®Celeron®processor
D = Intel®Pentium®II Xeon®processor
E = Intel®Pentium®III processor
F = Intel®Pentium®processor Extreme Edition
G = Intel®Pentium®III Xeon®processor
H = Mobile Intel®Celeron®processor at 466 MHz, 433 MHz, 400 MHz, 366 MHz, 333 MHz,
300 MHz, and 266 MHz
K = Mobile Intel®Pentium®III Processor – M
L = Intel®Celeron®D processor
M = Mobile Intel®Celeron®processor
N = Intel®Pentium®4 processor

Summary Tables of Changes
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Intel®Pentium®4 Processor on 90 nm Process Specification Update 9
O = Intel®Xeon®processor MP
P = Intel®Xeon®processor
Q = Mobile Intel®Pentium®4 processor supporting Hyper-Threading Technology on 90-nm
process technology
R = Intel®Pentium®4 processor on 90 nm process
S = 64-bit Intel®Xeon®Processor with 800 MHz system bus
T = Mobile Intel®Pentium®4 processor – M
U = 64-bit Intel®Xeon®processor MP with up to 8MB L3 Cache
V = Mobile Intel®Celeron®processor on 0.13 Micron Process in Micro-FCPGA Package
W = Intel®Celeron®M processor
X = Intel®Pentium®M processor on 90 nm process with 2-MB L2 cache
Y = Intel®Pentium®M processor
Z = Mobile Intel®Pentium®4 processor with 533 MHz system bus
AA = Intel®Pentium®processor Extreme Edition and Intel®Pentium®D processor on 65nm
process
AB = Intel®Pentium®4 processor on 65 nm process
AC = Intel®Celeron®Processor in 478 Pin Package
AD = Intel®Celeron®D processor on 65 nm process
AE = Intel®CoreTM Duo Processor and Intel®CoreTM Solo processor on 65nm process
NO. C01D0 LD02E0 LE02G11LG12LN02LR02Plan ERRATA
R1 X X X X X X X X X
No
Fix Transaction Is Not Retried after BINIT#
R2 X X X X X X X X X
No
Fix Invalid Opcode 0FFFh Requires a ModRM Byte
R3 X X X X X X X X X
No
Fix
Processor May Hang Due to
Speculative Page Walks to Non-
Existent System Memory
R4 X X X X X X X X X
No
Fix
Memory Type of the Load Lock
Different from Its Corresponding
Store Unlock
R5 X X X X X X X X X
No
Fix
Machine Check Architecture Error
Reporting and Recovery May Not
Work As Expected
R6 X X X X X X X X X
No
Fix Debug Mechanisms May Not Function as Expected
R7 X X X X X X X X X
No
Fix
Cascading of Performance
Counters Does Not Work Correctly
When Forced Overflow Is Enabled
R8 X X X X X X X X X
No
Fix EMON Event Counting of x87 Loads May Not Work As Expected
R9 X X X X X X X X X
No
Fix
System Bus Interrupt Messages
without Data Which Receive a
HardFailure Response May Hang
the Processor

Summary Tables of Changes
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10 Intel®Pentium®4 Processor on 90 nm Process Specification Update
NO. C01D0 LD02E0 LE02G11LG12LN02LR02Plan ERRATA
R10 X X X X X X X X X
No
Fix
The Processor Signals Page-Fault
Exception (#PF) Instead of
Alignment Check Exception (#AC)
on an Unlocked CMPXCHG8B
Instruction
R11 X X X X X X X X X
No
Fix
FSW May Not Be Completely
Restored after Page Fault on
FRSTOR or FLDENV Instructions
R12 X X X X X X X X X
No
Fix
Processor Issues Inconsistent
Transaction Size Attributes for
Locked Operation
R13 X X X X X X X X X
No
Fix
When the Processor Is in the
System Management Mode (SMM),
Debug Registers May Be Fully
Writeable
R14 X X X X X X X X X
No
Fix
Shutdown and IERR# May Result
Due to a Machine Check Exception
on a Hyper-Threading Technology
Enabled Processor
R15 X X X X X X X X X
No
Fix
Processor May Hang under Certain
Frequencies and 12.5% STPCLK#
Duty Cycle
R16 X X X X X X X X X
No
Fix
System May Hang if a Fatal Cache
Error Causes Bus Write Line (BWL)
Transaction to Occur to the Same
Cache Line Address as an
Outstanding Bus Read Line (BRL)
or Bus Read-Invalidate Line (BRIL}
R17 X X X X X X X X X
No
Fix
A Write to an APIC Registers
Sometimes May Appear to Have
Not Occurred
R18 X Fixed
Some Front Side Bus I/O
Specifications are not Met
R19 X X X X X X X X X
No
Fix Parity Error in the L1 Cache May Cause the Processor to Hang
R20 X Fixed
BPM4# Signal Not Being Asserted
According to Specification
R21 X X X X X Fixed
Sequence of Locked Operations
Can Cause Two Threads to
Receive Stale Data and Cause
Application Hang
R22 X X X Fixed
A 16-bit Address Wrap Resulting
from a Near Branch (Jump or Call)
May Cause an Incorrect Address to
be Reported to the #GP Exception
Handler
R23 X X X X X X X X X
No
Fix
Bus Locks and SMC Detection May
Cause the Processor to Hang
Temporarily

Summary Tables of Changes
R
Intel®Pentium®4 Processor on 90 nm Process Specification Update 11
NO. C01D0 LD02E0 LE02G11LG12LN02LR02Plan ERRATA
R24 X Fixed
PWRGOOD and TAP Signals
Maximum Input Hysteresis Higher
Than Specified
R25 X X X Fixed
Incorrect Physical Address Size
Returned by CPUID Instruction
R26 X X X X X X X X X
No
Fix
Incorrect Debug Exception (#DB)
May Occur When a Data Breakpoint
is set on an FP Instruction
R27 X X X X X X X X X
No
Fix xAPIC May Not Report Some Illegal Vector Errors
R28 X X X X X Fixed
Enabling No-Eviction Mode (NEM)
May Prevent the Operation of the
Second Logical Processor in a
Hyper-Threading Technology
Enabled Processor
R29 X X X X X X X X X
No
Fix
Incorrect Duty Cycle is Chosen
when On-Demand Clock
Modulation is Enabled in a
Processor Supporting Hyper-
Threading Technology
R30 X X X X X X X X X
No
Fix
Memory Aliasing of Pages as
Uncacheable Memory Type and
Write Back (WB) May Hang the
System
R31 X X X X X X X X X
No
Fix
Interactions Between the Instruction
Translation Lookaside Buffer (ITLB)
and the Instruction Streaming Buffer
May Cause Unpredictable Software
Behavior
R32 X Fixed
STPCLK# Signal Assertion under
Certain Conditions May Cause a
System Hang
R33 X Fixed
Missing Stop Grant
Acknowledge Special Bus Cycle
May Cause a System Hang
R34 X Fixed
Changes to CR3 Register do not
Fence Pending Instruction Page
Walks
R35 X Fixed
Simultaneous Page Faults at
Similar Page Offsets on Both
Logical Processors of a Hyper-
Threading Technology Enabled
Processor May Cause Application
Failure
R36 X Fixed
The State of the Resume Flag (RF
Flag) in a Task-State Segment
(TSS) May be Incorrect
R37 X X X X X X X X X
No
Fix
Using STPCLK# and Executing
Code From Very Slow Memory
Could Lead to a System Hang

Summary Tables of Changes
R
12 Intel®Pentium®4 Processor on 90 nm Process Specification Update
NO. C01D0 LD02E0 LE02G11LG12LN02LR02Plan ERRATA
R38 X X X X X X X X X
No
Fix Processor Provides a 4-Byte Store Unlock After an 8-Byte Load Lock
R39 X X X X X X X X X
No
Fix
Data Breakpoints on the High Half
of a Floating Point Line Split may
not be Captured
R40 X Fixed
CPUID Instruction May Report
Incorrect L2 Associativity in Leaf
0x80000006
R41 X Fixed
The FP_ASSIST EMON Event May
Return an Incorrect Count
R42 X X X X X X X X X
No
Fix
Machine Check Exceptions May not
Update Last-Exception Record
MSRs (LERs)
R43 X X X X X X X X X
No
Fix
MOV CR3 Performs Incorrect
Reserved Bit Checking When in
PAE Paging
R44 X X X X X X X X X
No
Fix
Stores to Page Tables May Not Be
Visible to Pagewalks for
Subsequent Loads Without
Serializing or Invalidating the Page
Table Entry
R45 X X X X X X X Fixed
Execution of IRET or INTn
Instructions
May Cause Unexpected System
Behavior
R46 X X X Fixed
A Split Store Memory Access May
Miss a Data Breakpoint
R47 X X Fixed
EFLAGS.RF May be Incorrectly Set
After an IRET Instruction
R48 X Fixed
Read for Ownership and
Simultaneous Fetch May Cause the
Processor to Hang
R49 X X Fixed
Writing the Echo TPR Disable Bit in
IA32_MISC_ENABLE May Cause a
#GP Fault
R50 X Fixed
Cache Lock with Simultaneous
Invalidate external snoop and SMC
check May Cause the Processor to
Hang
R51 X Fixed
IRET Instruction Performing Task
Switch May Not Serialize the
Processor Execution
R52 X X X Fixed
Incorrect Access Controls to
MSR_LASTBRANCH_0_FROM_LI
P MSR Registers
R53 X X X X Fixed
Recursive Page Walks May Cause
a System Hang

Summary Tables of Changes
R
Intel®Pentium®4 Processor on 90 nm Process Specification Update 13
NO. C01D0 LD02E0 LE02G11LG12LN02LR02Plan ERRATA
R54 X5 X X Fixed
WRMSR to bit[0] of
IA32_MISC_ENABLE Register
Changes Only One Logical
Processor on a Hyper-Threading
Technology Enabled Processor
R55 X5 X5 X X Fixed
VERR/VERW Instructions May
Cause #GP Fault when Descriptor
is in Non-canonical Space
R56 X X Fixed
The Base of a Null Segment May
be Non-zero on a Processor
Supporting Intel® Extended
Memory 64 Technology (Intel®
EM64T)Φ
R57 X X Fixed
Upper 32 Bits of FS/GS with Null
Base May not get Cleared in
Virtual-8086 Mode on Processors
with Intel® Extended Memory 64
Technology (Intel® EM64T)
Enabled
R58 X X X X X
No
Fix
Processor May Fault when the
Upper 8 Bytes of Segment Selector
is Loaded From a Far Jump
Through a Call Gate via the Local
Descriptor Table
R59 X X X X X
No
Fix
Loading a Stack Segment with a
Selector that References a Non-
canonical Address can Lead to a
#SS Fault on a Processor
Supporting Intel® Extended
Memory 64 Technology (Intel®
EM64T)
R60 X X X X X
No
Fix
FXRSTOR May Not Restore Non-
canonical Effective Addresses on
Processors with Intel® Extended
Memory 64 Technology (Intel®
EM64T) Enabled
R61 X X X X X
No
Fix A Push of ESP that Faults may Zero the Upper 32 Bits of RSP
R62 X Fixed
Enhanced Halt State (C1E) Voltage
Transition May Affect a System’s
Power Management in a Hyper-
Threading Technology
Enabled Processor
R63 X X X X
No
Fix
Enhanced Halt State (C1E) May
Not Be Entered in a Hyper-
Threading Technology Enabled
Processor
R64 X Fixed
When the Execute Disable Bit
Function is Enabled a Page-fault in
a Mispredicted Branch May Result
in a Page-fault Exception

Summary Tables of Changes
R
14 Intel®Pentium®4 Processor on 90 nm Process Specification Update
NO. C01D0 LD02E0 LE02G11LG12LN02LR02Plan ERRATA
R65 X Fixed
Execute Disable Bit Set with AD
Assist Will Cause Livelock
R66 X Fixed
The Execute Disable Bit Fault May
be Reported Before Other Types
of Page Fault When Both Occur
R67 X Fixed
Writes to IA32_MISC_ENABLE May
Not Update Flags for Both Logical
Processors Threads
R68 X Fixed
Execute Disable Mode Bit Set with
CR4.PAE May Cause Livelock
R69 X X X X X X X X X
No
Fix
Checking of Page Table Base
Address May Not Match the
Address Bit Width Supported by the
Platform
R70 X X X X X X X X X
No
Fix
The IA32_MCi_STATUS MSR May
Improperly Indicate that Additional
MCA Information May Have Been
Captured
R71 X Fixed
Execution of an Instruction with a
Code Breakpoint Inhibited by the
RF (Resume Flag) Bit May be
Delayed by an RFO (Request For
Ownership) from Another Bus
Agent
R72 X X X X X X X X X
No
Fix
With TF (Trap Flag) Asserted, FP
Instruction That Triggers an
Unmasked FP Exception May Take
Single Step Trap Before Retirement
of Instruction
R73 X X X Fixed
MCA Corrected Memory Hierarchy
Error Counter May Not Increment
Correctly
R74 X X X X X X X X X
No
Fix
BTS(Branch Trace Store) and
PEBS(Precise Event Based
Sampling) May Update Memory
outside the BTS/PEBS Buffer
R75 X X X X Fixed
The Base of an LDT (Local
Descriptor Table) Register May be
Non-zero on a Processor
Supporting Intel® Extended
Memory 64 Technology (Intel®
EM64T)
R76 X X X Fixed
L-bit of the CS and LMA bit of the
IA32_EFER Register May Have an
Erroneous Value For One
Instruction Following a Mode
Transition in a Hyper-Threading
Enabled Processor Supporting
Intel® Extended Memory 64
Technology (Intel® EM64T).

Summary Tables of Changes
R
Intel®Pentium®4 Processor on 90 nm Process Specification Update 15
NO. C01D0 LD02E0 LE02G11LG12LN02LR02Plan ERRATA
R77 X X X X X X X X X
No
Fix
Memory Ordering Failure May
Occur with Snoop Filtering Third
Party Agents after Issuing and
Completing a BWIL (Bus Write
Invalidate Line) or BLW (Bus
Locked Write) Transaction
R78 X X X X X X X X X
No
Fix
Control Register 2 (CR2) Can be
Updated during a REP
MOVS/STOS Instruction with Fast
Strings Enabled
R79 X X X X Fixed
TPR (Task Priority Register)
Updates during Voltage Transitions
of Power Management Events May
Cause a System Hang
R80 X X X X X
No
Fix
REP STOS/MOVS Instructions with
RCX >=2^32 May Cause a System
Hang
R81 X X X X Fixed
An REP MOVS or an REP STOS
Instruction with RCX >= 2^32 May
Fail to Execute to Completion or
May Write to Incorrect Memory
Locations on Processors
Supporting Intel® Extended
Memory 64 Technology (Intel®
EM64T)
R82 X X X X Fixed
An REP LODSB or an REP LODSD
or an REP LODSQ Instruction with
RCX >= 2^32 May Cause a System
Hang on Processors Supporting
Intel® Extended Memory 64
Technology (Intel® EM64T)
R83 X X X X No
Fix
A Data Access which Spans Both
the Canonical and the Non-
Canonical Address Space May
Hang the System
R84 X X X X X X X X Fixed
Running in SMM (System
Management Mode) And L1 Data
Cache Adaptive Mode May Cause
Unexpected System Behavior when
SMRAM is Mapped to Cacheable
Memory
R85 X Fixed
CPUID Instruction Incorrectly
Reports CMPXCH16B as
Supported
R86 X X X X X Fixed
Unaligned PDPTR (Page-Directory-
Pointer) Base with 32-bit Mode PAE
(Page Address Extension) Paging
May Cause Processor to Hang

Summary Tables of Changes
R
16 Intel®Pentium®4 Processor on 90 nm Process Specification Update
NO. C01D0 LD02E0 LE02G11LG12LN02LR02Plan ERRATA
R87 X Fixed
FXSAVE Instruction May Result in
Incorrect Data on Processors
Supporting Intel® Extended
Memory 64 Technology (Intel®
EM64T)
R88 X Fixed
Compatibility Mode STOS
Instructions May Alter RSI Register
Results on a Processor Supporting
Intel® Extended Memory 64
Technology (Intel® EM64T)
R89 X Fixed
LDT Descriptor Which Crosses 16
bit Boundary Access Does Not
Cause a #GP Fault on a Processor
Supporting Intel® Extended
Memory 64 Technology (Intel®
EM64T)
R90 X Fixed
Upper Reserved Bits are Incorrectly
Checked While Loading PDPTR's
on a Processor Supporting Intel®
Extended Memory 64 Technology
(Intel® EM64T)
R91 X X X X X
No
Fix
A 64-Bit Value of Linear Instruction
Pointer (LIP) May be Reported
Incorrectly in the Branch Trace
Store (BTS) Memory Record or in
the Precise Event Based Sampling
(PEBS) Memory Record
R92 X X X X X X X X Fixed
It is Possible That Two specific
Invalid Opcodes May Cause
Unexpected Memory Accesses
R93 X X X X X X X X X No
Fix
At Core-to-bus Ratios of 16:1 and
Above Defer Reply Transactions
with Non-zero REQb Values May
Cause a Front Side Bus Stall
R94 X X X X X X X X X
No
Fix
The Processor May Issue Front
Side Bus Transactions up to 6
Clocks after RESET# is Asserted
R95 X X X X X X X X X
No
Fix
Front Side Bus Machine Checks
May be Reported as a Result of On-
Going Transactions during Warm
Reset
R96 X Fixed
CPUID Feature Flag Reports
LAHF/SAHF as Unavailable
however the Execution of
LAHF/SAHF May Not Result in an
Invalid Opcode Exception
R97 X5 X5 X5 X5 X5 X5 X5 X5 X No
Fix
The Processor May Issue Multiple
Code Fetches to the Same Cache
Line for Systems with Slow Memory

Summary Tables of Changes
R
Intel®Pentium®4 Processor on 90 nm Process Specification Update 17
NO. C01D0 LD02E0 LE02G11LG12LN02LR02Plan ERRATA
R98 X X X X X X X X X
No
Fix
Writing the Local Vector Table
(LVT) when an Interrupt is Pending
May Cause an Unexpected
Interrupt
R99 X
No
Fix
Access to an Unsupported Address
Range in Uniprocessor (UP) or
Dual-processor (DP) Systems
Supporting Intel® Virtualization
Technology May Not Trigger
Appropriate Actions
R100 X
No
Fix
VM Exit Due to a MOV from CR8
May Cause an Unexpected Memory
Access
R101 X
No
Fix
The Processor May Incorrectly
Respond to Machine Checks during
VM Entry/Exit Transitions
R102 X
No
Fix
INIT during String Operations in the
Virtual-Machine Extension (VMX)
Guest Mode May Cause
Unexpected System Behavior
R103 X
No
Fix
Power Down Requests May not be
Serviced if a Power Down
Transition is Interrupted by an In-
Target Probe Event in the Presence
of a Specific Type of VM Exit
R104 X
No
Fix
VM EXIT Due to TPR shadow
Below Threshold May Improperly
Set and Cause "Blocking by STI"
actions
R105 X
No
Fix
VM Entry/Exit Writes to
LSTAR/SYSCALL_FLAG MSR's
May Cause Incorrect Data to be
Written to Bits [63:32]
R106 X
No
Fix
Machine Check Architecture
Multiple Data Parity Errors May be
Reported
R107 X
Plan
Fix
Attempting to Use an LDT Entry
when the LDTR Has Been Loaded
with an Unusable Segment May
Cause Unexpected Memory
Accesses
R108 X
No
Fix
The Execution of a VMPTRLD
Instruction May Cause an
Unexpected Memory Access
R109 X
No
Fix
The Execution of VMPTRLD or
VMREAD May Cause an
Unexpected Memory Access
R110 X X X X X
No
Fix
IRET under Certain Conditions May
Cause an Unexpected Alignment
Check Exception

Summary Tables of Changes
R
18 Intel®Pentium®4 Processor on 90 nm Process Specification Update
NO. C01D0 LD02E0 LE02G11LG12LN02LR02Plan ERRATA
R111 X
No
Fix
FS/GS Base MSRs can be Loaded
from MSR-Load Areas during VM
Entry or VM Exit
R112 X
Plan
Fix
NMI-blocking Information Recorded
in VMCS May be Incorrect after a
#GP on an IRET Instruction
R113 X
Plan
Fix
VMLAUNCH/VMRESUME May Not
Fail when VMCS is Programmed to
Cause VM Exit to Return to a
Different Mode
R114 X Fixed
Upper 32 bits of ‘From’ Address
Reported through LBR or LER
MSRs, BTMs or BTSs May be
Incorrect
R115 X
Plan
Fix
VMEntry from 64-bit Host to 32-bit
Guest may Cause IERR# with
Hyper-Threading Enabled
R116 X X X X X X X X X
No
Fix
L2 Cache ECC Machine Check
Errors May be erroneously Reported
after an Asynchronous RESET#
Assertion
R117 X
Plan
Fix
VMExit after MOV SS and a Waiting
x87 Instruction May not Clear the
Interruptibility State in the VMM’s
Working VMCS
R118 X
Plan
Fix
VMCALL to Activate Dual-monitor
Treatment of SMIs and SMM
Ignores Reserved Bit settings in
VM-exit Control Field
R119 X X X X X X X X X
No
Fix
Using 2M/4M Pages When A20M#
Is Asserted May Result in Incorrect
Address Translations
R120 X X X X X X X X X
No
Fix
Writing Shared Unaligned Data that
Crosses a Cache Line without
Proper Semaphores or Barriers May
Expose a Memory Ordering Issue
R121 X X X X X X X X X
No
Fix
The IA32_MC0_STATUS and
IA32_MC1_STATUS Overflow Bit is
not set when Multiple Un-
correctable Machine Check Errors
Occur at the Same Time
R122 X X X X X X X X X
No
Fix
Debug Status Register (DR6)
Breakpoint Condition Detected
Flags May be set Incorrectly
R123 X X X X X X X X X No
Fix
A Continuous Loop Executing Bus
Lock Transactions on One Logical
Processor may Prevent Another
Logical Processor from Acquiring
Resources
NOTES:
1. Only applies to Pentium®4 processor on 90 nm Process in the 478-pin package
2. Prefix “L” denotes Pentium 4 processor on 90 nm Process in the 775-land LGA package

Summary Tables of Changes
R
Intel®Pentium®4 Processor on 90 nm Process Specification Update 19
3. This erratum applies to Pentium 4 processor supporting Intel®Extended Memory 64 Technology (Intel®EM64T)
for Single-Processor Server/Workstation Platform configurations only. Non-server/workstation desktop
configurations do not support the Intel Extended Memory 64 Technology.
4. This erratum does not apply to Pentium 4 processors for single-processor server/workstation platform
configurations.
5. For these steppings, this erratum may be worked around in BIOS.
NO. SPECIFICATION CHANGES
R1 Land Assignment Specification Change
NO. SPECIFICATION CLARIFICATIONS
There are no Specification Clarification in this Specification Update revision
NO. DOCUMENTATION CHANGES
There are no documentation changes in this Specification Update revision
§

Summary Tables of Changes
R
20 Intel®Pentium®4 Processor on 90 nm Process Specification Update