Tern CAN-Engine User manual

1950 5
th
Street, Davis, CA 95616, USA
Tel: [phone] Fax: [phone]
Email: [email protected]om http://www.tern.com
CAN-Engine ™
C Programmable Embedded CAN Controller, with 100M BaseT Ethernet, RS232,
CompactFlash, and 16-bit parallel high speed ADC
Technical Manual

COPYRIGHT
CAN-Engine, E-Engine, A-Engine86, A-Engine, A-Core86, A-Core, i386-Engine,
MemCard-A, MotionC, VE232, and ACTF are trademarks of TERN, Inc.
Am188ES and Am186ES are trademarks of Advanced Micro Devices, Inc.
Borland C/C++ is a trademark of Borland International.
Microsoft, MS-DOS, Windows, Windows95, and Windows98 are trademarks of
Microsoft Corporation.
IBM is a trademark of International Business Machines Corporation.
Version 2.0
October 21, 2010
No part of this document may be copied or reproduced in any form or by any means
without the prior written consent of TERN, Inc.
© 1993-2010
1950 5
th
Street, Davis, CA 95616, USA
Tel: [phone] Fax: [phone]
Email: sa[email protected] http://www.tern.com
Important Notice
TERN is developing complex, high technology integration systems. These systems are
integrated with software and hardware that are not 100% defect free. TERN products are
not designed, intended, authorized, or warranted to be suitable for use in life-support
applications, devices, or systems, or in other critical applications. TERN and the Buyer
agree that TERN will not be liable for incidental or consequential damages arising from
the use of TERN products. It is the Buyer's responsibility to protect life and property
against incidental failure.
TERN reserves the right to make changes and improvements to its products without
providing notice.
Temperature readings for controllers are based on the results of limited sample tests; they
are provided for design reference use only.

CAN-Engine Chapter 1: Introduction
1-1
Chapter 1: Introduction
1.1 Functional Description
Measuring 3.6 x 2.3 inches, the CAN-Engine™ (CANE) is a high performance, low cost, C/C++ programmable
controller. It is intended for networking application including industrial process control, high-speed data acquisition,
and especially ideal for OEM applications.
The CANE can use any one of these 3 16-bit CPU chips: 40 MHz AM186ES(5V), or 40 MHz RDC R8820(5V) or
80MHz RDC R1120(3.3V).
An Fast Ethernet Module can be installed to provide 100M Base-T network connectivity. This Ethernet module has
a hardware LSI TCP/IP stack. It implements TCP/IP, UDP, ICMP and ARP in hardware, supporting internet
protocol DLC and MAC. It has 16KB internal transmit and receiving buffer which is mapped into host processor’s
direct memory. The host can access the buffer via high speed DMA transfers. The hardware Ethernet module
releases internet connectivity and protocol processing from the host processor, which represents a huge improvement
over software-based TCP/IP stacks. No processor cycles are used to track packet transmission/retransmission,
timeouts, etc. The resulting system can easily handle transmissions in the 100K bytes per second+ range in real
world applications. It supports 4 independent stack connections simultaneously at a 4Mbps protocol processing
speed. An RJ45 8-pin connector is on-board for connecting to 10/100 Base-T Ethernet network. Software libraries
and demo project are available for Ethernet connectivity.
A Controller Area Network (CAN) controller (SJA1000, 20 MHz clock) and CAN bus tranceiver is available. It
supports network baud rates up to 1M-bit per second. Software drivers allow access to all CAN controller registers,
as well as a buffering software layer.
The CANE features fast execution times through 16-bit ACTF Flash (256 KW) and battery-backed SRAM (256
KW). It also includes 3 timers, PWMs, 20+ PIOs, 512-byte serial EEPROM, two UARTs, 3 timer/counters, and a
watchdog timer. The three 16-bit timers can be used to count or time external events, up to 10 MHz, or to generate
non-repetitive or variable-duty-cycle waveforms as PWM outputs. The PIO pins are multifunctional and user
programmable.
A serial real timer clock (DS1337, Dallas) is a low power clock/calendar with two time-of-day alarms and a
programmable square-wave output.
Two RS232 channels of full-duplex asynchronous receivers and transmitters are on-board. The UARTs incorporate
9-bit mode for multi-processor communications.
A 16-bit parallel ADC (AD7655, 0-5V) supports ultra high-speed (1 MHz conversion rate) analog signal acquisition.
The AD7655 contains two low noise, high bandwidth track-and-hold amplifiers that allow simultaneous sampling on
two channels. Each track-and hold amplifier has a multiplexer in front to provide a total of 4 channels analog inputs.
The parallel ADC achieves high throughput by requiring only two CPU I/O operations (one start, one read) to
complete a 16-bit ADC reading. With a precision external 2.5V reference, the ADC accepts 0-5V analog inputs at
16-bit resolution of 0-65,535.
The CANE supports low cost, removable, up to 2 GB mass storage CompactFlash cards with onboard CompactFlash
interface. User can store and transfer large amounts of data with a PC, via a CF card with TERN’s FAT filesystem
software support.
The CANE can be powered by USB, or regulated 5V, or unregulated 9V DC power with on-board 5V regulator
installed.
The CANE provides a true 16-bit data bus for SRAM, Flash, ADC, Ethernet, and a J1 20x2 expansion header. The
CANE is an ideal upgrade for the A-Engine, V25-Engine, 386-Engine, or R-Engine providing increased reliability,
networking functionality, and performance. They have the similar mechanical dimensions, pin outs, software drivers,
and both are programmed using Paradigm C++ TERN Edition Evaluation Kit (EV-P) or Development Kit (DV-P).

Chapter 1: Introduction CAN-Engine
1-2
The CANE can be integrated into an OEM product as a processor core component. It also can be used to build a
smart sensor, or can act as a node in a distributed microprocessor system.
Am186ES
R8820/R1120
CPU
40/80MHz
DMA(2)
16-Bit Timers(3)
Ext. Interrupts(8)
32 I/O lines
PWM/PWD
16-bit Ext. data bus
691 U6
EEPROM U7
512 BYTES
FLASH
512 KB 16-bit U1
RS232 drivers
SER0+SER1
SDA P11
SDL P12
J1 & J2
100M BaseT
Ethernet
JP1+JP2
4 ch. 16-bit
AD7655 U8
RTC U15
Low drop 5V
regulators for USB
U0+U01
Or
Linear 5V regulators
LM7805
SRAM
128KB or 512 KB
16-bit U3 J9
watchdog
enable
CAN-Engine CAN
U5
CompactFlash
U11
D0..D15
D0..D15
Figure 1.1 Functional block diagram of the CAN-Engine
The CANE supports on-board 512 KB 16-bit Flash and up to 512 KB 16-bit battery-backed SRAM. The on-board
ACTF Flash has a protected boot loader and can be easily programmed in the field via serial link. Users can
download a kernel into the Flash for remote debugging. With the DV-P Kit support, user application codes can be
easily field-programmed into and run out of the Flash.
A 512-byte serial EEPROM is included on-board. Two DMA-driven serial ports from the Am186ES support high-
speed, reliable serial communication at a rate of up to 115,200 baud. All serial ports support 8-bit and 9-bit
communication.
There are three 16-bit programmable timers/counters and a watchdog timer. Two timers can be used to count or time
external events, at a rate of up to 10 MHz, or to generate non-repetitive or variable-duty-cycle waveforms as PWM
outputs. Pulse Width Demodulation (PWD), a distinctive feature, can be used to measure the width of a signal in
both its high and low phases. It can be used in many applications, such as bar-code reading.
The EE has 32 user-programmable, multifunctional I/O pins from the CPU. Schmitt-trigger inverters are provided
for six external interrupt inputs, to increase noise immunity and transform slowly-changing input signals into fast-
changing and jitter-free signals. A supervisor chip with power failure detection, a watchdog timer, an LED, and
expansion ports are on-board.

CAN-Engine Chapter 1: Introduction
1-3
Features:
• 3.6 x 2.3 x 1”, 200 mA at 5V for 80 MHz
• 40 or 80 MHz, 16-bit CPU, program in C/C++
• 256 KW 16-bit Flash, 256 KW 16-bit SRAM, 512 bytes EE
• Controller Area Network (CAN2.0B)
• 20+ TTL I/Os, Real-time clock, 2 serial ports, PWM, counters
• 4 ch 16-bit parallel high speed ADC (AD7655)
• Hardware TCP/IP stack for 100M Base-T Ethernet
• CompactFlash card with FAT file system support
1.2 Physical Description
The physical layout of the CAN-Engine is shown in Figure 1.2.
Figure 1.2 Physical layout of the CAN-Engine

Chapter 1: Introduction CAN-Engine
1-4
Figure 1.3 Flow chart for ACTF operation
The “ACTF boot loader” resides in the top protected sector of the 512KB on-board Flash chip (29F400).
By default, in the factory, before shipping, the DEBUG kernel (EE40_115.hex) is pre-loaded
in the Flash starting at 0xFA000, and the RED STEP2 jumper is installed, ready for
Paradigm C++ debugger. User does not need to download a DEBUG kernel to start with.
At power-on or RESET, the “ACTF” will check the STEP 2 jumper. If STEP 2 jumper is not installed, the ACTF
menu will be sent out from serial port0 at 19200 baud for a CANE 40MHz, or 9600 baud for a CANE 80MHz.
If the STEP 2 jumper is install ed, the “jump address” located in the on-board serial EE will be read out and then
jump to that address. A DEBUG kernel “EE40_115.hex” for the CANE 40MHz or “EE80_115.hex” for the CANE
80MHz can be downloaded, residing in “0xFA000” of the 512KB on-board flash chip.
The “EE84_115.hex can also be downloaded into a CANE 80MHz for easier running all demo projects, which are
designed for running 40MHz.
Power On or Reset
YES
Go to Application Code CS:IP
STEP 2
ACTF menu sent out through ser0
STEP 1
Step 2 jumper
NO
set?
CS:IP in EEPROM:
0x10=CS high byte
0x11=CS low byte
0x12=IP high byte
0x13=IP low byte
at 19200/9600 baud(EE40/80)

CAN-Engine Chapter 1: Introduction
1-5
1.3 CAN-Engine Programming Overview
Steps for product development:
Preparation for Debugging(DONE in Factory !)
• Connect board toPC via RS-232 link, 19,200, 8, N, 1
• Power onwithout STEP 2 jumper installed
• ACTF menu should be sent to PC terminal
• Use “D” command to download “L_TDREM.HEX” in SRAM
• “G04000” torun “L_TDREM”
•
Download “c:
\
tern
\
186
\
rom
\
ae86
\
E
E40_115.HEX” to Flash
• “GFA000” to setup EEPROM and run remote debugger
• Install the STEP2 jumper (J2.38-40)
• Power-on or reset, Ready for Remote debugger
STEP 2:
Standalone Field Test
8
88
8”G08000” setup EEPROM Jump Address, points to
application code resides in battery backed SRAM
8
88
8Install STEP2 jumper, then power on
8
88
8Applicationprogram running in battery-backedSRAM
(Battery lasts 3
-
5 years under normal conditions.)
• Start Paradigm C++, run “led.ide” or “test.ide”
• Download code to target SRAM.
• Edit, compile, link, locate, download, and remote-debug
STEP 1:
Debugging
STEP 3:
DV-P Kit
• Generate application HEX file with DV-P and ACTF Kit
• ACTF “D” to download “L_29F400.HEX” into SRAM
• Download application HEXfile into FLASH
• Modify EEPROM jump addressto 0x80000
• Set STEP2 jumper
Production
There is no ROM socket on the board. The user’s application program must reside in SRAM for debugging in
STEP1, reside in battery-backed SRAM for the standalone field test in STEP2, and finally be programmed into the
on-board Flash for a complete product. For production, the user must produce an ACTF-downloadable HEX file for
the application, based on the DV-P Kit. The “STEP2” jumper (J2 pins 38-40) must be installed for every production-
version board.
Step 1 settings
In order to talk to CANE with Paradign C++, the CANE must meet these requirements:
1) EE40_115.HEX or EE80_115.HEX must be pre-loaded into Flash starting address 0xfa000.
2) The SRAM installed must be large enough to hold your program.

Chapter 1: Introduction CAN-Engine
1-6
For a 128K SRAM, the physical address is 0x00000-0x01ffff
For a 512K SRAM, the physical address is 0x00000-0x07ffff
3) The on-board CANE must have a Jump Address of 0xfa000.
4) The STEP2 jumper must be installed on J2 pins 38-40.
For further information on programming the CAN-Engine, refer to the manual on the TERN CD under:
tern_docs\manuals\software_kit.pdf.
The CANE works with most TERN expansion boards including the P50, P100, P300, MotionC, MMC, and Eye0.
Figure 1.4 CAN-Engine is installed on the top of the MotionC-P.

CAN-Engine Chapter 2: Installation
2-1
Chapter 2: Installation
2.1 Software Installation
Please refer to the “software_kit.pdf” technical manual on the TERN installation CD, under
tern_docs\manual\software_kit.pdf, for information on installing software.
2.2 Hardware Installation
Hardware installation consists primarily of connecting the microcontroller to your PC.
2.2.1 Connecting to the PC
The following diagram (Fig 2.1) provides the location of the debug serial port and the power jack. The
controller is linked to the PC via a serial cable (DB9-IDE) which is supplied with TERN’s EV-P / DV-P
Kits.
The controller communicates through SER0 by default. Install the 5x2 IDE connector on the SER0 5x2 pin
header. IMPORTANT: Note that the red side of the cable must point to pin 1 of the SER0 header. The
DB9 connector should be connected to one of your PC's COM Ports (COM1 or COM2).
2.2.2 Powering-on the CAN-Engine™
By factory default setting:
1) The RED STEP2 Jumper is installed. (Default setting in factory)
2) The DEBUG kernel is pre-loaded into the on-board flash starting at address of 0xFA000. (Default setting
in factory)
3) The EEPROM is set to jump address of 0xFA000. (Default setting in factory)
Connect +9-12V DC to the DC power terminal. The DC power jack adapter is center negative.
The on-board LED should blink twice and remain on, indicating the debug kernel is running and ready to
communicate with Paradigm C++ TERN Edition for programming and debugging.
(See next page for connection diagram).
Overview
•Connect PC-IDE serial cable:
For debugging (STEP 1), place IDE connector on SER0 (H1)
with red edge of cable at pin 1. This DEBUG cable is a 10-pin
IDE to DB9 cable, made by TERN (See Appendix D).
•Connect wall transformer:
Connect 9V wall transformer to power and plug into power jack
using power jack adapter supplied with EV-P/DV-P Kit

Chapter 2: Installation CAN-Engine
2-2
2.2.3 Connecting the CAN-Engine™
The proper connections required to debug the board (through Paradigm software).
H1 (Ser 0) is a 5x1 pin header. Use the back row of the IDE cable’s female header to connect to H1. (See
Appendix D)
Figure 2.1: Debug Cable (Ser0), Power Plug, and Step 2 Jumper shown
NOTE: Remember to watch for the “double blink” off the LED. This indicates the Debug Kernel has
been loaded with the jump address pointing to it. This is mandatory to commence downloading code
through the Paradigm environment.
Step 2 Jumper
H1 (Ser 0)
IDE
-
DB9
Debug
Cable
9-12 Volt
Power
plug
(Center
Negative)
CAN Port
CAN
Termination
Resistor.

CAN-Engine Chapter 3: Hardware
3-1
Chapter 3: Hardware
3.1 Am186ES/R8820/R1120 - Introduction
The Am186ES is based on industry-standard x86 architecture. The Am186ES controllers uses 16-bit
external data bus, are higher-performance, more integrated versions of the 80C188 microprocessors which
uses 8-bit external data bus. In addition, the Am186ES has new peripherals. The on-chip system interface
logic can minimize total system cost. The Am186ES has two asynchronous serial ports, 32 PIOs, a
watchdog timer, additional interrupt pins, a pulse width demodulation option, DMA to and from serial
ports, a 16-bit reset configuration register, and enhanced chip-select functionality.
R8820 is a drop-in replacement 5V, 40MHz chip for the AM186ES. Connecting J0.1=J0.2.
R1100 is a 80MHz, 3.3V chip can be installed on the E-Engine with J0.2=J0.3.
By default, the E-Engine uses 5V 40 MHz R8820 and low power 55-70 ns SRAM with battery backup.
Optional 3.3V 80 MHz R1120 can be installed.
At 80 MHz, the low power 55 ns SRAM with battery backup works fine but will not be able to support
DMA operation.
A fast 10/15/25 ns SRAM (Not low power) can be used to support zero wait state and DMA operation at 80
MHz, but the backup battery will be drain in few days.
There are three pads on the PCB for battery. One pads is ground, and the other two pads allowing a 3V
backup lithium battery is installed in two different positions:
1) The battery’s positive lead is installed in the pad which is away from the RTC, supporting the RTC only.
No battery backup for the SRAM.
2) The battery’s positive lead is installed in the pad which is closer to the RTC, supporting both RTC and
SRAM.
In the future, when the fast (10 ns) and low standby power SRAM is available, then 80 MHz E-Engine can
have both RTC and SRAM with battery backup plus the DMA, zero wait state operation.
User can use sample program c:\tern\186\samples\ee\rdc_id.c to read the ID register (0xfff4), in order to
identify RDC CPU type.
R1100=0xC5D9, R1120=0x85D9, R8820/30=0x04D9(xxD9)
3.2 Am186ES – Features
3.2.1 Clock and crystal
Due to its integrated clock generation circuitry, the Am186ES microcontroller allows the use of a times-one
crystal frequency. The design achieves 40 MHz CPU operation, while using a 40 MHz crystal.
The system CLKOUTA signal is routed to J1 pin 4, default 40 MHz for EE40.
CLKOUTA remains active during reset and bus hold conditions. The initial function ae_init(); disables
CLKOUTA and CLKOUTB with clka_en(0); and clkb_en(0);
You may use clka_en(1); to enable CLKOUTA=CLK=J1 pin 4.
The R8820 uses a 40 MHz crystal.
By default the 3.3V R1120 uses a 20 MHz crystal. The CPU speed is software programmable with the PLL.
At power-on, the on-board ACTF Flash programs the R1120 running at 20 MHz system clock, so a 9600
baud (instead 19,200 baud) is used for ACTF Manu.
Three debug kernels are available:

Chapter 3: Hardware CAN-Engine
3-2
c:\tern\186\rom\ae86\EE40_115.hex,
c:\tern\186\rom\ae86\EE80_115.hex,
c:\tern\186\rom\ae86\EE84_115.hex.
The EE40_115.hex will run the R8820 at 40 MHz, and the EE80_115.hex will run the R1120 at 80 MHz.
The EE84_115.hex will run the R1120 at 40 MHz
By default, the EE40_115.hex is pre-programmed for the 40 MHz CAN-Engine.
User can use software to setup the CPU speed:
outport(0xfff8,0x0103); // PLLCON, 20MHz crystal, 0103=40 MHz, 0107=80MHz
3.2.2 External Interrupts and Schmitt Trigger Input Buffer
There are eight external interrupts: INT0-INT6 and NMI.
/INT0, J2 pin 8, free to use.
/INT1, J2 pin 6, free to use.
INT2, J2 pin 19, RTC DS1337 alarm
/INT3, J2 pin 21, CAN
/INT4, J2 pin 33, used by 100M BaseT Ethernet
INT5=P12=DRQ0, J2 pin 5, used for LED/EE/HWD
INT6=P13=DRQ1, J2 pin 11, Free to use.
/NMI, J2 pin 7
Some of external interrupt inputs, /INT0, 1, 3, 4 and /NMI, are buffered by Schmitt-trigger inverters (U9,
74HC14), in order to increase noise immunity and transform slowly changing input signals to fast changing
and jitter-free signals. As a result of this buffering, these pins are capable of only acting as input.
These buffered external interrupt inputs require a falling edge (HIGH-to-LOW) to generate an interrupt.
The CAN-Engine uses vector interrupt functions to respond to external interrupts. Refer to the Am186ES
User’s manual for information about interrupt vectors.
3.2.3 Asynchronous Serial Ports
The Am186ES CPU has two asynchronous serial channels: SER0 and SER1. Both asynchronous serial
ports support the following:
•Full-duplex operation
•7-bit, 8-bit, and 9-bit data transfers
•Odd, even, and no parity
•One stop bit
•Error detection
•Hardware flow control
•DMA transfers to and from serial ports
•Transmit and receive interrupts for each port
•Multidrop 9-bit protocol support
•Maximum baud rate of 1/16 of the CPU clock speed
•Independent baud rate generators
The software drivers for each serial port implement a ring-buffered DMA receiving and ring-buffered
interrupt transmitting arrangement. See the samples files s1_echo.c and s0_echo.c.

CAN-Engine Chapter 3: Hardware
3-3
Important Note: For 80MHz CAN Engine, DMA functions are not available when by default low power 55
ns SRAM is installed. If install a 25 ns SRAM, 80MHz CANE can have all DMA functions, but it will
drain the backup battery fast. Two battery positive pads allowing the battery be installed:
1) Support both RTC and low power SRAM, or
2) Support only RTC.
3.2.4 Timer Control Unit
The timer/counter unit has three 16-bit programmable timers: Timer0, Timer1, and Timer2.
Timer0 and Timer1 are connected to external pins:
Timer0 output = P10 = J2 pin 12
Timer0 input = P11 = U7 EE pin 5
Timer1 output = P1 = J2 pin 29
Timer1 input = P0 = J2 pin 20
Timer0 input P11 is used and shared by on-board EE, LED, and HitWD, not recommended for other
external use.
The timer can be used to count or time external events, or can generate non-repetitive or variable-duty-cycle
waveforms.
Timer2 is not connected to any external pin. It can be used as an internal timer for real-time coding or time-
delay applications. It can also prescale timer 0 and timer 1 or be used as a DMA request source.
The maximum rate at which each timer can operate is 10 MHz, since each timer is serviced once every
fourth clock cycle. Timer output takes up to six clock cycles to respond to clock or gate events. See the
sample programs timer02.c and ae_cnt1.c in the tern\186\samples\ae directory.
3.2.5 PWM outputs and PWD
The Timer0 and Timer1 outputs can also be used to generate non-repetitive or variable-duty-cycle
waveforms. The timer output takes up to 6 clock cycles to respond to the clock input. Thus the minimum
timer output cycle is 25 ns x 6 = 150 ns (at 40 MHz).
Each timer has a maximum count register that defines the maximum value the timer will reach. Both Timer0
and Timer1 have secondary maximum count registers for variable duty cycle output. Using both the primary
and secondary maximum count registers lets the timer alternate between two maximum values.
MAX. COUNT A
MAX. COUNT B
Pulse Width Demodulation can be used to measure the input signal’s high and low phases on the /INT2=J2
pin 19.
3.2.6 Power-save Mode
The power-save mode of the Am186ES reduces power consumption and heat dissipation, thereby extending
battery life in portable systems. In power-save mode, operation of the CPU and internal peripherals
continues at a slower clock frequency. When an interrupt occurs, it automatically returns to its normal
operating frequency.

Chapter 3: Hardware CAN-Engine
3-4
3.3 Am186ES PIO lines
The Am186ES has 32 pins available as user-programmable I/O lines. Each of these pins can be used as a
user-programmable input or output signal, if the normal shared function is not needed. A PIO line can be
configured to operate as an input or output with or without a weak pull-up or pull-down, or as an open-drain
output. A pin’s behavior, either pull-up or pull-down, is pre-determined and shown in the table below.
After power-on/reset, PIO pins default to various configurations. The initialization routine provided by
TERN libraries reconfigures some of these pins as needed for specific on-board usage, as well. These
configurations, as well as the processor-internal peripheral usage configurations, are listed below in Table
3.1.
PIO Function Power-On/Reset status CAN-Engine Pin No. CAN-Engine Initial
P0 Timer1 in Input with pull-up J2 pin 20 Input with pull-up
P1 Timer1 out Input with pull-down J2 pin 29 Input with pull-down
P2 /PCS6/A2 Input with pull-up J2 pin 24 Input with pull-up
P3 /PCS5/A1 Input with pull-up J2 pin 15 Input with pull-up
P4 DT/R Normal J2 pin 38 Input with pull-up Step 2
P5 /DEN/DS Normal J2 pin 30 Input with pull-up
P6 SRDY Normal J2 pin 35 Input with pull-down
P7 A17 Normal U3 pin 22 A17
P8 A18 Normal U3 pin 23 A18
P9 A19 Normal J2 pin 10 A19
P10 Timer0 out Input with pull-down J2 pin 12 Input with pull-down
P11 Timer0 in Input with pull-up U7 EE pin 5 Input with pull-up
P12 DRQ0/INT5 Input with pull-up J2 pin 5 Output for LED/EE/HWD
P13 DRQ1/INT6 Input with pull-up J2 pin 11 Input with pull-up
P14 /MCS0 Input with pull-up J2 pin 37 Input with pull-up(ET)
P15 /MCS1 Input with pull-up J2 pin 23 Input with pull-up
P16 /PCS0 Input with pull-up J1 pin 19 /PCS0
P17 /PCS1 Input with pull-up J2 pin 13 CAN, ADC, CF select
P18 CTS1/PCS2 Input with pull-up J2 pin 22 Input with pull-up
P19 RTS1/PCS3 Input with pull-up J2 pin 31 Input with pull-up
P20 RTS0 Input with pull-up J2 pin 27 Input with pull-up
P21 CTS0 Input with pull-up J2 pin 36 Input with pull-up
P22 TxD0 Input with pull-up J2 pin 34 TxD0
P23 RxD0 Input with pull-up J2 pin 32 RxD0
P24 /MCS2 Input with pull-up J2 pin 17 Input with pull-up
P25 /MCS3 Input with pull-up J2 pin 18 Input with pull-up
P26 UZI Input with pull-up J2 pin 4 Input with pull-up*
P27 TxD1 Input with pull-up J2 pin 28 TxD1
P28 RxD1 Input with pull-up J2 pin 26 RxD1
P29 /CLKDIV2 Input with pull-up J2 pin 3 Input with pull-up*
P30 INT4 Input with pull-up J2 pin 33 Input with pull-up
P31 INT2 Input with pull-up J2 pin 19 Input with pull-up
* Note: P26 and P29 must NOT be forced low during power-on or reset.
Table 3.1 I/O pin default configuration after power-on or reset

CAN-Engine Chapter 3: Hardware
3-5
Three external interrupt lines are not shared with PIO pins:
INT0 = J2 pin 8
INT1 = J2 pin 6
INT3 = J2 pin 21
The 32 PIO lines, P0-P31, are configurable via two 16-bit registers, PIOMODE and PIODIRECTION. The
settings are as follows:
MODE PIOMODE reg. PIODIRECTION reg. PIN FUNCTION
0 0 0 Normal operation
1 0 1 INPUT with pull-up/pull-down
2 1 0 OUTPUT
3 1 1 INPUT without pull-up/pull-down
CAN-Engine initialization on PIO pins in ae_init() is listed below:
outport(0xff78,0xe73c); // PDIR1, TxD0, RxD0, TxD1, RxD1, P16=PCS0, P17=PCS1=PPI
outport(0xff76,0x0000); // PIOM1
outport(0xff72,0xec7b); // PDIR0, P12,A19,A18,A17,P2=PCS6=RTC
outport(0xff70,0x1000); // PIOM0, P12=LED
The C function in the library ae_lib can be used to initialize PIO pins.
void pio_init(char bit, char mode);
Where bit = 0-31 and mode = 0-3, see the table above.
Example: pio_init(12, 2); will set P12 as output
pio_init(1, 0); will set P1 as Timer1 output
void pio_wr(char bit, char dat);
pio_wr(12,1); set P12 pin high, if P12 is in output mode
pio_wr(12,0); set P12 pin low, if P12 is in output mode
unsigned int pio_rd(char port);
pio_rd (0); return 16-bit status of P0-P15, if corresponding pin is in input mode,
pio_rd (1); return 16-bit status of P16-P31, if corresponding pin is in input mode,
Some of the I/O lines are used by the CAN-Engine system for on-board components (Table 3.2). We
suggest that you not use these lines unless you are sure that you are not interfering with the operation of
such components (i.e., if the component is not installed).
You should also note that the external interrupt PIO pins INT2, 4, 5, and 6 are not available for use as
output because of the inverters attached. The input values of these PIO interrupt lines will also be inverted
for the same reason. As a result, calling pio_rd to read the value of P31 (INT2) will return 1 when pin 19
on header J2 is pulled low, with the result reversed if the pin is pulled high.
Signal Pin Function
P14 /MCS0 100M BaseT Ethernet
P4 /DT STEP2 jumper
P11 Timer0 input Shared with RTC, EE data input
P12 DRQ0/INT5 Output for LED or U7 serial EE clock or Hit watchdog
P17 /PCS1 CAN, ADC
P22 TxD0 Default SER0 debug

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Signal Pin Function
P23 RxD0 Default SER0 debug
/INT4 J2 pin 33 Ethernet interrupt, if U8 is installed
Table 3.2 I/O lines used for on-board components
3.4 I/O Mapped Devices
3.4.1 I/O Space
External I/O devices can use I/O mapping for access. You can access such I/O devices with inportb(port) or
outportb(port,dat). These functions will transfer one byte or word of data to the specified I/O address. The
external I/O space is 64K, ranging from 0x0000 to 0xffff.
The default I/O access time is 15 wait states. You may use the function void io_wait(char wait) to define the
I/O wait states from 0 to 15. The system clock is 25 ns ( or 50 ns), giving a clock speed of 40 MHz (or 20
MHz). Details regarding this can be found in the Software chapter, and in the Am186ES User’s Manual.
Slower components, such as most LCD interfaces, might find the maximum programmable wait state of 15
cycles still insufficient. Due to the high bus speed of the system, some components need to be attached to
I/O pins directly.
For details regarding the chip select unit, please see Chapter 5 of the Am186ES User’s Manual.
The table below shows more information about I/O mapping.
I/O space Select Location Usage
0x0000-0x00ff /PCS0 J1 pin 19=P16 USER*
0x0100-0x0103 /PCS1 J2 pin 13=P17 U4 pin 4-5
0x0200-0x02ff /PCS2 J2 pin 22=CTS1 USER
0x0300-0x03ff /PCS3 J2 pin 31=RTS1 USER
0x0400-0x04ff /PCS4 Reserved
0x0500-0x05ff /PCS5 J2 pin 15=P3 USER
0x0600-0x06ff /PCS6 J2 pin 24=P2 USER
*PCS0 may be used for other TERN peripheral boards.
To illustrate how to interface the CAN-Engine with external I/O boards, a simple decoding circuit for
interfacing to an 82C55 parallel I/O chip is shown in Figure 3.1.
/WR
/RD
/SEL20
A0
A1
D0-D7
/CS
/WR
/RD
82C55
RST P00-P07
P10-P17
P20-P27
1
/PCS0
A7
6
VCC
4
3
2
5
A5
A6 /SEL20
/SELF0
/SELC0
/SELA0
/SEL80
/SEL60
/SEL40
14
13
12
11
10
9
7
NC
15
74HC138
C
A
B
G2A
G2B
G1
Y2
Y3
Y4
Y5
Y6
Y7
Y1
Y0
Figure 3.1 Interface to external I/O devices

CAN-Engine Chapter 3: Hardware
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The function ae_init() by default initializes the /PCS0 line at base I/O address starting at 0x00. You
can read from the 82C55 with inportb(0x020) or write to the 82C55 with outportb(0x020,dat). The call to
inportb(0x020) will activate /PCS0, as well as putting the address 0x00 over the address bus. The decoder
will select the 82C55 based on address lines A5-7, and the data bus will be used to read the appropriate data
from the off-board component.
3.5 Other Devices
A number of other devices are also available. Some of these are optional, and might not be installed on the
particular controller you are using. For a discussion regarding the software interface for these components,
please see the Software chapter.
3.5.1 On-board Supervisor with Watchdog Timer
The MAX691/LTC691 (U6) is a supervisor chip. With it installed, the CAN-Engine has several functions:
watchdog timer, battery backup, power-on-reset delay, power-supply monitoring, and power-failure
warning. These will significantly improve system reliability.
Watchdog Timer
The watchdog timer is activated by setting a jumper on J5 of the CAN-Engine. The watchdog timer
provides a means of verifying proper software execution. In the user's application program, calls to the
function hitwd() (a routine that toggles the P12=HWD pin of the MAX691) should be arranged such that
the HWD pin is accessed at least once every 1.6 seconds. If the J5 jumper is on and the HWD pin is not
accessed within this time-out period, the watchdog timer pulls the WDO pin low, which asserts /RESET.
This automatic assertion of /RESET may recover the application program if something is wrong. After the
CAN-Engine is reset, the WDO remains low until a transition occurs at the WDI pin of the MAX691. When
controllers are shipped from the factory the J5 jumper is off, which disables the watchdog timer.
The Am186ES has an internal watchdog timer. This is disabled by default with ae_init().

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Figure 3.2 Location of watchdog timer enable jumper
Power-failure Warning
The supervisor supports power-failure warning and backup battery protection. When power failure is
sensed by the PFI=J1.11, pin 9 of the MAX691 (lower than 1.3 V), the PFO is low. The PFI pin 9 of 691 is
directly shorted to VCC by default. In order to use PFI externally, cut the trace and bring the PFI signal out.
You may design an NMI service routine to take protect actions before the +5V drops and processor dies.
The following circuit shows how you might use the power-failure detection logic within your application.
47K
2K
PFI, pin 9 of MAX691
(1.3 V min)
(8.35 V min)
9-14 V
C?
VCC = +5V
Using the supervisor chip for power failure detection
Battery Backup Protection
The backup battery protection protects data stored in the SRAM and RTC. The battery-switch-over circuit
compares VCC to VBAT (+3 V lithium battery positive pin), and connects whichever is higher to the
VRAM (power for SRAM and RTC). Thus, the SRAM and the real-time clock are backed up. In normal
J5 WatchDog

CAN-Engine Chapter 3: Hardware
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use, the lithium battery should last about 3-5 years without external power being supplied. When the
external power is on, the battery-switch-over circuit will select the VCC to connect to the VRAM.
3.5.2 EEPROM
A serial EEPROM of 512 bytes (24C04), or optional 2K bytes (24C16) can be installed in U7. The CAN-
Engine uses the P12=SCL (serial clock) and P11=SDA (serial data) to interface with the EEPROM. The
EEPROM can be used to store important data such as a node address, calibration coefficients, and
configuration codes. It typically has 1,000,000 erase/write cycles. The data retention is more than 40 years.
EEPROM can be read and written by simply calling the functions ee_rd() and ee_wr().
A range of lower addresses in the EEPROM is reserved for TERN use. Details regarding which addresses
are reserved, and for what purpose, can be found in Appendix E of this manual.
3.5.3 AD7655, 16-bit parallel high speed ADC
The unique 16-bit parallel ADC (AD7655, 0-5V) supports ultra high-speed (1 MHz conversion rate) analog
signal acquisition. The AD7655 contains two low noise, high bandwidth track-and-hold amplifiers that
allow simultaneous sampling on two channels. Each track-and hold amplifier has a multiplexer in front to
provide a total of 4 channels analog inputs. The parallel ADC achieves very high throughput by requiring
only two CPU I/O operations (one start, one read) to complete a 16-bit ADC reading. With a precision
external 2.5V reference, the ADC accepts 0-5V analog inputs at 16-bit resolution of 0-65,535.
See sample program \tern\186\samples\ee\ee_ad.c for details on reading the ADC. The sample program is
also included in the pre-built sample project; \tern\186\samples\ee\ee.ide.
Refer to the data sheet for additional specifications; \tern_docs\parts\ad7655.pdf.
3.5.4 CAN
The CAN-Engine supports an on-board Controller Area Network (CAN) controller(SJA1000, Philips). It
supports network baud rates up to 1M-bit per second. Software drivers allow access to all CAN controller
registers, as well as a buffering software layer.
The CAN bus is a balanced (differential) 2-wire interface running over either a Shielded Twisted Pair
(STP), Un-shielded Twisted Pair (UTP), or Ribbon cable.
CAN Bus Electrical Interface Circuit

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A number of different data rates are defined, with 1Mbps (Bits per second) being the top end, and 10kbps
the minimum rate. Cable length depends on the data rate used. Normally all the devices in a system transfer
uniform and fixed bit-rates. The maximum line length is 1Km, 40 meters at 1Mbps. Termination resistors
are used at each end of the cable. The worst-case transmission time of an 8-byte frame with an 11-bit
identifier is 134 bit times (that's 134 microseconds at the maximum baud rate of 1Mbits/sec).
The CAN Bus interface uses an asynchronous transmission scheme controlled by start and stop bits at the
beginning and end of each character. This interface is used, employing serial binary interchange.
Information is passed from transmitters to receivers in a data frame. The data frame is composed of an
Arbitration field, Control field, Data field, CRC field, ACK field. The frame begins with a 'Start of frame'
[SOF], and ends with an 'End of frame' [EOF] space. The data field may be from 0 to 8 bits.
The CAN bus pinout on J3 is shown below. It is a compact 0.1” spacing 3x2 pin header. User can use a
IDE10-DB9 flat cable from TERN to connect CAN signals to an external standard DB9 CAN connector in
the field.
3.5.5 100 MHz BaseT Ethernet
An WizNet™ Fast Ethernet Module can be installed to provide 100M Base-T network connectivity. This
Ethernet module has a hardware LSI TCP/IP stack. It implements TCP/IP, UDP, ICMP and ARP in
hardware, supporting internet protocol DLC and MAC. It has 16KB internal transmit and receiving buffer
which is mapped into host processor’s direct memory. The host can access the buffer via high speed DMA
transfers. The hardware Ethernet module releases internet connectivity and protocol processing from the
host processor. It supports 4 independent stack connections simultaneously at a 4Mbps protocol
processing speed. An RJ45 8-pin connector is on-board for connecting to 10/100 Base-T Ethernet network.
A software library is available for Ethernet connectivity.
3.5.6 Dual 12-bit DAC (LTC1446)
The LTC1446/LTC1446L is a dual 12-bit digital-to-analog converter (DAC) in an SO-8 package. It is
complete with a rail-to-rail voltage output amplifier, an internal reference and a 3-wire serial interface. The
LTC1446 outputs a full-scale of 4.096V, making 1 LSB equal to 1 mV. The LTC1446L outputs a full-scale
of 2.5 V, making 1 LSB equal to 0.61 mV. The buffered outputs can source or sink 5 mA.
The DAC (U0) outputs are routed to J3 pin 9 for channel A, and pin 10 for channel B.