Tews Technologies TAMC640 User manual

The Embedded I/O Company
TAMC640
Virtex-5 AMC with FMC Slot
Version 1.0
User Manual
Issue 1.0.5
November 2016
TEWS TECHNOLOGIES GmbH
Am Bahnhof 7
25469 Halstenbek, Germany
Phone: [phone]
Fax: [phone]
e-mail: [email protected]
www.tews.com

TAMC640-10R
XC5VLX50T-1, 256 MB DDR2, 2MB QDR-II,
Mid-Size front panel
TAMC640-11R
same as TAMC640-10R but Full-Size front panel
TAMC640-12R
XC5VLX85T-1, 256 MB DDR2, 2MB QDR-II,
Mid-Size front panel
TAMC640-13R
same as TAMC640-12R but Full-Size front panel
TAMC640-14R
XC5VSX50T-1, 256 MB DDR2, 2MB QDR-II Mid-
Size front panel
TAMC640-15R
same as TAMC640-14R but Full-Size front panel
This document contains information, which is
proprietary to TEWS TECHNOL
OGIES GmbH. Any
reproduction without written permission is forbidden.
TEWS TECHNOLOGIES GmbH has made any
effort to ensure that this manual is accurate and
complete. However TEWS TECHNOLOGIES GmbH
reserves the right to change the product described
in this document at any time without notice.
TEWS TECHNOLOGIES GmbH is not liable for any
damage arising out of the application or use of the
device described herein.
Style Conventions
Hexadecimal characters are specified with prefix 0x,
i.e. 0x029E (that means hexadecimal value 029E).
For signals on hardware products, an ‚Active Low’ is
represented by the signal name with # following, i.e.
IP_RESET#.
Access terms are described as:
W Write Only
R Read Only
R/W Read/Write
R/C Read/Clear
R/S Read/Set
2011-2016 by TEWS TECHNOLOGIES GmbH
All trademarks mentioned are property of their respective owners.
TAMC640 User Manual Issue 1.0.5 Page 2 of 69

Issue
Description
Date
1.0.0 Initial Issue May 2011
1.0.1 corrected value of “Power Requirements as per Module Current
Requirement Record (max.)” in chapter “Technical Specification” June 2011
1.0.2 - Revised chapters “SPI-Flash” and “FPGA Configuration”. Added
information and warning about the relationship between indirect SPI-
programming with Xilinx Impact and the FPGA Mode Pins.
- Corrected SPI Interface Pinning in Appendix B
July 2011
1.0.3 Update to V1.0 Rev. B:
- Changed default FPGA configuration mode to “Master SelectMap”
- Changed DIP-Switch 3 from “USER_SWITCH_CPLD” to “FPGA
Configuration Source selection”
- Table with worst case FPGA Configuration Times added
- Pin assignment for (post configuration) user SPI access changed
- Chapter “Design Help” moved to the end of the document, and
chapter “Troubleshooting” added.
November 2011
1.0.4 Correction of the interchanged DIP-Switch SW1 and SW2 descriptions.
This affects:
- Table 5-12 “configuration DIP-Switch SW1-SW2 Settings” in
chapter 5.11 “JTAG”
- Table 6-1 “DIP Switch” in chapter 6.2 “DIP-Switch”
Samtec Part Number of the FMC Connector corrected (chapter 9.4)
January 2012
1.0.5 - Typo corrected in Table 5-2
- Typo corrected in Table 9-2 November 2016
TAMC640 User Manual Issue 1.0.5 Page 3 of 69

Table of Contents
1PRODUCT DESCRIPTION ...........................................................................................8
2TECHNICAL SPECIFICATION ...................................................................................10
3HANDLING AND OPERATION INSTRUCTION .........................................................12
3.1 ESD Protection..............................................................................................................................12
3.2 Thermal Considerations...............................................................................................................12
3.3 Mid-Size Option Usage Restrictions...........................................................................................12
3.4 I/O Signaling Voltages..................................................................................................................12
3.5 Voltage Limits on FMCs ...............................................................................................................12
4IPMI SUPPORT...........................................................................................................13
4.1 Temperature and Voltage Sensors..............................................................................................13
4.1.1 Sensor Locations....................................................................................................................13
4.2 FRU Information............................................................................................................................14
4.2.1 Internal Use Area....................................................................................................................14
4.2.2 Board Info Area.......................................................................................................................15
4.2.3 Product Info Area....................................................................................................................15
4.2.4 Multi Record Area...................................................................................................................16
4.2.4.1 Module Current Requirements ..........................................................................................16
4.2.4.2 AMC Point-to-Point Connectivity.......................................................................................16
4.2.4.3 Clock Configuration ...........................................................................................................17
4.2.5 Modifying FRU Records..........................................................................................................17
5FUNCTIONAL DESCRIPTION....................................................................................18
5.1 AMC Interface................................................................................................................................20
5.2 FMC Interface ................................................................................................................................20
5.2.1 VADJ.......................................................................................................................................22
5.3 Memory Interfaces ........................................................................................................................22
5.3.1 SPI-Flash................................................................................................................................22
5.3.2 QDR-II SRAM .........................................................................................................................23
5.3.3 DDR2 SDRAM........................................................................................................................23
5.4 Reset ..............................................................................................................................................24
5.5 GPIO ...............................................................................................................................................25
5.6 I2C ...................................................................................................................................................25
5.7 UART ..............................................................................................................................................26
5.8 Multi-Gigabit Transceiver (GTPs)................................................................................................27
5.9 Configuration.................................................................................................................................28
5.9.1 Board Configuration CPLD (BCC)..........................................................................................28
5.9.2 FPGA Configuration................................................................................................................29
5.9.3 Clock Configuration.................................................................................................................31
5.10 Clocks ............................................................................................................................................33
5.10.1 GTP Reference Clock Generator............................................................................................34
5.11 JTAG...............................................................................................................................................35
5.12 Thermal Management...................................................................................................................36
6BOARD CONFIGURATION ........................................................................................37
6.1 Overview ........................................................................................................................................37
6.2 DIP-Switch .....................................................................................................................................37
6.3 Battery............................................................................................................................................38
6.4 Debug Connector..........................................................................................................................38
TAMC640 User Manual Issue 1.0.5 Page 4 of 69

7INSTALLATION ..........................................................................................................39
7.1 Installation of a FMC Module .......................................................................................................39
7.1.1 Using FMCs with Mid-Size faceplates....................................................................................39
7.1.2 Voltage Limits on FMC Modules.............................................................................................39
7.2 AMC Module Insertion & Hot-Swap.............................................................................................40
7.2.1 Insertion..................................................................................................................................40
7.2.2 Extraction................................................................................................................................40
8INDICATORS ..............................................................................................................41
8.1 Front Panel LEDs ..........................................................................................................................41
8.2 On board LEDs..............................................................................................................................41
9I/O CONNECTORS .....................................................................................................43
9.1 Overview ........................................................................................................................................43
9.2 I/O Circuitry....................................................................................................................................43
9.2.1 Differential Signaling...............................................................................................................43
9.3 AMC-Connector X4 .......................................................................................................................44
9.4 FMC HPC Connector X2 ...............................................................................................................46
9.5 Debug-Connector X1 ....................................................................................................................49
10 DESIGN HELP ............................................................................................................50
10.1 GTP Reference Clock Generator Configuration ........................................................................50
10.2 Example Design ............................................................................................................................50
10.3 Troubleshooting............................................................................................................................51
10.3.1 Board does not power up........................................................................................................51
10.3.2 DONE is always off.................................................................................................................51
10.3.3 INIT LED stays illuminated (red).............................................................................................51
11 APPENDIX A...............................................................................................................52
12 APPENDIX B...............................................................................................................58
TAMC640 User Manual Issue 1.0.5 Page 5 of 69

List of Figures
FIGURE 1-1 : BLOCK DIAGRAM......................................................................................................................9
FIGURE 4-1 : TEMP. SENSOR LOCATIONS..................................................................................................13
FIGURE 5-1 : TAMC640 FUNCTIONAL BLOCK DIAGRAM..........................................................................18
FIGURE 5-2 : AMC INTERFACE DIAGRAM ..................................................................................................20
FIGURE 5-3 : FMC INTERFACE TO VIRTEX-5 FPGA ..................................................................................21
FIGURE 5-4 : A FMC MODULE......................................................................................................................22
FIGURE 5-5 : QDR-II SRAM INTERFACE TO FPGA.....................................................................................23
FIGURE 5-6 : DDR2 SDRAM INTERFACES TO FPGA.................................................................................24
FIGURE 5-7 : RESET STRUCTURE ..............................................................................................................24
FIGURE 5-8 : I2C BUS STRUCTURE OVERVIEW........................................................................................26
FIGURE 5-9 : GTP BLOCK DIAGRAM...........................................................................................................27
FIGURE 5-10: BOARD CONFIGURATION CPLD BLOCK DIAGRAM...........................................................28
FIGURE 5-11: CLOCK CONFIGURATION......................................................................................................32
FIGURE 5-12: FPGA CLOCK SOURCES.......................................................................................................33
FIGURE 5-13: JTAG-CHAIN SEGMENTATION.............................................................................................35
FIGURE 6-1 : PRE-INSERTION BOARD CONFIGURATION OVERVIEW....................................................37
FIGURE 7-1 : USING FMCS WITH MID-SIZE FACEPLATES .......................................................................39
FIGURE 8-1 : FRONT PANEL LED VIEW ......................................................................................................41
FIGURE 8-2 : ON BOARD LED VIEW ............................................................................................................41
FIGURE 9-1: CONNECTOR POSITIONS – SIDE 1 .......................................................................................43
FIGURE 9-2: CONNECTOR POSITION – SIDE 2..........................................................................................43
TAMC640 User Manual Issue 1.0.5 Page 6 of 69

List of Tables
TABLE 2-1 : TECHNICAL SPECIFICATION...................................................................................................11
TABLE 4-1 : TEMPERATURE AND VOLTAGE SENSORS...........................................................................13
TABLE 4-2 : FRU INFORMATION..................................................................................................................14
TABLE 4-3 : INTERNAL USE AREA...............................................................................................................14
TABLE 4-4 : BOARD INFO AREA...................................................................................................................15
TABLE 4-5 : PRODUCT INFO AREA..............................................................................................................15
TABLE 4-6 : MODULE CURRENT REQUIREMENT (W/O FMC)...................................................................16
TABLE 4-7 : AMC POINT-TO-POINT CONNECTIVITY .................................................................................17
TABLE 4-8 : CLOCK CONFIGURATION........................................................................................................17
TABLE 5-1 : TAMC640 FPGA FEATURE OVERVIEW ..................................................................................19
TABLE 5-2 : FPGA BANK USAGE..................................................................................................................19
TABLE 5-3: FMC-SUPPLIES ..........................................................................................................................21
TABLE 5-4 : GENERAL PURPOSE I/O..........................................................................................................25
TABLE 5-5 : I2C BUS SIGNALS .....................................................................................................................25
TABLE 5-6 : FPGA UART ...............................................................................................................................26
TABLE 5-7 : WORST CASE FPGA CONFIGURATION TIMES .....................................................................30
TABLE 5-8 : TCLK TRANSCEIVER CONFIGURATION.................................................................................31
TABLE 5-9 : JITTER ATTENUATOR CONFIGURATION...............................................................................31
TABLE 5-10: AVAILABLE FPGA CLOCKS.....................................................................................................34
TABLE 5-11: PROGRAMMABLE GTP REFERENCE CLOCK........................................................................35
TABLE 5-12: CONFIGURATION DIP-SWITCH SW1-SW2 SETTINGS.........................................................36
TABLE 6-1 : DIP-SWITCH...............................................................................................................................37
TABLE 7-1 : VOLTAGE LIMITS ON FMC MODULES....................................................................................39
TABLE 7-2 : HOT-SWAP STATES .................................................................................................................40
TABLE 8-1 : FRONT PANEL LEDS................................................................................................................41
TABLE 8-2 : BOARD-STATUS LEDS.............................................................................................................42
TABLE 9-1: PIN ASSIGNMENT AMC CONNECTOR X4...............................................................................45
TABLE 9-2: PIN ASSIGNMENT FMC-CONNECTOR X2 ROW F-K...............................................................47
TABLE 9-3: PIN ASSIGNMENT FMC-CONNECTOR X2 ROW A-E ..............................................................48
TABLE 9-4: PIN ASSIGNMENT DEBUG CONNECTOR X1 ..........................................................................49
TAMC640 User Manual Issue 1.0.5 Page 7 of 69

1 Product Description
The TAMC640 is a standard single Mid-Size or Full-Size AMC module providing a user configurable Virtex-5
FPGA. The integrated PCIe Endpoint Block of the Virtex-5 can be used to build an x1, x4 or x8 PCIe link via
AMC Port 4-11. The implementation of other protocols like SRIO or XAUI is also possible. AMC Ports 0 & 1,
commonly used for Gigabit Ethernet, are also connected to the FPGA. The integrated Gigabit Ethernet
MACs of the Virtex-5 allow fast and easy protocol implementation.
To allow direct board-to-board communication, AMC Ports 12-17 are connected to Virtex-5 I/Os, allowing
AC-coupled LVDS communication with a port speed up to 1.0Gb/sec.
For flexible I/O solutions the TAMC640 provides a VITA 57.1 high pin count FMC Module slot, allowing active
and passive signal conditioning. All FMC I/O lines are directly connected to the FPGA, which maintains the
flexibility of the Select I/O technology of the Virtex-5 FPGA.
In addition, the FPGA is connected to the following external memories:
•two banks of DDR2 DRAM (up to 128 M x 16 (256 MB) each)
•one bank of QDR-II SRAM (up to 4 M x 18 (8 MB))
Multiple clocks from the AMC-interface, the FMC and from on-board sources are supplied to the FPGA.
The FPGA is configured by a flash device, which is in-system programmable and able to store multiple code
versions.
The TAMC640 supports encrypted FPGA bitstream usage. Encrypted FPGA bitstreams cannot be copied or
reverse engineered, securing your intellectual property.
The IPMI Connectivity Records located inside the Module Management Controller (MMC) can be modified by
the customer (e.g. via IPMI), to adapt to the different possible communication protocols (PCIe, SRIO, XAUI,
...).
User applications for the TAMC640 require the full ISE Foundation software, which must be purchased from
Xilinx.
The Engineering Documentation TAMC640-ED includes all information needed for customer specific FPGA
programming. The FPGA Development Kit TAMC640-FDK includes the engineering documentation, ucf-files
with all necessary pin assignments and basic timing constraints, and a well documented VHDL example
application. This example application is called TPLD002 (Tews Programmable Logic Design) and covers the
main functionalities of the TAMC640 like DMA capable PCIe endpoint with interrupt support, register
mapping, DDR2 and QDR-II memory access and basic I/O to the FMC slot. It comes as a Xilinx ISE project
with source code and as a ready-to-download bitstream. It is the basis for fast and reliable customer
application development, and can significantly reduce time to market.
Software support for the TPLD002 is available for all major operating systems.
In-circuit programming and debugging of the FPGA design (e.g. using Xilinx “ChipScope”) is supported. The
Program and Debug Box TA900 allows access to the module while it is inserted in a system. It provides
access to the module's JTAG Chain, the UART of the on-board Module Management Controller (MMC) and
to two user pins of the Virtex-5 FPGA. If a UART core is implemented in the FPGA, serial communication via
the TA900 is possible.
The TA900 can be accessed by USB 2.0 and by a 14-pin JTAG Header (e.g. for connecting a Xilinx Platform
Cable).
For First-Time-Buyers the TA900 and the TAMC640-ED or TAMC640-FDK is recommended.
TAMC640 User Manual Issue 1.0.5 Page 8 of 69

Figure 1-1 : Block Diagram
TAMC640 User Manual Issue 1.0.5 Page 9 of 69

2 Technical Specification
AMC Interface
Mechanical Interface
Advanced Mezzanine Card (AMC) Interface conforming to
PICMG® AMC.0 R2.0 (Advanced Mezzanine Card Base
Specification)
Module Type: Single Mid-Size module or Single Full-Size module
(see data sheet for order information)
Electrical Interface
Virtex-5 GTPs connected to AMC port 0, 1, 4 - 11
Virtex-5 LVDS Transceivers connected to port 12-15 & 17
TCLKA-D connected to FPGA
IPMI
IPMI Version
1.5
Front Panel LEDs
Blue Hot-Swap LED
Red Failure Indication LED (LED1)
Green Board OK / User LED (LED2)
On Board Devices
PCIe Endpoint
Virtex-5 integrated PCI Express Endpoint Block
User configurable FPGA
Virtex-5 (Xilinx)
XC5VLX50T, XC5VLX85T,
XC5VSX50T
(see data sheet for order information)
Configuration Flash 2 x Xilinx XCF32P, 32 MBit each
SPI-Flash MP25P64 (Micron) 64 Mbit (can be used for FPGA configuration)
DDR2 SDRAM 2 x Micron MT47H64M16 (64M x 16)
QDR-II SRAM 1 x IDT 71P74804 (1M x 18)
Programmable Clock
Generator
Si5338B (Silicon Labs)
I/O Interface
I/O Connector
FMC high pin count slot according to VITA 57.1 (FPGA Mezzanine
Card (FMC) Standard)
User Defined Signals 80 differential or 160 single-ended I/O plus 4 differential Clocks
Multi-Gigabit-Interfaces 2 gigabit data plus 1 gigabit reference clocks
TAMC640 User Manual Issue 1.0.5 Page 10 of 69

Physical Data
Power Requirements
Depends on FPGA design.
400 mA typical @ +12V DC (Payload Power, Blank FPGA)
40 mA typical @ +3.3V DC (Management Power)
3.3A as per Module Current Requirement Record (max.)
Additional power is used by the FMC.
Temperature Range Operating
Storage 0°C to +70°C -40°C to +85°C
MTBF 306000 h
MTBF values shown are based on calculation according to MIL-HDBK-217F and
MIL-HDBK-217F Notice 2; Environment: GB20°C.
The MTBF calculation is based on component FIT rates provided by the
component suppliers. If FIT rates are not available, MIL-HDBK-217F and
MIL-HDBK-217F Notice 2 formulas are used for FIT rate calculation.
Humidity 5 – 95 % non-condensing
Weight 190 g
Table 2-1 : Technical Specification
TAMC640 User Manual Issue 1.0.5 Page 11 of 69

3 Handling and Operation Instruction
ESD Protection3.1
The TAMC640 is sensitive to static electricity. Packing, unpacking
and all other handling of the TAMC640 has to be done in an ESD/EOS
protected Area.
Thermal Considerations3.2
Forced air cooling is recommended during operation. Without forced
air cooling, damage to the device will occur.
Mid-Size Option Usage Restrictions3.3
Please note that the Mid-Size module has restrictions to its usage
because of a component height violation. It is within the
responsibility of the user to carefully check if the Mid-Size module
with its component height violation can be used in the system.
Otherwise damage to the TAMC640 or the slot it is used in may
occur!
Refer to the chapter “Using FMCs with Mid-Size faceplates” for
details.
I/O Signaling Voltages3.4
The FPGA I/O-Lines to the FMC Slot are directly connected to the
FPGA I/O pins. The I/O voltage of these FPGA I/O pins is 3.3V
maximum.
The FPGA I/O pins are NOT 5V tolerant.
Voltage Limits on FMCs3.5
The AMC.0 specification limits the voltages on AMC modules. These
limits also apply to mounted FMCs.
Refer to the chapter “Voltage Limits on FMC Modules” for details.
TAMC640 User Manual Issue 1.0.5 Page 12 of 69

4 IPMI Support
The TAMC640 provides a Module Management Controller (MMC) that performs health monitoring, hot-swap
functionality and Field Replaceable Unit (FRU) information storage. The MMC communicates via an
Intelligent Platform Management Interface (IPMI) with its superordinated IPMI controller / shelf manager.
Temperature and Voltage Sensors4.1
The MMC monitors on board sensors and reports sensor events to the superordinated IPMI controller / shelf
manager.
Sensor Number Signal Type Thresholds
1
Signal Monitored
0 Event - Hot-swap switch
1 Temperature lcr lnc unc ucr FPGA Temp.
2 Temperature lcr lnc unc ucr Board Temp.
3
Temperature
lcr lnc unc ucr
FMC Air Temp.
4 Voltage lcr lnc unc ucr PWR
5 Voltage lcr lnc unc ucr +12V (FMC)
6
Voltage
lcr lnc unc ucr
+5V
7 Voltage lcr lnc unc ucr V
ADJ
(FMC)
Table 4-1 : Temperature and Voltage Sensors
4.1.1 Sensor Locations
FPGA Temp.
FMC Air Temp.
Board Temp.
(bottom)
Figure 4-1 : Temp. Sensor Locations
1unr: upper non-recoverable, ucr: upper critical, unc: upper non-critical lnc: lower non-critical, lcr: lower
critical, lnr: lower non-recoverable
TAMC640 User Manual Issue 1.0.5 Page 13 of 69

FRU Information4.2
The MMC stores the module FRU information in a non-volatile EEPROM. Some of the records are writeable
to allow adapting the TAMC640 to user FPGA designs. If records are modified, the user is responsible to set
the affected checksums to correct values.
Area
Size (in Bytes)
Writeable
Common Header 8 no
Internal Use Area 72 yes
Chassis Info Area
0
no
Board Info Area variable no
Product Info Area variable no
Multi Record Area variable see below
Module Current
Requirements variable yes
AMC Point-to-Point
Connectivity variable yes
Clock Configuration variable yes
Table 4-2 : FRU Information
4.2.1 Internal Use Area
The TAMC640 uses the Internal Use Area to store default FMC-slot settings for the case that a module is
present, but no valid FRU information is found. The value of “Fallback-Voltage for VADJ” determines what
happens in this case. If the “Fallback-Voltage for VADJ” is set to 0x0000, the module won’t turn on. Any
other value sets VADJ to “Fallback-Voltage for VADJ” * 10mV, as long this value is within the range defined
by Minimum VADJ and Maximum VADJ. Example: 0x00FA = 250 * 10mV = 2.5V.
Product Information
Value
Internal Use Format Version 0x01
TEWS IUA Format-Version 0x01
Present FMC Slots 0x01 – FMC-slot #0
Fallback-Voltage for VADJ 0x0000 – if no valid FMC-FRU is found, the TAMC640
won’t turn on.
Minimum VADJ 0x0078 – 1200mV for TAMC640
Maximum VADJ 0x014A – 3300mV for TAMC640
Table 4-3 : Internal Use Area
The whole Internal Use Area is writeable, but if changes become necessary, only the Fallback-Voltage for
VADJ should be altered.
TAMC640 User Manual Issue 1.0.5 Page 14 of 69

4.2.2 Board Info Area
Product Information
Value
Version 0x01
Language Code 0x00 - English
Manufacturer date/time determined at manufacturing
Board manufacturer TEWS TECHNOLOGIES GmbH
Board product name TAMC640
Board serial number determined at manufacturing (see board label)
Board part number TAMC640-xxR
-xx = -10 / -11 / -12 / -13 / -14 / -15
Table 4-4 : Board Info Area
4.2.3 Product Info Area
Product Information Value
Version
0x01
Language Code 0x00 - English
Product manufacturer TEWS TECHNOLOGIES GmbH
Product name
TAMC640
Board part/model number TAMC640-xxR
-xx = -10 / -11 / -12 / -13 / -14 / -15
Product version
V1.0 Rev. B (see board label)
Product serial number determined at manufacturing (see board label)
Asset tag
= Product serial Number
Table 4-5 : Product Info Area
TAMC640 User Manual Issue 1.0.5 Page 15 of 69

4.2.4 Multi Record Area
4.2.4.1 Module Current Requirements
The “Current Draw” value holds the Payload Power (PWR) requirement of the module given as current
requirement in units of 0.1A at 12V.
The AMC module announces the sum of “Current Draw” and FMC Current Requirement as current demand
to the shelf manager. If the power budget for the AMC slot is smaller than this value, the shelf manager may
not enable Payload power for the slot.
If required, the “Current Draw” value in the Module Current Requirements record may be modified to a value
that falls within the given power budget. Make sure that the modified value still satisfies the AMC module
power requirements for the actual FPGA content.
Product Information Value
Current Draw 0x2F (4.7 A)
Table 4-6 : Module Current Requirement (w/o FMC)
4.2.4.2 AMC Point-to-Point Connectivity
The TAMC640’s Virtex-5 FPGA allows implementing a wide range of interfaces (Serial RapidIO, PCI-
Express, Gig.-Eth., XAUI, etc.). The MMC stores a Connectivity Record for each interface that is
implemented by the TAMC640. By default, the MMC of the TAMC640 stores the following Connectivity
Records:
•2x GbE Links on AMC Ports 0-1
•x1 2.5 Gbps PCI-Express Gen1 Link on AMC Port 4
•x4 2.5 Gbps PCI-Express Gen1 Link on AMC Port 4-7
•x8 2.5 Gbps PCI-Express Gen1 Link on AMC Port 4-11
Channel Port Link Type Link Type Extension Link Grouping ID Asymmetric Match
0 0 AMC.2 Ethernet 1000BASE-BX
Ethernet Link Single Channel Link exact match
1 1 AMC.2 Ethernet 1000BASE-BX
Ethernet Link Single Channel Link exact match
2 4 AMC.1 PCI
Express
Gen 1 PCI Express,
non-SSC Single Channel Link matches with 10
Gen 1 PCI Express,
SSC
3 4-7 AMC.1 PCI
Express
Gen 1 PCI Express,
non-SSC Single Channel Link matches with 10
Gen 1 PCI Express,
SSC
4 4-7 AMC.1 PCI
Express
Gen 1 PCI Express,
non-SSC 0x1 matches with 10
Gen 1 PCI Express,
SSC
TAMC640 User Manual Issue 1.0.5 Page 16 of 69

5 8-11 AMC.1 PCI
Express
Gen 1 PCI Express,
non-SSC 0x1 matches with 10
Gen 1 PCI Express,
SSC
Table 4-7 : AMC Point-to-Point Connectivity
4.2.4.3 Clock Configuration
AMC FCLKA should be used as the PCI Express Reference Clock. TCLKA – D are all inputs by default, but
can independently be changed to outputs.
Clock ID Clock Features Clock Family Clock
Accuracy
Clock
Frequency
FCLKA
Clock Receiver,
connected through Jitter
Attenuator and
programmable Clock
Generator
PCI Express PCI Express
Gen 1 100 MHz nom
TCLKA Clock Receiver misc - -
TCLKB Clock Receiver misc - -
TCLKC Clock Receiver misc - -
TCLKD Clock Receiver misc - -
Table 4-8 : Clock Configuration
4.2.5 Modifying FRU Records
Some of the records are writeable to allow adapting the TAMC640 to user FPGA designs. If records are
modified, the user is responsible to set the affected checksums to correct values.
TAMC640 User Manual Issue 1.0.5 Page 17 of 69

5 Functional Description
This chapter gives a brief overview of the various module functions.
x16 Data
x16 Data
MGT to Port 0-1
2 MGTs
M-LVDS
Transceiver
Virtex-5
AMC
Connector
DDR2 DDR2
QDR-II
Platform
Flash Platform
Flash
50MHz
Clock
50MHz
Clock
32MHz
Clock
Battery
50MHz
Clock
MMC
x18 Data
Clocks
160 I/Os
I2C
MGT to Port 4-11
LVDSto Port 12-17
M-LVDS
Common Options Region
Fat Pipe Region
Extended Options Region
TCLK A - D
FCLKA
GTP Ref.-Clocks
Debug
Connector
UART
GPIO
JTAG*
JTAG*
Data
Control
Control
Board
Configuration
CPLD
(BCC)
Config Data
Config Control
PL_LED2
I2C
DIP
Switch
JitterAttenuator
Si5338
M[2:0]
Rev.-Sel
Reset#
USER-LED_CTRL
USER LED
(Front Panel)
FMC-Slot
* The JTAGChain is not shown in this drawing
See the corresponding chapter for information
about the JTAG Chain.
Reset#
Control
SPI
I2C
EEPROM
Flash
Figure 5-1 : TAMC640 Functional Block Diagram
The FPGA is a Virtex-5 LX50T, LX85T or SX50T FPGA. Each FPGA provides four Gigabit Ethernet MACs,
and one Endpoint Blocks for PCI Express.
TAMC640 User Manual Issue 1.0.5 Page 18 of 69

Virtex-5 Logic
Cells DSP48A1 Slices
Block
RAM
(Kb) CMTs Ethernet
MACs PCIe Endpoint GTP / GTX Transceiver Power PC
LX50T 46,080 48 2,160 6 4 1 12 / - -
LX85T 82,944 48 3,888 6 4 1 12 / - -
SX50T 52,224 288 4,752 6 4 1 12 / - -
Table 5-1 : TAMC640 FPGA Feature Overview
The FPGA is equipped with 14 I/O banks and 12 Multi-Gigabit Transceivers.
I/O Bank
VCCO
VREF
Signals
Remarks
0 2.5V - Configuration no user I/Os
1 VCC_B VREF_B_M2C FMC HB[17:21]
2 2.5V - AMC Tx12 -15 + Configuration
3 VADJ VREF_A_M2C FMC HA[17:23] + 50MHz Clock
4 2.5V - AMC TCLK
FMC CLK + AMC Tx 17
11 VADJ VREF_A_M2C FMC LA[17:33]
12 1.8V 0.9V QDR-II Bank 0
13 VADJ VREF_A_M2C FMC LA[00:16]
15 VADJ VREF_A_M2C FMC HA[00:16]
17 1.8V 0.9V DDR2 Bank 1
18 1.8V 0.9V DDR2 Bank 0 + AMC Rx 12-15 & 17
19 VCC_B VREF_B_M2C FMC HB[00:16]
20 1.8V - QDR-II Bank 0
21 1.8V 0.9V DDR2 Bank 1 + GPIO
22 1.8V 0.9V DDR2 Bank 0 + GPIO
GTP Bank Description Remarks
112 (X0Y3) AMC Backplane, Port 6 & 7
114 (X0Y2) AMC Backplane, Port 8 & 9
116 (X0Y4) AMC Backplane, Port 4 & 5
118 (X0Y1) AMC Backplane, Port 10 & 11
120 (X0Y5) AMC Backplane, Port 0 & 1
122 (X0Y0) FMC, DP 0 & 1
Table 5-2 : FPGA Bank Usage
All FMC I/O lines are directly connected to the FPGA-pins. Refer to the Xilinx UG190: Virtex-5 FPGA User
Guide for SelectIO interface signal standards, slew rate control and current drive strength capabilities.
The board supports FPGA configuration via JTAG, from a Platform Flash or a SPI-Flash.
TAMC640 User Manual Issue 1.0.5 Page 19 of 69

AMC Interface5.1
AMC Ports 0, 1 & 4 – 11 are connected to Virtex-5 GTP transceivers. Ports 12-17 are connected to Virtex-5
LVDS Receivers / Transmitters. All Ports provide on board AC-coupling on the Rx and Tx lines.
FCLKA, commonly used as PCI-Express reference clock, is feed into a powerful clock distribution that allows
using this clock on any FPGA GTP transceiver needed.
TCLKA – TCLKD are accessible by the Virtex-5 FPGA via M-LVDS transceivers that allow their use as inputs
or outputs. All TCLKx inputs are lead on FPGA global clock buffers.
Virtex-5
GTP 0
GTP 1
Ref.-Clk
GTP 0
GTP 1
Ref.-Clk
GTP 0
GTP 1
Ref.-Clk
GTP 0
GTP 1
Ref.-Clk
GTP 0
GTP 1
Ref.-Clk
Port 0
ICS874001I-05
FCLKA
100 MHz
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
Port 7
Port 8
Port 9
Port 10
Port 11
50MHz
Clock
Port 12
Port 13
Port 14
Port 15
Port 17
Rx12_C
Tx12_C
LVDS
Transmitter / Receiver
Rx14_C
Tx14_C
Rx15_C
Tx15_C
Rx16_C
Tx16_C
Rx13_C
Tx13_C
Global Clock
Output
Global Clock
Output
Global Clock
Output
Global Clock
Output
AMC-Connector AMC-Connector
TCLKA
TCLKB
TCLKC
TCLKD
TCLKA_Rx
TCLKB_Rx
TCLKC_Rx
TCLKD_Rx
TCLKA_Tx
TCLKB_Tx
TCLKC_Tx
TCLKD_Tx
Si5338
M-LVDSTransceiver
GTP_
DUAL
120
(X0_Y5)
GTP_
DUAL
116
(X0_Y4)
GTP_
DUAL
112
(X0_Y3)
GTP_
DUAL
114
(X0_Y2)
GTP_
DUAL
118
(X0_Y1)
Figure 5-2 : AMC Interface Diagram
FMC Interface5.2
Instead of a front I/O Connector, the TAMC640 offers a FPGA Mezzanine Card (FMC) module slot. This
allows a wide range of connectors to be used with the TAMC640 and customer specific I/O solutions can be
easily applied.
The FMC module can adapt the TAMC640 to various I/O standards, either mechanical (connector) or
electrical.
TAMC640 User Manual Issue 1.0.5 Page 20 of 69