Tews Technologies TPMC467-10R User manual

The Embedded I/O Company
TPMC467
4 Channel RS232/RS422/RS485
Programmable Serial Interface
Version 1.0
User Manual
Issue 1.0.4
August 2014
TEWS TECHNOLOGIES GmbH
Am Bahnhof 7
25469 Halstenbek, Germany
Phone: [phone] Fax: [phone]
e-mail: [email protected]om
www.tews.com

TPMC467-10R
4 Channel RS232/RS422/RS485 Programmable
Serial Interface, front panel I/O
TPMC467-11R
4 Channel RS232/RS422/RS485 Programmable
Serial Interface, front panel I/O with non standard
RJ45 I/O pinout
This document contains information, which is
proprietary to TEWS TECHNOLOGIES GmbH. Any
reproduction without written permission is forbidden.
TEWS TECHNOLOGIES GmbH has made any
effort to ensure that this manual is accura
te and
complete. However TEWS TECHNOLOGIES GmbH
reserves the right to change the product described
in this document at any time without notice.
TEWS TECHNOLOGIES GmbH is not liable for any
damage arising out of the application or use of the
device described herein.
Style Conventions
Hexadecimal characters are specified with prefix 0x,
i.e. 0x029E (that means hexadecimal value 029E).
For signals on hardware products, an ‚Active Low’ is
represented by the signal name with # following, i.e.
IP_RESET#.
Access terms are described as:
W Write Only
R Read Only
R/W Read/Write
R/C Read/Clear
R/S Read/Set
2014 by TEWS TECHNOLOGIES GmbH
All trademarks mentioned are property of their respective owners.
TPMC467 User Manual Issue 1.0.4 Page 2 of 30

Issue Description Date
1.0 First Issue August 2006
1.1 New address TEWS LLC September 2006
1.2 Technical Specification update January 2007
1.0.3 New notation for HW Engineering Documentation Releases December 2009
1.0.4 General Revision August 2014
TPMC467 User Manual Issue 1.0.4 Page 3 of 30

Table of Contents
1PRODUCT DESCRIPTION.........................................................................................6
2TECHNICAL SPECIFICATION...................................................................................7
3LOCAL SPACE ADDRESSING..................................................................................9
3.1 XR17D154 Local Space Configuration..........................................................................................9
3.2 Device Configuration Space ..........................................................................................................9
3.2.1 UART Register Sets .........................................................................................................10
3.2.2 Device Configuration Registers........................................................................................11
3.2.3 UART Channel Configuration Registers...........................................................................12
4XR17D154 TARGET CHIP .......................................................................................14
4.1 PCI Configuration Registers (PCR).............................................................................................14
4.2 Configuration EEPROM................................................................................................................15
5CONFIGURATION HINTS........................................................................................17
5.1 CPLD Description..........................................................................................................................17
5.1.1 CPLD Address Map..........................................................................................................17
5.1.2 Channel Control Register .................................................................................................17
5.2 CPLD Access.................................................................................................................................18
5.2.1 Accessing XR17D154 MPIO-Pins....................................................................................19
5.2.2 CPLD-Bus Protocol...........................................................................................................19
5.2.2.1 Write............................................................................................................................19
5.2.2.2 Read............................................................................................................................20
5.3 Serial Interface Channel Setup....................................................................................................21
5.3.1 Special Features...............................................................................................................21
5.3.1.1 Auto RS485 Operation................................................................................................21
5.3.1.2 RS485 Receiver Control.............................................................................................21
5.3.1.3 Slew Rate Limiting ......................................................................................................22
5.3.1.4 Low-Power Shutdown.................................................................................................22
5.3.2 Channel Setup..................................................................................................................22
5.4 RS485/RS422 Configuration Examples.......................................................................................23
5.4.1 RS422 Multidrop...............................................................................................................23
5.4.2 RS422 Full Duplex Point to Point.....................................................................................23
5.4.3 RS485 Full Duplex Point to Point.....................................................................................23
5.4.4 RS485 Half Duplex Point to Point.....................................................................................24
5.4.5 RS485 Full Duplex Multi-point..........................................................................................24
5.4.6 RS485 Half Duplex Multi-point .........................................................................................25
5.5 I/O Electrical Interface ..................................................................................................................25
5.5.1 ±15kV ESD Protection......................................................................................................25
5.5.2 RS232 Transceivers.........................................................................................................25
5.5.3 RS485/RS422 Transceivers.............................................................................................25
5.5.4 Termination.......................................................................................................................26
5.6 Block Diagram...............................................................................................................................26
6PROGRAMMING HINTS ..........................................................................................27
6.1 UART Baud Rate Programming...................................................................................................27
7PIN ASSIGNMENT – I/O CONNECTOR ..................................................................29
7.1 Front Panel I/O Connector (TPMC467-10R)................................................................................29
7.2 Front Panel I/O Connector (TPMC467-11R)................................................................................29
7.3 Serial Channel to Front Panel Port Mapping..............................................................................30
TPMC467 User Manual Issue 1.0.4 Page 4 of 30

List of Figures
FIGURE 1-1 : BLOCK DIAGRAM......................................................................................................................6
FIGURE 5-1 : CPLD-BUS BLOCK DIAGRAM ................................................................................................18
FIGURE 5-2 : CPLD-BUS WRITE...................................................................................................................19
FIGURE 5-3 : CPLD-BUS READ ....................................................................................................................20
FIGURE 5-4 : RS422 MULTIDROP CONFIGURATION.................................................................................23
FIGURE 5-5: RS422 FULL DUPLEX POINT TO POINT CONFIGURATION.................................................23
FIGURE 5-6: RS485 FULL DUPLEX POINT TO POINT CONFIGURATION.................................................23
FIGURE 5-7: RS485 HALF DUPLEX POINT TO POINT CONFIGURATION ................................................24
FIGURE 5-8: RS485 FULL DUPLEX MULTI-POINT CONFIGURATION.......................................................24
FIGURE 5-9: RS485 HALF DUPLEX MULTI-POINT CONFIGURATION ......................................................25
FIGURE 5-10: I/O BLOCK DIAGRAM.............................................................................................................26
FIGURE 7-1 : I/O CONNECTOR PINOUT......................................................................................................29
List of Tables
TABLE 2-1 : TECHNICAL SPECIFICATION.....................................................................................................8
TABLE 3-1 : XR17D154 LOCAL SPACE CONFIGURATION...........................................................................9
TABLE 3-2 : DEVICE CONFIGURATION SPACE............................................................................................9
TABLE 3-3 : UART REGISTER SET OFFSET ...............................................................................................10
TABLE 3-4 : UART REGISTER SET...............................................................................................................10
TABLE 3-5 : DEVICE CONFIGURATION REGISTERS.................................................................................11
TABLE 3-6 : UART CHANNEL CONFIGURATION REGISTERS...................................................................12
TABLE 4-1 : PCI HEADER..............................................................................................................................14
TABLE 4-2 : CONFIGURATION EEPROM TPMC467-XX..............................................................................15
TABLE 4-3 : PHYSICAL CONFIGURATION EEPROM DATA .......................................................................16
TABLE 5-1 : CPLD REGISTER ADDRESS MAP............................................................................................17
TABLE 5-2 : CHANNEL CONTROL REGISTER.............................................................................................18
TABLE 5-3 : MPIO PINS .................................................................................................................................18
TABLE 5-4 : MPIO DEVICE CONFIGURATION REGISTERS.......................................................................19
TABLE 5-5 : SERIAL CHANNEL SETUP........................................................................................................22
TABLE 6-1 : UART BAUD RATE PROGRAMMING .......................................................................................27
TABLE 7-1 : PIN ASSIGNMENT RJ45 FRONT PANEL I/O CONNECTOR...................................................29
TABLE 7-2 : PIN ASSIGNMENT RJ45 FRONT PANEL I/O CONNECTOR...................................................29
TABLE 7-3 : SERIAL CHANNEL TO FRONT PANEL PORT MAPPING........................................................30
TPMC467 User Manual Issue 1.0.4 Page 5 of 30

1Product Description
The TPMC467 is a standard single-width 32 bit PMC module and offers 4 channels of high
performance RS232/RS422/RS485 programmable serial interface. The module offers front panel I/O
with four RJ45 type connectors. The TPMC467-10R provides a RJ45 I/O pinout according to EIA-
232D. The TPMC467-11R provides a non standard RJ45 I/O pinout (as used on Motorola CPU
boards).
The serial channels can be individually programmed to operate as RS232, RS422 or RS485 full
duplex/half duplex interface. In addition programmable termination is provided for the RS422/RS485
interfaces. After power-up all serial I/O lines are in a high impedance state.
Each RS232 channel supports RxD, TxD, RTS, CTS and GND. RS422 and RS485 full duplex support
a four wire interface (RX+, RX-, TX+, TX-) plus ground (GND). RS485 half duplex supports a two wire
interface (DX+, DX-) plus ground (GND).
Each channel has 64 byte transmit and receive FIFOs to significantly reduce the overhead required to
provide data to and get data from the transmitters and receivers. The FIFO trigger levels are
programmable and the baud rate is individually programmable up to 921.6 kbps for RS232 channels
and 5.5296 Mbps for RS422 channels. The UART offers readable FIFO levels.
All channels generate interrupts on PCI interrupt INTA. For fast interrupt source detection the UART
provides a special Global Interrupt Source Register.
All serial channels use ESD protected transceivers. ESD protection is up to ±15KV.
The TPMC467 can operate with 3.3V and 5.0V PCI I/O signaling voltage.
Figure 1-1 : Block Diagram
TPMC467 User Manual Issue 1.0.4 Page 6 of 30

2Technical Specification
PMC Interface
Mechanical Interface PCI Mezzanine Card (PMC) Interface
Single Size
Electrical Interface PCI Rev. 2.3 compliant
33 MHz / 32 bit PCI
3.3V and 5V PCI Signaling Voltage
On Board Devices
PCI Target Chip
XR17D154 (Exar)
Quad UART
XR17D154 (Exar)
Transceiver
MAX3161E
I/O Interface
Interface Type
Asynchronous serial interface
Number of Channels
4
Physical Interface Software selectable RS232, RS422, RS485 full duplex, RS485
half duplex
Serial Channel I/O Signals RS232: TxD, RxD, RTS, CTS, GND
RS422/RS485 Full Duplex: TxD+/-, RxD+/-, GND
RS485 Half Duplex: Dx+/-, GND
Termination Software selectable 120Ω
Programmable Baud Rates RS232: up to 921.6 kbps
RS422: up to 5.5296 Mbps
ESD Protection
±15kV - Human Body Model
I/O Connector
4x RJ45 Modular Jack (AMP 406 732-1)
Front I/O Pinout RS232 (TPMC467-10R): Compliant to TIA/EIA-561 (EIA-232D)
RS232 (TPMC467-11R): Compliant to TIP866-TM-20
RS422 (TPMC467-11R): Compliant to TIP866-TM-20
Physical Data
Power Requirements 40 mA typical @ +5V DC (Shutdown, no load)
45 mA typical @ +5V DC (RS232, no load)
75 mA typical @ +5V DC (RS422, no load)
235 mA typical @ +5V DC (RS485 FD Master, no load)
210 mA typical @ +5V DC (RS485 HD, no load)
25 mA typical @ +3.3V DC (no load)
Temperature Range Operating
Storage -40°C to +85°C -55°C to +125°C
TPMC467 User Manual Issue 1.0.4 Page 7 of 30

MTBF TPMC467-10R: 360 000 h
TPMC467-11R: 360 000 h
MTBF values shown are based on calculation according to MIL-HDBK-217F and
MIL-HDBK-217F Notice 2; Environment: GB20°C.
The MTBF calculation is based on component FIT rates provided by the
component suppliers. If FIT rates are not available, MIL-HDBK-217F and
MIL-HDBK-217F Notice 2 formulas are used for FIT rate calculation.
Humidity
5 – 95 % non-condensing
Weight
69 g
Table 2-1 : Technical Specification
TPMC467 User Manual Issue 1.0.4 Page 8 of 30

3 Local Space Addressing
3.1XR17D154 Local Space Configuration
The local on board addressable regions are accessed from the PCI side by using the XR17D154 local
space.
XR17D154 PCI Base
Address
(Offset in PCI
Configuration
Space)
PCI
Space
Mapping
Size
(Byte) Port
Width
(Bit)
Endian
Mode Description
0 (0x10) MEM 2048 32 BIG Device Configuration
Space
Table 3-1 : XR17D154 Local Space Configuration
3.2Device Configuration Space
PCI Base Address: XR17D154 PCI Base Address 0 (Offset 0x10 in PCI Configuration
Space).
The TPMC467 uses the Exar XR17D154 Quad UART to provide and control the 4 channels.
Device Configuration Space
Content PCI Address Size
(Bit)
UART 0 Register Set PCI Base Address 0 + (0x0000 to 0x007F) 32
Device Configuration Registers PCI Base Address 0 + (0x0080 to 0x009F) 32
UART 0 Register Set PCI Base Address 0 + (0x0100 to 0x01FF) 32
UART 1 Register Set PCI Base Address 0 + (0x0200 to 0x03FF) 32
UART 2 Register Set PCI Base Address 0 + (0x0400 to 0x05FF) 32
UART 3 Register Set PCI Base Address 0 + (0x0600 to 0x07FF) 32
Table 3-2 : Device Configuration Space
All registers can be accessed in 8, 16 or 32 bit width with exception to one special case: When reading
the receive data together with its LSR register content, the host must read them in 16 or 32 bits format
in order to maintain integrity of the data byte with its associated error flags.
TPMC467 User Manual Issue 1.0.4 Page 9 of 30

3.2.1 UART Register Sets
The Device Configuration Space provides a register set for each of the 4 UARTs.
UART Register Set Register Set Offset
Serial Channel 0 0x0000
Serial Channel 1 0x0200
Serial Channel 2 0x0400
Serial Channel 3 0x0600
Table 3-3 : UART Register Set Offset
Offset Address Description Access Data Width
0x000 – 0x00F UART Channel Configuration Registers
First 8 registers are 16550 compatible R/W 8, 16, 32
0x010 – 0x07F Reserved - -
0x080 – 0x093 Channel 0: Device Configuration Registers
All other channels: Reserved R/W 8, 16, 32
0x094 – 0x0FF Reserved - -
0x100 Read FIFO – 64 bytes of RX FIFO data R 8, 16, 32
Write FIFO – 64 bytes of TX FIFO data W 8, 16, 32
0x140 – 0x17F Reserved - -
0x180 – 0x1FF Read FIFO with errors –
64 bytes of RX FIFO data + LSR R 16, 32
Table 3-4 : UART Register Set
TPMC467 User Manual Issue 1.0.4 Page 10 of 30

3.2.2 Device Configuration Registers
The Device Configuration Registers control general operating conditions and monitor the status of
various functions. This includes a 16 bit general purpose counter, multipurpose input/outputs (not
supported by the TPMC467), sleep mode, soft-reset and device identification, and revision. They are
embedded inside the UART 0 Register Set.
Address Register Description Access Reset
Value
0x080 INT0 [7:0] Channel Interrupt Indicator R 0x00
0x081 INT1 [15:8] Interrupt Source Details R 0x00
0x082 INT2 [23:16] R 0x00
0x083 INT3 [31:24] R 0x00
0x084 TIMERCNTL Timer Control Register R/W 0x00
0x085 TIMER Reserved - 0x00
0x086 TIMERLSB Programmable Timer Value R/W 0x00
0x087 TIMERMSB R/W 0x00
0x088 8XMODE Sampling Rate Select R/W 0x00
0x089 REGA Reserved - 0x00
0x08A RESET UART Reset W 0x00
0x08B SLEEP UART Sleep Mode Enable R/W 0x00
0x08C DREV Device Revision R 0x01
0x08D DVID Device Identification R 0x28
0x08E REGB Simultaneous UART Write & EEPROM Interface W 0x00
0x08F MPIOINT MPIO Interrupt Mask R/W 0x00
0x090 MPIOLVL MPIO Level Control R/W 0x00
0x091 MPIO3T MPIO Output Pin Tri-state Control R/W 0x00
0x092 MPIOINV MPIO Input Polarity Select R/W 0x00
0x093 MPIOSEL MPIO Input/Output Select R/W 0xFF
Table 3-5 : Device Configuration Registers
For a detailed description of the Device Configuration Registers please refer to the XR17D154 data
sheet which is available on the Exar website (www.exar.com).
TPMC467 User Manual Issue 1.0.4 Page 11 of 30

3.2.3 UART Channel Configuration Registers
Each UART channel has its own set of internal UART configuration registers for its own operation
control and status reporting. The following table provides the register offsets within a register set,
access types and access control:
Register
Offset
Comment Register Access Reset
Value
16550 Compatible
0x00 LCR[7] = 0 RHR – Receive Holding Register
THR – Transmit Holding Register R 0xXX
W
LCR[7] = 1 DLL – Baud Rate Generator Divisor Latch Low R/W 0xXX
0x01 LCR[7] = 0 IER – Interrupt Enable Register R/W 0x00
LCR[7] = 1 DLM – Baud Rate Generator Divisor Latch High R/W 0xXX
0x02 ISR – Interrupt Status Register
FCR – FIFO Control Register R 0x01
W0x00
0x03 LCR – Line Control Register R/W 0x00
0x04 MCR – Modem Control Register R/W 0x00
0x05 LSR – Line Status Register
Reserved R 0x60
W
0x06 MSR – Modem Status Register
MSR – Auto RS485 Delay (not supported by the
TPMC467)
R 0xX0
W
0x07 User Data SPR – Scratch Pad Register R/W 0xFF
Enhanced Registers
0x08 FCTR – Feature Control Register R/W 0x00
0x09 EFR – Enhanced Function Register R/W 0x00
0x0A TXCNT – Transmit FIFO Level Counter
TXTRG – Transmit FIFO Trigger Level R 0x00
W
0x0B RXCNT – Receiver FIFO Level Counter
RXTRG – Receiver FIFO Trigger Level R 0x00
W
0x0C Xchar – Xon, Xoff Received Flags
Xoff-1 – Xoff Character 1 R 0x00
W
0x0D Reserved
Xoff-2 – Xoff Character 2 R0x00
W
0x0E Reserved
Xon-1 – Xon Character 1 R0x00
W
0x0F Reserved
Xon-2 – Xon Character 2 R0x00
W
Table 3-6 : UART Channel Configuration Registers
TPMC467 User Manual Issue 1.0.4 Page 12 of 30

The address for a UART Channel Configuration Register x in a UART Register Set for channel y
is:
PCI Base Address 0 (PCI Base Address for the UART Register Space)
+ UART Register Set Offset for channel y
+ Register Offset for register x
Addressing example:
The address for the LCR register of UART channel 2 is:
PCI Base Address (PCI Base Address for the Device Configuration Space)
+ 0x0400 (Offset of the UART register set for serial channel 2)
+ 0x0003 (Offset of the LCR register within a UART register set)
For a detailed description of the serial channel registers please refer to the XR17D154 data sheet
which is available on the Exar website (www.exar.com).
TPMC467 User Manual Issue 1.0.4 Page 13 of 30

4 XR17D154 Target Chip
4.1 PCI Configuration Registers (PCR)
PCI CFG
Register
Address
Write ‘0’ to all unused (Reserved) bits PCI
writeable
Initial Values
(Hex Values)
31 24 23 16 15 8 7 0
0x00 Device ID Vendor ID N 01D3 1498
0x04 Status Command Y 0080 0000
0x08 Class Code Revision ID N 070002??
0x0C BIST Header Type PCI Latency
Timer Cache Line Size N 00 00 00 00
0x10 Memory Base Address Register (BAR) Y FFFFF000
0x14 I/O Base Address Register (Unimplemented) N 00000000
0x18 Base Address Register 0 (Unimplemented) N 00000000
0x1C Base Address Register 1 (Unimplemented) N 00000000
0x20 Base Address Register 2 (Unimplemented) N 00000000
0x24 Base Address Register 3 (Unimplemented) N 00000000
0x28 Reserved N 00000000
0x2C Subsystem ID Subsystem Vendor ID N s.b. 1498
0x30 Expansion ROM Base Address (Unimplemented) N 00000000
0x34 Reserved N 00000000
0x38 Reserved N 00000000
0x3C Max_Lat Min_Gnt Interrupt Pin Interrupt Line Y[7:0] 00 00 01 00
Table 4-1 : PCI Header
Device-ID: 0x01D3 TPMC467
Vendor-ID: 0x1498 TEWS TECHNOLOGIES
Revision ID: XR17D154 silicon revision
Subsystem-ID: 0x000A
0x000B -10R -11R
Subsystem
Vendor-ID: 0x1498 TEWS TECHNOLOGIES
TPMC467 User Manual Issue 1.0.4 Page 14 of 30

4.2 Configuration EEPROM
After power-on or PCI reset, the XR17D154 loads initial configuration register data from the on board
configuration EEPROM.
The configuration EEPROM contains the following configuration data:
•Vendor ID
•Vendor Device ID
•SubSystem Vendor ID
•SubSystem Device ID
See the XR17D154 Manual for more information.
Address Configuration Register
Configuration
Register Offset Value
0x00 Vendor ID 0x02 0x1498
0x01 Device ID 0x00 0x01D3
0x02 Subsystem Vendor ID 0x2E 0x1498
0x03 Subsystem ID 0x2C s.b.
Table 4-2 : Configuration EEPROM TPMC467-xx
Subsystem-ID Value (Offset 0x0C): TPMC467-10R 0x000A
TPMC467-11R 0x000B
The words following the configuration data contain:
•The module version and revision
•The UART clock frequency in Hz
•The physical interface attached to the serial channels
•The maximal baud rate of the transceivers in bps
•The supported control signals of the serial channels
For the physical interfaces and the control signals applies: Bit 3 represents UART channel 3 and bit 0
represents UART channel 0. The appropriate bit is set to ‘1’ for each UART channel attached to the
physical interface represented by the word. Bit 15 to bit 4 are always ‘0’.
TPMC467 User Manual Issue 1.0.4 Page 15 of 30

Address Configuration Register TPMC467-10R
TPMC467-11R
0x04 Module Version 0x0100 0x0100
0x05 Module Revision 0x0000 0x0000
0x06 EEPROM Revision 0x0002 0x0002
0x07 Oscillator Frequency (high) 0x02A3 0x02A3
0x08 Oscillator Frequency (low) 0x0000 0x0000
0x09-0x0F Reserved - -
0x10 RS232 Channels 0x000F 0x000F
0x11 RS422 Channels 0x000F 0x000F
0x12 TTL Channels 0x0000 0x0000
0x13 RS485 Full Duplex Channels
0x000F 0x000F
0x14 RS485 Half Duplex Channels
0x000F 0x000F
0x15-0x1E Reserved - -
0x1F Programmable Interfaces 0x000F 0x000F
0x20 Max Data Rate RS232 (high) 0x000F 0x000F
0x21 Max Data Rate RS232 (low) 0x4240 0x4240
0x22 Max Data Rate RS422 (high) 0x0098 0x0098
0x23 Max Data Rate RS422 (low) 0x9680 0x9680
0x24 Max Data Rate TTL (high) 0x0000 0x0000
0x25 Max Data Rate TTL (low) 0x0000 0x0000
0x26 Max Data Rate RS485 Full Duplex (high) 0x0098 0x0098
0x27 Max Data Rate RS485 Full Duplex (low) 0x9680 0x9680
0x28 Max Data Rate RS485 Half Duplex (high) 0x0098 0x0098
0x29 Max Data Rate RS485 Half Duplex (low) 0x9680 0x9680
0x2A-0x2F Reserved - -
0x30 RxD & TxD 0x000F 0x000F
0x31
RTS & CTS
0x0000
0x0000
0x32 Full modem 0x0000 0x0000
0x33-0x37 Reserved - -
0x38 Enhanced RTS & CTS
(Front or Back I/O only) 0x0000 0x0000
0x39 Enhanced Full modem
(Front or Back I/O only) 0x0000 0x0000
0x3A Channels with enhanced RTS & CTS
Support for RS232 only 0x000F 0x000F
0x3B-0x3F Reserved - -
Table 4-3 : Physical Configuration EEPROM Data
TPMC467 User Manual Issue 1.0.4 Page 16 of 30

5 Configuration Hints
The TPMC467 physical interfaces of the serial channels are individually software programmable to
various interface configurations. For this purpose a CPLD provides a control register for each interface
channel.
5.1CPLD Description
The CPLD provides a Channel Control Register for each of the interface channels. Each of the
Channel Control Registers is individually addressable. The access to this registers is described in
detail in chapter “5.2 CPLD Access”.
5.1.1 CPLD Address Map
Refer to the following chart for the register addresses.
Address
Register Name
Size (Bit)
000 Control Register Channel 0 7
001 Control Register Channel 1 7
010 Control Register Channel 2 7
011 Control Register Channel 3 7
Table 5-1 : CPLD Register Address Map
5.1.2 Channel Control Register
This register is identical for all channels.
Bit Symbol Description Access Reset
Value
6 SHDN Active-Low Shutdown-Control. Drive SHDN high to shut down
transmitters and charge pump.
‘0’: Normal operation
‘1’: Shutdown
R/W 1
5 SLEW
LIMIT Transmitter Speed-Select. Select slew-rate limiting for RS232 and RS485. Slew-rate limits with a logic-level high.
‘0’: Normal data rate limit (RS232: 1 Mbps; RS485: 10 Mbps)
‘1’: Limit data rate to 250 kbps (both RS232 & RS485)
R/W 0
4 TTERM Transmitter Termination Enable
Terminate transmit line with a 120Ωtermination resistor
‘0’: Termination inactive
‘1’: Termination active
R/W 0
3 RTERM Receiver Termination Enable
Terminate receive line with a 120Ωtermination resistor
‘0’: Termination inactive
‘1’: Termination active
R/W 0
TPMC467 User Manual Issue 1.0.4 Page 17 of 30

Bit Symbol Description Access Reset
Value
2 RENA Auto RS485 Receiver Enable
When the Auto RTS Control feature of the XR17D154 is used
in half duplex configurations, this bit can be used to inhibit the
reception of an echo of the own data transmission
‘0’: Normal operation (receiver is always enabled)
‘1’: Inhibit echo reception (receiver is disabled during data
transmission)
R/W 0
1 HDPLX Selectable Mode Functionality. Operates in full-duplex mode
when low; operates in half-duplex mode when high.
‘0’: Full-duplex
‘1’: Half-Duplex
R/W 0
0 RS485/
RS232# Selectable Mode Functionality. Operates as RS485 with a logic-level high; operates as RS232 with a logic-level low.
‘0’: RS232
‘1’: RS485
R/W 0
Table 5-2 : Channel Control Register
5.2CPLD Access
The CPLD it is connected to the MPIO-pins of the XR17D154 to provide access to the control
registers.
PCI Bus
MPIO
XR17D154 CPLD Transceiver
CH0
CH1
CH2
CH3
Reg. CH0
Reg. CH1
Reg. CH2
Reg. CH3
Figure 5-1 : CPLD-Bus Block Diagram
The MPIO-pins form a simple bus to the CPLD. The following chart gives an overview about the MPIO
pin assignment:
MPIO Pin Direction Function
MPIO[0] Output CEN – Chip Enable
MPIO[1] Output R/W# - Read/Write
Low: Write to Address
High: Read from Address
MPIO[2] Output CLK – Clock
MPIO[5-3] Output ADR – Register Address
MPIO[6] Output DATAOUT – Serial Data Output
MPIO[7] Input DATAIN – Serial Data Input
Table 5-3 : MPIO Pins
TPMC467 User Manual Issue 1.0.4 Page 18 of 30

5.2.1 Accessing XR17D154 MPIO-Pins
The MPIO Registers are accessible at PCI Base Address 0 + Device Configuration Register Offset.
Address
Offset
Register Description Access Reset
Value
0x08F MPIOINT MPIO Interrupt Mask R/W 0x00
0x090 MPIOLVL MPIO Level Control R/W 0x00
0x091 MPIO3T MPIO Output Pin Tri-state Control R/W 0x00
0x092 MPIOINV MPIO Input Polarity Select R/W 0x00
0x093 MPIOSEL MPIO Input/Output Select R/W 0xFF
Table 5-4 : MPIO Device Configuration Registers
MPIOINT, MPIOLVL and MPIO3T must be left at their default values. MPIOSEL must be set to 0x80 to
configure MPIO[6-0] pins as outputs and MPIO[7] as input. MPIOLVL sets the output level of the MPIO
output pins and is used to write on the CPLD-bus.
5.2.2 CPLD-Bus Protocol
5.2.2.1 Write
A CPLD register write access starts with setting CEN to ‘1’. This resets the CPLD’s internal state-
machine. Before the first clock pulse is issued, ADR and DATAOUT have to be set; R/W# must be left
‘0’. The first rising edge of CLK samples the ADR bits and the DATAOUT bit. ADR determines which
internal register is accessed. The following 6 rising edges of CLK sample the remaining data bits,
additional CLK pulses are ignored. Setting CEN back to ‘0’ completes the access and the
configuration of the transceivers will be updated.
CLK
DATAOUT
ADR
CEN
Address
Bit5 Bit4 Bit3 Bit2 Bit1
Bit6
Sample address & first data bit
Reset internal state machine Write to outputs
R/W
DATAIN
Bit0
Figure 5-2 : CPLD-Bus Write
Example (pseudocode):
Write value 0x05 to CPLD address 0x03
define MPIOLVL 0x90;
define MPIOSEL 0x93;
void Write_XR17D154(int address, int value);
TPMC467 User Manual Issue 1.0.4 Page 19 of 30

Write_XR17D154(MPIOSEL, 0x80); // Setting up MPIOSEL
Write_XR17D154(MPIOLVL, 0x19); // CEN = ‘1’, ADR = "011”, D(6) = ‘0’
Write_XR17D154(MPIOLVL, 0x1D); // CLK = ‘1’
Write_XR17D154(MPIOLVL, 0x01); // CLK = ‘0’, ADR = “000”, D(5) = ‘0’
Write_XR17D154(MPIOLVL, 0x05); // CLK = ‘1’
Write_XR17D154(MPIOLVL, 0x01); // CLK = ‘0’, D(4) = ‘0’
Write_XR17D154(MPIOLVL, 0x05); // CLK = ‘1’
Write_XR17D154(MPIOLVL, 0x01); // CLK = ‘0’, D(3) = ‘0’
Write_XR17D154(MPIOLVL, 0x05); // CLK = ‘1’
Write_XR17D154(MPIOLVL, 0x41); // CLK = ‘0’, D(2) = ‘1’
Write_XR17D154(MPIOLVL, 0x45); // CLK = ‘1’
Write_XR17D154(MPIOLVL, 0x01); // CLK = ‘0’, D(1) = ‘0’
Write_XR17D154(MPIOLVL, 0x05); // CLK = ‘1’
Write_XR17D154(MPIOLVL, 0x41); // CLK = ‘0’, D(0) = ‘1’
Write_XR17D154(MPIOLVL, 0x45); // CLK = ‘1’
Write_XR17D154(MPIOLVL, 0x00); // CLK = ‘0’, CEN = ‘0’
5.2.2.2 Read
A CPLD register read access starts with setting CEN to ‘1’. This resets the CPLD’s internal state-
machine. Before the first clock pulse is issued, ADR and R/W# have to be set. The first rising edge of
CLK samples the ADR bits and starts the output of the first DATAIN bit. ADR determines which
internal register is accessed. The following 6 rising edges of CLK put out the remaining data bits,
additional CLK pulses are ignored. Setting CEN back to ‘0’ completes the access.
CLK
DATAOUT
ADR
CEN
Address
Sample address &output of first data bit
Reset internal state machine
R/W
DATAIN Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Bit6
Figure 5-3 : CPLD-Bus Read
Example (pseudocode):
Read value 0x05 to CPLD address 0x03
define MPIOLVL 0x90;
define MPIOSEL 0x93;
int Read_XR17D154(int address); // Returns the address’ bit 7
int value
Write_XR17D154(MPIOSEL, 0x80); // Setting up MPIOSEL
Write_XR17D154(MPIOLVL, 0x1B); // CEN = ‘1’, ADR = "011”, R/W# = ‘1’
Write_XR17D154(MPIOLVL, 0x1F); // CLK = ‘1’
Write_XR17D154(MPIOLVL, 0x03); // CLK = ‘0’, ADR = “000”
TPMC467 User Manual Issue 1.0.4 Page 20 of 30