Tews Technologies TPCE636 User manual

The Embedded
I/O Company
TPCE636
Reconfigurable FPGA with 16x 16bit Analog Input
and 16x 16bit Analog Output
Version 1.0
User Manual
Issue 1.0.2
January 2019
TEWS TECHNOLOGIES GmbH
Am Bahnhof 7 25469 Halstenbek, Germany
Phone: [phone] Fax: [phone]
e-mail: [email protected] www.tews.com

TPCE636 User Manual Issue 1.0.2 Page 2 of 104
TPCE636-10R
16x Analog In, 16x Analog Out and 64 direct
FPGA Back I/O Lines,
XC7K160T-2 FBG676 Kintex-7 FPGA, 1GB
DDR3
TPCE636-11R
16x Analog In, 16x Analog Out and 64 direct
FPGA Back I/O Lines,
XC7K325T-2 FBG676 Kintex-7 FPGA, 1GB
DDR3
TPCE636-12R
24x Analog In and 64 direct FPGA Back I/O
Lines,
XC7K410T-2 FBG676 Kintex-7 FPGA, 1GB
DDR3
This document contains information, which is
proprietary to TEWS TECHNOLOGIES GmbH. Any
reproduction without written permission is forbidden.
TEWS TECHNOLOGIES GmbH has made any
effort to ensure that this manual is accurate and
complete. However TEWS TECHNOLOGIES GmbH
reserves the right to change the product described
in this document at any time without notice.
TEWS TECHNOLOGIES GmbH is not liable for any
damage arising out of the application or use of the
device described herein.
Style Conventions
Hexadecimal characters are specified with prefix 0x,
i.e. 0x029E (that means hexadecimal value 029E).
For signals on hardware products, an ‚Active Low’ is
represented by the signal name with # following, i.e.
IP_RESET#.
Access terms are described as:
W Write Only
R Read Only
R/W Read/Write
R/C Read/Clear
R/S Read/Set
2018 by TEWS TECHNOLOGIES GmbH
All trademarks mentioned are property of their respective owners.

TPCE636 User Manual Issue 1.0.2 Page 3 of 104
Issue Description Date
1.0.0 First Issue July 2018
1.0.1 Chapter On-Board Indicators added to the manual.
Correction and extension of the JTAG chain description. August 2018
1.0.2 Correction of the Electrical Interface specification in the
Technical Specification table. January 2019

TPCE636 User Manual Issue 1.0.2 Page 4 of 104
Table of Contents
1 PRODUCT DESCRIPTION ...........................................................................................9
2 TECHNICAL SPECIFICATION ...................................................................................10
3 HANDLING AND OPERATION INSTRUCTION .........................................................12
ESD Protection..............................................................................................................................123.1 Thermal Considerations...............................................................................................................123.2
4 PCI DEVICE TOPOLOGY...........................................................................................13
User FPGA (Kintex-7)....................................................................................................................144.1 BCC (Board Configuration Controller) FPGA ............................................................................144.2
4.2.1 PCI Configuration Registers (PCR)........................................................................................14
4.2.2 PCI BAR Overview..................................................................................................................14
4.2.2.1 Local Configuration Register Space..................................................................................15
4.2.2.2 In-System Programming Data Space................................................................................16
5 REGISTER DESCRIPTION.........................................................................................17
User FPGA (Kintex-7)....................................................................................................................175.1 BCC (Board Configuration Controller) FPGA ............................................................................185.2
5.2.1 DAC Control / Status Register – 0x00....................................................................................18
5.2.2 DAC Output Voltage Range Register – 0x04 .........................................................................19
5.2.3 Reference DAC Voltage Control Register – 0x10 to 0x4C.....................................................20
5.2.1 User FPGA JTAG Control and Status Register – 0x80..........................................................22
5.2.2 User FPGA JTAG Signal Line Register – 0x84......................................................................23
5.2.3 User FPGA JTAG TMS Data Register - 0x88 ........................................................................24
5.2.4 User FPGA JTAG TDI Data Register - 0x8C..........................................................................24
5.2.5 User FPGA JTAG TDO Data Register - 0x90 ........................................................................25
5.2.6 I2C Bridge Register - 0xA0.....................................................................................................25
5.2.7 Interrupt Enable Register - 0xC0............................................................................................25
5.2.8 Interrupt Status Register - 0xC4.............................................................................................26
5.2.9 User FPGA Configuration Control/Status Register - 0xD0.....................................................26
5.2.10 User FPGA Configuration Data Register - 0xD4 ....................................................................27
5.2.11 ISP Control Register - 0xE0....................................................................................................27
5.2.12 ISP Configuration Register - 0xE4..........................................................................................28
5.2.13 ISP Command Register - 0xE8...............................................................................................28
5.2.14 ISP Status Register - 0xEC ....................................................................................................29
5.2.15 TPCE636 Temperature Sensor Register - 0xF4 ....................................................................30
5.2.16 TPCE636 Serial Number - 0xF8.............................................................................................30
5.2.17 BCC - FPGA Code Version - 0xFC.........................................................................................31
6 INTERRUPTS..............................................................................................................32
Interrupt Sources ..........................................................................................................................326.1
6.1.1 User FPGA (Kintex-7).............................................................................................................32
6.1.2 BCC (Board Configuration Controller) FPGA .........................................................................32
Interrupt Handling.........................................................................................................................326.2
6.2.1 User FPGA (Kintex-7).............................................................................................................32
6.2.2 BCC (Board Configuration Controller) FPGA .........................................................................32
7 FUNCTIONAL DESCRIPTION....................................................................................33
User FPGA Block Diagram...........................................................................................................337.1 User FPGA Highlights ..................................................................................................................347.2 User FPGA Gigabit Transceiver (MGT).......................................................................................357.3 User FPGA Configuration ............................................................................................................377.4

TPCE636 User Manual Issue 1.0.2 Page 5 of 104
7.4.1 Master Serial SPI Flash Configuration....................................................................................37
7.4.2 Manually User FPGA SPI Flash Reconfiguration...................................................................38
7.4.3 Slave Select Map Configuration .............................................................................................39
7.4.4 Configuration via JTAG...........................................................................................................41
7.4.4.1 User JTAG Chain...............................................................................................................41
7.4.4.2 TEWS Factory JTAG Chain...............................................................................................41
7.4.5 Programming User FPGA SPI Configuration Flash................................................................42
7.4.6 Erasing User FPGA SPI Configuration Flash.........................................................................43
7.4.7 Sector Erasing User FPGA SPI Configuration Flash..............................................................44
7.4.8 Reading User FPGA SPI Configuration Flash........................................................................45
BCC (Board Configuration Controller) FPGA ............................................................................467.5
7.5.1 I2C Interface to BCC Register................................................................................................46
Clocking.........................................................................................................................................477.6
7.6.1 FPGA Clock Sources..............................................................................................................47
7.6.2 Si514 Free Programming Clock source..................................................................................49
Back I/O Interface..........................................................................................................................507.7 Memory ..........................................................................................................................................527.8
7.8.1 DDR3 SDRAM........................................................................................................................52
7.8.2 SPI-Flash................................................................................................................................55
7.8.3 I2C - EEPROM........................................................................................................................55
7.8.3.1 I2C Calibration Data ..........................................................................................................56
7.8.3.2 ADC and DAC Calibration Data Values.............................................................................56
7.8.3.3 DAC Calibration Data Values ............................................................................................57
7.8.3.4 ADC Data Correction Formula...........................................................................................58
7.8.3.5 DAC Data Correction Formula...........................................................................................58
Serial ADC Interface......................................................................................................................597.9
7.9.1 Overview.................................................................................................................................59
7.9.2 ADC digital Output Coding......................................................................................................60
7.9.3 User FPGA Pinning.................................................................................................................61
7.9.4 Programming Hints LTC2323-16............................................................................................64
Parallel DAC Interface ..................................................................................................................657.10
7.10.1 Overview.................................................................................................................................65
7.10.2 User FPGA Pinning.................................................................................................................66
7.10.3 Programming Hints for AD5547..............................................................................................68
7.10.4 Output Voltage Range ............................................................................................................69
Digital Interface to FireFly Connector.........................................................................................707.11 JTAG Controller to K7 JTAG Interface .......................................................................................717.12
7.12.1 Bit-IO.......................................................................................................................................71
7.12.2 Vector-IO.................................................................................................................................71
I2C Bridge ......................................................................................................................................727.13 On-Board Indicators .....................................................................................................................737.14
7.14.1 User FPGA Pinning.................................................................................................................74
User FPGA Reset Inputs ..............................................................................................................747.15
8 DESIGN HELP ............................................................................................................75
Board Reference Design ..............................................................................................................758.1
9 I/O INTERFACES........................................................................................................76
9.1.1 Front I/O - ADC Analog Input Level........................................................................................76
9.1.2 Front I/O – Analog Output Level.............................................................................................77
9.1.3 Back I/O Interface...................................................................................................................77
10 I/O DESCRIPTION ......................................................................................................78
Overview ........................................................................................................................................7810.1 Front I/O Connector (X1) ..............................................................................................................7910.2

TPCE636 User Manual Issue 1.0.2 Page 6 of 104
10.2.1 Connector Type ......................................................................................................................79
10.2.2 Pin Assignment.......................................................................................................................79
Digital Back I/O Connector (X7)...................................................................................................8110.3
10.3.1 Connector Type ......................................................................................................................81
10.3.2 Pin Assignment.......................................................................................................................81
MGT Back I/O Connector (X8/X9) ................................................................................................8310.4
10.4.1 Connector Type ......................................................................................................................83
10.4.2 Pin Assignment.......................................................................................................................83
10.4.3 Connector Type ......................................................................................................................84
10.4.4 Pin Assignment.......................................................................................................................84
FPGA JTAG Header (X5) ..............................................................................................................8510.5
10.5.1 Connector Type ......................................................................................................................85
10.5.2 Pin Assignment.......................................................................................................................85
FPGA USB Connector (X2)...........................................................................................................8610.6
10.6.1 Connector Type ......................................................................................................................86
10.6.2 Pin Assignment.......................................................................................................................86
11 APPENDIX A...............................................................................................................87
List of Figures
FIGURE 1-1 : BLOCK DIAGRAM......................................................................................................................9
FIGURE 4-1 : PCIE/PCI DEVICE TOPOLOGY...............................................................................................13
FIGURE 5-1 : DAC AND REF. DAC SCHEMATA...........................................................................................20
FIGURE 5-2 : DAC OUTPUT CHANNEL........................................................................................................20
FIGURE 7-1 : FPGA BLOCK DIAGRAM.........................................................................................................33
FIGURE 7-2 : MGT BLOCK DIAGRAM...........................................................................................................35
FIGURE 7-3 : USER JTAG-CHAIN................................................................................................................41
FIGURE 7-4 : TEWS FACTORY JTAG-CHAIN ..............................................................................................41
FIGURE 7-5 : FPGA CLOCK SOURCES.......................................................................................................47
FIGURE 7-6 : ANALOG INPUT SECTION.....................................................................................................59
FIGURE 7-7 : ANALOG INPUT BLOCK DIAGRAM.......................................................................................59
FIGURE 7-8 : DIGITAL ADC TO FPGA INTERFACE....................................................................................64
FIGURE 7-9 : TIMING DIAGRAM LTC2323-16.............................................................................................64
FIGURE 7-10 : ANALOG OUTPUT SECTION................................................................................................65
FIGURE 7-11 : ANALOG OUTPUT SECTION................................................................................................65
FIGURE 7-12 : USER FPGA I2C TO BCC I2C BRIDGE................................................................................72
FIGURE 9-1 : DAC OUTPUT INTERFACE....................................................................................................77
FIGURE 10-1 : PIN ASSIGNMENT BACK I/O CONNECTOR TPCE636.......................................................82
FIGURE 10-2 : FIREFLY BACK I/O CONNECTOR TPCE636.......................................................................83
FIGURE 10-3 : PIN ASSIGNMENT FIREFLY BACK I/O CONNECTOR TPCE636.......................................83
FIGURE 10-4 : FIREFLY BACK I/O CONNECTOR TPCE636.......................................................................84
FIGURE 10-5 : PIN ASSIGNMENT FIREFLY BACK I/O CONNECTOR TPCE636.......................................84
FIGURE 10-6 JTAG HEADER TPCE636.........................................................................................................85
FIGURE 10-7 FPGA USB CONNECTOR TPCE636 .......................................................................................86

TPCE636 User Manual Issue 1.0.2 Page 7 of 104
List of Tables
TABLE 2-1 : TECHNICAL SPECIFICATION...................................................................................................11
TABLE 4-1 : ON-BOARD PCIE / PCI DEVICES............................................................................................13
TABLE 4-2 : PCI CONFIGURATION REGISTERS.........................................................................................14
TABLE 4-3 : PCI BAR OVERVIEW.................................................................................................................14
TABLE 4-4 : LOCAL CONFIGURATION REGISTER SPACE.......................................................................16
TABLE 4-5 : REGISTER BIT ACCESS TYPES..............................................................................................16
TABLE 5-1 : DAC CONTROL AND STATUS REGISTER..............................................................................18
TABLE 5-2 : DAC OUTPUT VOLTAGE RANGE REGISTER.........................................................................19
TABLE 5-3 : REFERENCE DAC VOLTAGE CONTROL REGISTER.............................................................20
TABLE 5-4 : VOLTAGE CODING FOR THE REFERENCE DAC...................................................................21
TABLE 5-5 : USER FPGA JTAG CONTROL AND STATUS REGISTER.......................................................22
TABLE 5-6 : USER FPGA JTAG SIGNAL LINE REGISTER..........................................................................24
TABLE 5-7 : USER FPGA JTAG TMS DATA REGISTER..............................................................................24
TABLE 5-8 : USER FPGA JTAG TDI DATA REGISTER................................................................................24
TABLE 5-9 : USER FPGA JTAG TDO DATA REGISTER..............................................................................25
TABLE 5-10 : I2C BRIDGE REGISTER..........................................................................................................25
TABLE 5-11 : INTERRUPT ENABLE REGISTER .........................................................................................25
TABLE 5-12 : INTERRUPT STATUS REGISTER .........................................................................................26
TABLE 5-13 : USER FPGA CONFIGURATION CONTROL/STATUS REGISTER.......................................26
TABLE 5-14 : USER FPGA CONFIGURATION DATA REGISTER................................................................27
TABLE 5-15 : ISP CONTROL REGISTER......................................................................................................27
TABLE 5-16 : ISP CONFIGURATION REGISTER .........................................................................................28
TABLE 5-17 : ISP COMMAND REGISTER.....................................................................................................28
TABLE 5-18 : ISP STATUS REGISTER .........................................................................................................29
TABLE 5-19 : TPCE636 TEMPERATURE SENSOR REGISTER..................................................................30
TABLE 5-20 : TPCE636 SERIAL NUMBER....................................................................................................30
TABLE 5-21: BCC - FPGA CODE VERSION..................................................................................................31
TABLE 7-1 : TPCE636 FPGA FEATURE OVERVIEW...................................................................................34
TABLE 7-2 : FPGA BANK USAGE.................................................................................................................34
TABLE 7-3 : MGT CONNECTIONS................................................................................................................35
TABLE 7-4 : MULTI GIGABIT TRANSCEIVER REFERENCE CLOCKS ......................................................36
TABLE 7-5: USER FPGA I2C INTERFACE TO BCC .....................................................................................46
TABLE 7-6 : AVAILABLE FPGA CLOCKS.....................................................................................................48
TABLE 7-7 : FPGA I2C SI514 CONNECTIONS ............................................................................................49
TABLE 7-8 : DIGITAL BACK I/O INTERFACE...............................................................................................51
TABLE 7-9 : DDR3 SDRAM INTERFACE......................................................................................................53
TABLE 7-10 : FPGA SPI-FLASH CONNECTIONS........................................................................................55
TABLE 7-11: FPGA I2C EEPROM CONNECTIONS.....................................................................................55
TABLE 7-12: ADC CALIBRATION DATA VALUES ........................................................................................56
TABLE 7-13: DAC CALIBRATION DATA VALUES ........................................................................................57
TABLE 7-14: ADC DATA CODING EXAMPLE...............................................................................................60

TPCE636 User Manual Issue 1.0.2 Page 8 of 104
TABLE 7-15: ADC DATA CODING .................................................................................................................60
TABLE 7-16: ADC INTERFACE CONNECTIONS.........................................................................................63
TABLE 7-17: TPCE636 PARALLEL DAC INTERFACE.................................................................................67
TABLE 7-18 : FIREFLY BACK I/O INTERFACE............................................................................................70
TABLE 7-19: BOARD-STATUS AND USER LEDS ........................................................................................73
TABLE 7-20: TPCE636 USER ON-BOARD INDICATORS ...........................................................................74
TABLE 7-21: USER FPGA RESET INPUTS..................................................................................................74
TABLE 9-1 : DIFFERENTIAL INPUT VOLTAGE RANGES............................................................................76
TABLE 9-2 : DAC ELECTRICAL INTERFACE................................................................................................77
TABLE 10-1 : FRONT I/O CONNECTOR .......................................................................................................79
TABLE 10-2: PIN ASSIGNMENT FRONT PANEL I/O CONNECTOR............................................................80
TABLE 10-3 : BACK I/O CONNECTOR..........................................................................................................81
TABLE 10-4: PIN ASSIGNMENT JTAG HEADER...........................................................................................85
TABLE 10-5: PIN ASSIGNMENT USB TYPE C CONNECTOR.....................................................................86

TPCE636 User Manual Issue 1.0.2 Page 9 of 104
1 Product Description
The TPCE636 is a half-length x4 PCIe compatible module providing a user configurable Kintex-7 FPGA with
16 ADC input channels and 16 DAC output channels.
The TPCE636 ADC input channels are based on the Linear Dual 16bit 5Msps Differential LTC2323-16 ADC.
The TPCE636 provides 16 ADC channels. Each of the 16 channels has a resolution of 16bit and can work
with up to 5Msps. The analog input circuit is designed to allow input voltages of up to ±10V on each input-pin
(results in ±20V differential voltage range)
The TPCE636 DAC output channels are based on the Dual 16bit AD5547 DAC. Each DAC output is
designed as a single-ended bipolar ±10V analog output.
For customer specific I/O extension or inter-board communication, the TPCE636 provides 64 FPGA I/Os on
a back I/O connector and 4 FPGA Multi-Gigabit-Transceivers on a Samtec Firefly connector. Digital back I/O
lines can be configured as 64 single-ended LVCMOS25 lines or as 32 differential LVDS25 lines.
The User FPGA is connected to a 1GB, 32bit wide DDR3 SDRAM. The SDRAM-interface uses an internal
Memory Controller of the Kintex-7.
The User FPGA is configured by a serial SPI flash. For full PCIe specification compliance, the XILINX
Tandem Configuration Feature can be used for FPGA configuration. XILINX Tandem Methodologies
“Tandem PROM” should be the preferred methodology. The SPI flash device is in-system programmable.
An in-circuit debugging option is available via a JTAG header for read back and real-time debugging of the
FPGA design (using Xilinx “ChipScope”).
User applications for the TPCE636 with Kintex-7 FPGA can be developed using the design software Vivado
Design Suite. A license for the Vivado Design Suite design tool is required.
Kintex-7
XC7K160T, XC7K325T ,
or
XC7K410T
(FBG676)
Debug
and
JTAG Header
Clock-
Generator
64 x
FPGA-I/O
4 x MGT
PCIe
Switch
x32
SPI
PROM
Power Supply
ERF8 Connector
PCIe x4
BCC
PCIe x4
DDR3
1GB
16ADC Channel
16Bit
5MSps
with
Signal Conditioning
16 DAC Channel
16Bit
Settling <2us
Figure 1-1 : Block Diagram

TPCE636 User Manual Issue 1.0.2 Page 10 of 104
2 Technical Specification
PCIe Interface
Mechanical Interface Peripheral Component Interconnect Express (PCIe)
PCI Express CEM R3.0
Standard Height, shortened Half Length PCI Express Add-in Card
(98.4mm x 153.50mm)
Electrical Interface PCI Express x4 Link (Base Specification 2.1) compliant interface
conforming to ANSI/VITA 42.3-2006 (PCI Express Protocol Layer
Standard)
On-Board Devices
PCI Express Switch PI7C9X2G312GP (Pericom)
PCI Express to PCI Bridge XIO2001 (Texas Instruments)
User configurable FPGA TPCE636-10R: XC7K160T-2FBG676I (Xilinx)
TPCE636-11R: XC7K325T-2FBG676I (Xilinx)
TPCE636-12R: XC7K410T-2FBG676I (Xilinx)
SPI-Flash MT25QL128 (Micron) 128Mbit (contains TPCE636 FPGA BRD) or
compatible; +3.3V supply voltage
DDR3 RAM 2 x MT41K256M16TW-107 (Micron) 256Meg x 32Bit
Board Configuration
Controller LCMXO2-7000HC (Lattice)
ADC LTC2323IUFD-16 (Linear Technologies)
DAC AD5547BRUZ (Analog Devices)
I/O Interface
Number of analog Input 16 differential 16bit Inputs
Analog Input Voltage diff. VINMAX (allowed voltage between input pins):
Common Mode Voltage Range:
Input Voltage limit for each pin relative to common ground:
±20.0V
0.0V
±10V
Number of analog Outputs 16 single-ended 16bit Outputs
Analog Output Voltage Maximum single-ended Output Voltage – Vout
Maximum Output Drive Current for each Output
Maximum Capacitive Load for each Output
Typical Settling Time for a 10mA / 1000pF
±10V
10mA
1000pF
< 1µs
Number of digital Back I/O 64 direct FPGA I/O lines to P14 Back I/O connector
- Can be used as single-ended or differential I/O
- FPGA I/O Standard: LVCMOS25, LVTTL25 and LVDS25
I/O Connector Front I/O Samtec – ERF8-049-01-L-D-RA-L
Back I/O Connector male SMC-B 68 (ERNI 154766 64)
High Speed Back I/O Connector (Samtec FireFly™)
Physical Data
Power Requirements Depends on FPGA design
With TPCE636 Board Reference Design / without external load
typical @ +12V PCIe typical @ +3.3V PCIe
TPCE636-xxR 1.3 A not used by TPCE636

TPCE636 User Manual Issue 1.0.2 Page 11 of 104
Temperature Range Operating
Storage -40°C to +85°C -40°C to +85°C
MTBF TPCE636-xxR: 240000 h
MTBF values shown are based on calculation according to MIL-HDBK-217F and
MIL-HDBK-217F Notice 2; Environment: GB20°C.
The MTBF calculation is based on component FIT rates provided by the component
suppliers. If FIT rates are not available, MIL-HDBK-217F and MIL-HDBK-217F Notice 2
formulas are used for FIT rate calculation.
Humidity 5 – 95 % non-condensing
Weight TPCE636-xxR: 208g
Table 2-1 : Technical Specification

TPCE636 User Manual Issue 1.0.2 Page 12 of 104
3 Handling and Operation Instruction
ESD Protection3.1
The TPCE636 is sensitive to static electricity. Packing, unpacking
and all other handling of the TPCE636 has to be done in an ESD/EOS
protected Area.
Thermal Considerations3.2
Forced air cooling is recommended during operation. Without forced
air cooling, damage to the device can occur.
Please also note chapter “Thermal Management”.

TPCE636 User Manual Issue 1.0.2 Page 13 of 104
4 PCI Device Topology
The TPCE636 consists of two FPGAs. Both FPGAs are designed as PCIe / PCI endpoint devices. One
FPGA is the User FPGA (Kintex-7) which can be programmed with user defined FPGA code. The second
FPGA takes control of on-board hardware functions of TPCE636 and also the configuration control of the
User FPGA. This second FPGA is the BCC (Board Configuration Controller).
The BCC PCI endpoint is connected via a PCI-to-PCIe Bridge to the second x1 Downstream Port of the
PCIe Switch (Pericom PI7C9X2G312GP). The User FPGA (Kintex-7 PCIe endpoint) is directly connected to
the first x4 Downstream Port.
The x4 Upstream Port of the PCIe Switch is connected to the XMC P15 Connector, communicating with the
host system.
P15
XC7KxxxT-2 PCIe-to-PCI Bridge
x4 PCIe
x1PCIex4PCIe
PI7C9X2G312GP
XIO2001
LCMXO2
User FPGA
Board Configuration
Controller (FPGA)
Figure 4-1 : PCIe/PCI Device Topology
Device Vendor ID Device ID Class
Code Description (as shown by lspci)
PI7C9X2G312GP 0x12D8
(Pericom) 0x2312 0x060400 PCI bridge: 0x04h to indicate device as PCI-to-PCI Bridge
0x06h to indicate device as Bridge device
XIO2001 0x104C (Texas
Instruments)
0x8240 0x060400 PCI bridge: Texas Instruments
0x04h to indicate device as PCI-to-PCI Bridge
0x06h to indicate device as Bridge device
XC7KxxxT-2
user defined Device identification for the User
programmable FPGA is defined by user. The
data will be created with the Xilinx Vivado “7
Series Integrated Block for PCI Express” IP
generator.
BCC
LCMXO2
0x1498
(TEWS) 0x727c 0x068000 Bridge Device: TEWS Technologies GmbH
Device 927E
(TPCE636).
Table 4-1 : On-Board PCIe / PCI Devices

TPCE636 User Manual Issue 1.0.2 Page 14 of 104
User FPGA (Kintex-7)4.1
The User FPGA address map depends on the user application and is not part of this specification.
BCC (Board Configuration Controller) FPGA4.2
4.2.1 PCI Configuration Registers (PCR)
PCI CFG
Register
Address
Write ‘0’ to all unused (Reserved) bits PCI
writeable Initial Values (Hex Values)
31 24 23 16 15 8 7 0
0x00 Device ID Vendor ID N 727C 1498
0x04 Status Command Y 0480 000B
0x08 Class Code Revision ID N 068000 01
0x0C BIST Header Type PCI Latency
Timer Cache Line Size Y[7:0] 00 00 00 08
0x10 PCI Base Address 0 for Local Address Space 0 Y FFFFFF00
0x14 PCI Base Address 1 for Local Address Space 1 Y FFFFFF00
0x18 PCI Base Address 2 for Local Address Space 2 N 00000000
0x1C PCI Base Address 3 for Local Address Space 3 N 00000000
0x20 PCI Base Address 4 for Local Address Space 4 N 00000000
0x24 PCI Base Address 5 for Local Address Space 5 N 00000000
0x28 PCI CardBus Information Structure Pointer N 00000000
0x2C Subsystem ID Subsystem Vendor ID N 727C 1498
0x30 PCI Base Address for Local Expansion ROM Y 00000000
0x34 Reserved New Cap. Ptr. N 000000 40
0x38 Reserved N 00000000
0x3C Max_Lat Min_Gnt Interrupt Pin Interrupt Line Y[7:0] 00 00 01 00
Table 4-2 : PCI Configuration Registers
4.2.2 PCI BAR Overview
BAR Size
(Byte) Space Prefetch Port
Width
(Bit)
Endian
Mode Description
0 256 MEM No 32 Little Local Configuration Register Space
1 256 MEM No 32 Little In-System Programming Data Space
Table 4-3 : PCI BAR Overview

TPCE636 User Manual Issue 1.0.2 Page 15 of 104
4.2.2.1 Local Configuration Register Space
Offset to PCI
Base Address Register Name Size (Bit)
0x00 DAC Control and Status Register 32
0x04 DAC Output Voltage Range Register 32
0x08 – 0x0C Reserved -
0x10 Register for VOFF and VREF of DAC Channel 1 32
0x14 Register for VOFF and VREF of DAC Channel 2 32
0x18 Register for VOFF and VREF of DAC Channel 3 32
0x1C Register for VOFF and VREF of DAC Channel 4 32
0x20 Register for VOFF and VREF of DAC Channel 5 32
0x24 Register for VOFF and VREF of DAC Channel 6 32
0x28 Register for VOFF and VREF of DAC Channel 7 32
0x2C Register for VOFF and VREF of DAC Channel 8 32
0x30 Register for VOFF and VREF of DAC Channel 9 32
0x34 Register for VOFF and VREF of DAC Channel 10 32
0x38 Register for VOFF and VREF of DAC Channel 11 32
0x3C Register for VOFF and VREF of DAC Channel 12 32
0x40 Register for VOFF and VREF of DAC Channel 13 32
0x44 Register for VOFF and VREF of DAC Channel 14 32
0x48 Register for VOFF and VREF of DAC Channel 15 32
0x4C Register for VOFF and VREF of DAC Channel 16 32
0x50 – 0x7F Reserved -
0x80 Kintex-7 JTAG Control Register 32
0x84 Kintex-7 JTAG Interface Register 32
0x88 Kintex-7 JTAG Signal TMS Data Register 32
0x8C Kintex-7 JTAG Signal TDI Data Register 32
0x90 Kintex-7 JTAG Signal TDO Data Register 32
0x94 – 0x9F Reserved -
0xA0 I2C Bridge Register 32
0xA4 – 0xBF Reserved -
0xC0 Interrupt Enable Register 32
0xC4 Interrupt Status Register 32
0xC8 Reserved -
0xCC Reserved -
0xD0 User FPGA Configuration Control/Status Register 32
0xD4 User FPGA Configuration Data Register (Slave SelectMAP) 32
0xD8 Reserved -
0xDC Reserved -
0xE0 ISP Control Register (SPI) 32

TPCE636 User Manual Issue 1.0.2 Page 16 of 104
0xE4 ISP Configuration Register (SPI) 32
0xE8 ISP Command Register (SPI) 32
0xEC ISP Status Register (SPI) 32
0xF0 Reserved -
0xF4 TPCE636 Board Temperature 32
0xF8 TPCE636 Serial Number 32
0xFC BCC Code Version 32
Table 4-4 : Local Configuration Register Space
Register Bit
Access Type Description
R Read The bit is readable by software.
R/W Read/Write The bit is readable and writeable by software.
R/C Read/Clear The bit is readable by software.
The bit is set by firmware. Software may clear the bit by writing a ‘1’.
R/S Read/Set The bit is readable by software.
Software may set this bit to ‘1’. The bit is cleared by firmware.
Table 4-5 : Register Bit Access Types
When reading reserved register bits, the value is undefined.
Reserved register bits shall be written as '0'.
4.2.2.2 In-System Programming Data Space
The In-System Programming (ISP) Data Space is used for passing user FPGA configuration data for in-
system programming of the User FPGA SPI Flash.
For ISP write/program instructions, the data must be written (zero-based) to the ISP Data Space before the
instruction is started. The data must cover a complete SPI Flash memory page.
For ISP read instructions, the data can be read (zero-based) from the ISP Data Space after the instruction is
done. The data is passed for a complete SPI Flash memory page.
The ISP Data Space size is 256byte, covering an SPI Flash Memory Page. All supported SPI Flash read and
write instructions are page-based.
Control and status register for ISP are located in the Local Configuration Register Space. The data register
for direct FPGA ISP is also located in the Local Configuration Register Space.

TPCE636 User Manual Issue 1.0.2 Page 17 of 104
5 Register Description
User FPGA (Kintex-7)5.1
The FPGA register description depends on the user application and is not part of this specification.

TPCE636 User Manual Issue 1.0.2 Page 18 of 104
BCC (Board Configuration Controller) FPGA5.2
5.2.1 DAC Control / Status Register – 0x00
The output voltage ranges of the TPCE636 DAC outputs are set via DAC Control / Status Register and DAC
Output Voltage Range Register.
For the three predefined ranges (±10V, ±5V and ±2.5V), the DAC Output Voltage Range Register is set first
and then the values are transferred via the DAC Control / Status Register.
For the individual range selection the Reference DAC Voltage Control Register must also be set before
updating the data via DAC Control / Status Register.
Bit Symbol Description Access Reset
Value
31:16 - Reserved R 0
15:14 - Reserved R 0
13 DAC2_OUTP_UPD
Bits correspond to DAC #1
Refer description for DAC #1
12 DAC2_CLR
11 DAC2_OVRTMP
10 -
9 DAC2_OUTPSTTLE
8 DAC2_IOBSY
7:6 - Reserved R 0
5 DAC1_OUTP_UPD
DAC #1 Output Update
Initiate DAC Device Output Update with currently
adjusted output values
Self-Clearing
R/S 0
4 DAC1_CLR
DAC #1 Clear
Causes DAC to be cleared. Includes setup with
current adjusted values
Self-Clearing
R/S 0
3 DAC1_OVRTMP DAC #1 Over Temperature
Status is provided by DAC device R 0
2 - Reserved
1 DAC1_OUTPSTTLE DAC #1 Output Settle
Internal generated settling pulse (set to 20.5us) R 0
0 DAC1_IOBSY
DAC #1 I/O Busy
Indicates that
Controller is not in idle
Span-Configuration update is pending
Output Value update is pending
Internal synchronization is pending
R 0
Table 5-1 : DAC Control and Status Register

TPCE636 User Manual Issue 1.0.2 Page 19 of 104
5.2.2 DAC Output Voltage Range Register – 0x04
Bit Symbol Description Access Reset
Value
31:30 REF_DAC16
DAC Output Voltage range selection for DAC channel 16
00 : ±10V range (default value)
01 : ±5V range
10 : ±2.5V range
11 : individual range selection
R/W 0b00
… - … … …
1:0 REF_DAC1
DAC Output Voltage range selection for DAC channel 1
00 : ±10V range (default value)
01 : ±5V range
10 : ±2.5V range
11 : individual range selection
R/W 0b00
Table 5-2 : DAC Output Voltage Range Register
For individual voltage range selection also see the chapter 5.2.3Reference DAC Voltage Control Register.

TPCE636 User Manual Issue 1.0.2 Page 20 of 104
5.2.3 Reference DAC Voltage Control Register – 0x10 to 0x4C
The 16 TPCE636 DAC outputs consist of eight dual DAC devices (AD5547). Each of these DACs could be
used independently.
For the generation of the reference voltage of these 16 TPCE636 DACs, two additional serial DAC devices
are placed on the TPCE636. Each of this Reference DAC has 16 analog outputs. Thus 32 reference
voltages are available. Two reference voltages for each TPCE636 DAC output.
Via these reference voltages (VREF and VOFF), an individual voltage range can be set for each TPCE636
DAC channel. Both reference voltages are each set as 16 bit value via a 32bit register of the BCC. This
results in 16 32bit registers via which the reference voltage and thus the output voltage range of the
TPCE636 can be set.
Ref. DAC
LTC2668
Channel 1
DAC -AD5547
Channel 2
Ref. DAC
LTC2668
VREF
VREF
VOFF
VOFF
Op.Amp.
Op.Amp.
Front I/O
Figure 5-1 : DAC and Ref. DAC Schemata
One 32bit Register for each of the 16 TPCE636 DAC outputs.
Bit Symbol Description Access Reset
Value
31:16 VREF 16-bit Data Value for VREF which specifies the half
voltage swing of the reference voltage for the AD5547
DAC channel. R/W 0x8000
15:0 VOFF 16-bit Data Value for VOFF which represents the
negative reference voltage of the AD5547 DAC
channel. R/W 0x8000
Table 5-3 : Reference DAC Voltage Control Register
Each TPCE636 analog output consists of a half AD5547 output DAC, an operational amplifier driving the
output load, and two references DAC outputs each for VREF and VOFF.
AVSS
AVCC
TPCE636
DAC_OUTx
1/2
AD5547
16 bit Data
VREF
VOFF
-
+
one of two
AD5547 Channel
Figure 5-2 : DAC Output Channel