Tews Technologies TPMC851 User manual

The Embedded I/O Company
TPMC851
Multifunction I/O
(16 bit ADC/DAC, TTL I/O, Counter)
Version 1.0
User Manual
Issue 1.0.9
September 2014
TEWS TECHNOLOGIES GmbH
Am Bahnhof 7 25469 Halstenbek, Germany
Phone: [phone] Fax: [phone]
e-mail: [e-mail] www.tews.com

TPMC851-10R
Multifunction I/O
(16 bit ADC/DAC, TTL I/O, Counter)
This document contains information, which is proprietary
to TEWS TECHNOLOGIES GmbH. Any reproduction
without written permission is forbidden.
TEWS TECHNOLOGIES GmbH has made any effort to
ensure that this manual is accurate and complete.
However TEWS TECHNOLOGIES GmbH reserves the
right to change the product described in this document at
any time without notice.
TEWS TECHNOLOGIES GmbH is not liable for any
damage arising out of the application or use of the device
described herein.
Style Conventions
Hexadecimal characters are specified with prefix 0x, i.e.
0x029E (that means hexadecimal value 029E).
For signals on hardware products, an ‚Active Low’ is
represented by the signal name with # following, i.e.
IP_RESET#.
Access terms are described as:
W Write Only
R Read Only
R/W Read/Write
R/C Read/Clear
R/S Read/Set
¤2014 by TEWS TECHNOLOGIES GmbH
All trademarks mentioned are property of their respective owners.
TPMC851 User Manual Issue 1.0.9 Page 2 of 65

Issue Description Date
1.0 Initial Issue May 2004
1.1 Added ADC power-up note January 2005
1.2 Correction Interrupt Control Register ICR, Summarization of Important
Notes
February 2006
1.3 New address TEWS LLC September 2006
1.4 Changed PCI9030 Local Configuration
Clarified Sequencer Start / Stop Control in ADCSEQCONT
September 2006
1.5 Added note to ADC Control Register October 2006
1.0.6 New notation for HW Engineering Documentation Releases March 2009
1.0.7 Corrected DAC Data Register Reset Value to 0x0000 January 2010
1.0.8 General Revision August 2014
1.0.9 "PCI Base Address 2 for Local Address Space 0" initial value
corrected in Table "PCI9030 Header"
September 2014
TPMC851 User Manual Issue 1.0.9 Page 3 of 65

Table of Contents
1PRODUCT DESCRIPTION......................................................................................... 8
2TECHNICAL SPECIFICATION................................................................................. 10
3LOCAL SPACE ADDRESSING................................................................................ 12
PCI9030 Local Space Configuration ...........................................................................................123.1
Local Register Address Space ....................................................................................................123.2
3.2.1 Analog Input Registers........................................................................................................14
3.2.1.1 ADC Control Register ADCCONT (Offset 0x0000) ....................................................14
3.2.1.2 ADC Data Register ADCDATA (Offset 0x0004) .........................................................16
3.2.1.3 ADC Status Register ADCSTAT (Offset 0x0008).......................................................17
3.2.1.4 ADC Conversion Start Register ADCCONV (Offset 0x000C) ....................................18
3.2.1.5 ADC Sequencer Control Register ADCSEQCONT (Offset 0x0010) ..........................19
3.2.1.6 ADC Sequencer Status Register ADCSEQSTAT (Offset 0x0014).............................20
3.2.1.7 ADC Sequencer Timer Register ADCSEQTIME (Offset 0x0018) ..............................21
3.2.1.8 ADC Sequencer Instruction RAM (Offset 0x0020 - Offset 0x009C) ...........................22
3.2.2 Analog Output Registers.....................................................................................................24
3.2.2.1 DAC Control Register DACCONT (Offset 0x00C0)....................................................24
3.2.2.2 DAC Sequencer Status Register DACSEQSTAT (Offset 0x00C4) ............................25
3.2.2.3 DAC Sequencer Timer Register DACSEQTIME (Offset 0x00C8)..............................26
3.2.2.4 DAC Data Register DACDATA 1-8 (Offset 0x00D0 - Offset 0x00EC) .......................26
3.2.3 Digital I/O Registers ............................................................................................................27
3.2.3.1 Line Direction Register LINEDIR (Offset 0x0100) ......................................................27
3.2.3.2 Line Debounce Enable Register LINEDEB (Offset 0x0104).......................................28
3.2.3.3 Line Debounce Time Register LINEDBT (Offset 0x0108) ..........................................28
3.2.3.4 Line Input Register LINEIN (Offset 0x010C)...............................................................29
3.2.3.5 Line Output Register LINEOUT (Offset 0x0110) ........................................................30
3.2.3.6 Line Interrupt Enable Register LINEIEN (Offset 0x0114) ...........................................31
3.2.3.7 Line Interrupt Status Register LINEIST (Offset 0x0118) ............................................32
3.2.4 Counter Registers ...............................................................................................................33
3.2.4.1 Counter Preload Register CNTPRL (Offset 0x0120)..................................................33
3.2.4.2 Counter Compare Register CNTCMP (Offset 0x0124) ..............................................33
3.2.4.3 Counter Data Register CNTDATA (Offset 0x0128) ....................................................33
3.2.4.4 Counter Control Register CNTCONT (Offset 0x012C)...............................................34
3.2.4.5 Counter Status Register CNTSTAT (Offset 0x0130)..................................................36
3.2.4.6 Counter Command Register CNTCOM (Offset 0x0134) ............................................37
3.2.5 Interrupt Control Register ICR (Offset 0x0140) ..................................................................38
ADC Sequencer Data RAM...........................................................................................................393.3
ADC/DAC Calibration Data ROM .................................................................................................393.4
4PCI9030 TARGET CHIP........................................................................................... 41
PCI Configuration Registers (PCR) .............................................................................................414.1
4.1.1 PCI9030 Header .................................................................................................................41
4.1.2 PCI Base Address Initialization...........................................................................................42
Local Configuration Register (LCR)............................................................................................434.2
Configuration EEPROM ................................................................................................................444.3
Local Software Reset....................................................................................................................444.4
5CONFIGURATION HINTS ........................................................................................ 45
Big / Little Endian..........................................................................................................................455.1
TPMC851 User Manual Issue 1.0.9 Page 4 of 65

6PROGRAMMING HINTS .......................................................................................... 47
Data Correction .............................................................................................................................476.1
6.1.1 ADC Correction Formula.....................................................................................................47
6.1.2 DAC Correction Formula.....................................................................................................48
ADC Operating Modes..................................................................................................................486.2
6.2.1 Manual Mode ......................................................................................................................48
6.2.2 Sequencer Mode.................................................................................................................49
6.2.2.1 Sequencer Errors........................................................................................................50
6.2.3 Application Examples..........................................................................................................51
6.2.3.1 Fastest Conversion of an arbitrary Single Channel ....................................................51
6.2.3.2 Fastest Conversion of a specific Single Channel .......................................................51
6.2.3.3 Periodic Conversion of multiple Channels ..................................................................53
6.2.3.4 Continuous Conversion of multiple Channels.............................................................54
DAC Operating Modes..................................................................................................................556.3
6.3.1 Immediate Update...............................................................................................................55
6.3.2 Simultaneous Update..........................................................................................................55
Digital TTL I/O................................................................................................................................566.4
Counter Operating Modes............................................................................................................576.5
6.5.1 Input Modes ........................................................................................................................57
6.5.1.1 Timer Mode.................................................................................................................57
6.5.1.2 Direction Count ...........................................................................................................57
6.5.1.3 Up/Down Count...........................................................................................................57
6.5.1.4 Quadrature Count .......................................................................................................58
6.5.2 Count Modes.......................................................................................................................58
6.5.2.1 Divide-by-N .................................................................................................................58
6.5.2.2 Single Cycle ................................................................................................................58
6.5.3 Control Modes.....................................................................................................................58
6.5.3.1 No Control Mode.........................................................................................................59
6.5.3.2 Load Mode ..................................................................................................................59
6.5.3.3 Latch Mode .................................................................................................................59
6.5.3.4 Gate Mode ..................................................................................................................59
6.5.3.5 Reset Mode.................................................................................................................59
6.5.4 Configuration Examples......................................................................................................59
6.5.4.1 Watchdog Timer..........................................................................................................59
6.5.4.2 Event Counting ...........................................................................................................60
6.5.4.3 Input Pulse Width Measurement.................................................................................60
6.5.4.4 Mechanical System Positioning ..................................................................................60
Interrupts .......................................................................................................................................606.6
6.6.1 Interrupt Sources.................................................................................................................60
7INSTALLATION........................................................................................................ 62
ADC Input Wiring ..........................................................................................................................627.1
DAC Output Wiring .......................................................................................................................637.2
TTL I/O Interface............................................................................................................................637.3
8PIN ASSIGNMENT – I/O CONNECTOR .................................................................. 64
9IMPORTANT NOTES ............................................................................................... 65
Dummy Conversions after Power-up..........................................................................................659.1
Open Multiplexer Inputs ...............................................................................................................659.2
TPMC851 User Manual Issue 1.0.9 Page 5 of 65

List of Figures
FIGURE 1-1 : BLOCK DIAGRAM......................................................................................................................9
FIGURE 6-1 : FLOW: FASTEST CONVERSION OF AN ARBITRARY SINGLE CHANNEL .........................51
FIGURE 6-2 : FLOW: FASTEST CONVERSION OF A SPECIFIC SINGLE CHANNEL ................................52
FIGURE 6-3 : FLOW: PERIODIC CONVERSION OF MULTIPLE CHANNELS .............................................53
FIGURE 6-4 : FLOW: CONTINUOUS CONVERSION OF MULTIPLE CHANNELS ......................................54
FIGURE 6-5: QUADRATURE SIGNALS.........................................................................................................58
FIGURE 7-1 : ADC INPUT WIRING................................................................................................................62
FIGURE 7-2 : DAC OUTPUT WIRING............................................................................................................63
FIGURE 7-3 : TTL I/O INTERFACE ................................................................................................................63
List of Tables
TABLE 2-1 : TECHNICAL SPECIFICATION...................................................................................................11
TABLE 3-1 : PCI9030 LOCAL SPACE CONFIGURATION ............................................................................12
TABLE 3-2 : REGISTER WORD/BYTE ACCESSES ......................................................................................12
TABLE 3-3 : REGISTER ADDRESS SPACE..................................................................................................13
TABLE 3-4 : ADC CONTROL REGISTER ......................................................................................................15
TABLE 3-5 : ADC DATA REGISTER .............................................................................................................16
TABLE 3-6 : ADC DATA CODING ..................................................................................................................16
TABLE 3-7 : ADC STATUS REGISTER..........................................................................................................17
TABLE 3-8 : ADC SEQUENCER CONTROL REGISTER ..............................................................................19
TABLE 3-9 : ADC SEQUENCER STATUS REGISTER..................................................................................20
TABLE 3-10: ERROR FLAG IRQ GENERATION ...........................................................................................20
TABLE 3-11: ADC SEQUENCER TIMER REGISTER....................................................................................21
TABLE 3-12: ADC SEQUENCER INSTRUCTION RAM REGISTER .............................................................22
TABLE 3-13: ADC SEQUENCER INSTRUCTION RAM REGISTER POSITIONS ........................................23
TABLE 3-14: DAC CONTROL REGISTER .....................................................................................................24
TABLE 3-15: DAC SEQUENCER STATUS REGISTER.................................................................................25
TABLE 3-16: DAC SEQUENCER TIMER REGISTER....................................................................................26
TABLE 3-17: DAC DATA REGISTER .............................................................................................................26
TABLE 3-18: DAC DATA CODING .................................................................................................................26
TABLE 3-19: LINE DIRECTION REGISTER...................................................................................................27
TABLE 3-20: LINE DEBOUNCE ENABLE REGISTER...................................................................................28
TABLE 3-21: LINE DEBOUNCE TIME REGISTER ........................................................................................28
TABLE 3-22: LINE INPUT REGISTER............................................................................................................29
TABLE 3-23: LINE OUTPUT REGISTER........................................................................................................30
TABLE 3-24: LINE INTERRUPT ENABLE REGISTER ..................................................................................31
TABLE 3-25: LINE INTERRUPT STATUS REGISTER ..................................................................................32
TABLE 3-26: COUNTER PRELOAD REGISTER ...........................................................................................33
TABLE 3-27: COUNTER COMPARE REGISTER ..........................................................................................33
TABLE 3-28: COUNTER DATA REGISTER ...................................................................................................33
TPMC851 User Manual Issue 1.0.9 Page 6 of 65

TABLE 3-29: COUNTER CONTROL REGISTER ...........................................................................................35
TABLE 3-30: COUNTER STATUS REGISTER ..............................................................................................36
TABLE 3-31: COUNTER COMMAND REGISTER .........................................................................................37
TABLE 3-32: INTERRUPT CONTROL REGISTER ........................................................................................38
TABLE 3-33: ADC SEQUENCER DATA RAM SPACE ADDRESS MAP .......................................................39
TABLE 3-34: ADC/DAC CALIBRATION ROM DATA SPACE ADDRESS MAP.............................................40
TABLE 4-1 : PCI9030 HEADER ......................................................................................................................41
TABLE 4-2 : PCI9030 PCI BASE ADDRESS USAGE ....................................................................................42
TABLE 4-3 : PCI9030 LOCAL CONFIGURATION REGISTER ......................................................................43
TABLE 4-4 : CONFIGURATION EEPROM TPMC851-10R............................................................................44
TABLE 5-1 : LOCAL BUS LITTLE/BIG ENDIAN .............................................................................................45
TABLE 6-1 : SEQUENCER ERRORS.............................................................................................................50
TABLE 6-2 : DAC LOAD MODES ...................................................................................................................55
TABLE 6-3 : INPUT MODES ...........................................................................................................................57
TABLE 6-4 : CLOCK PRESCALER.................................................................................................................57
TABLE 6-5 : COUNT DIRECTIONS................................................................................................................57
TABLE 6-6 : INPUT CONTROL MODE EVENTS ...........................................................................................59
TABLE 6-7: GATE MODE ...............................................................................................................................59
TABLE 6-8 : INTERRUPT SOURCES ............................................................................................................61
TABLE 8-1 : PIN ASSIGNMENT I/O CONNECTOR .......................................................................................64
TPMC851 User Manual Issue 1.0.9 Page 7 of 65

1 Product Description
The TPMC851 combines 32 single ended / 16 differential channels of 16 bit multiplexed analog input, 8 channels
of 16 bit analog output, 16 digital I/O lines and a 32 bit multi-purpose counter on a standard single-width PMC
module.
A 16 bit ADC converts 32 single-ended or 16 differential multiplexed ADC input channels. The data acquisition
and conversion time is up to 1.25μs without channel/gain change and up to 17.25μs with channel/gain change.
The input multiplexer of the A/D circuit offers analog overvoltage protection of up to 70Vpp. A programmable gain
amplifier allows gains of 1, 2, 4 or 8 resulting in input voltage ranges of ±10V, ±5V, ±2.5V or ±1.25V.
The ADC part of the TPMC851 can operate in Manual Mode or Sequencer Mode:
xManual Mode
In Manual Mode the multiplexer, programmable gain amplifier and the converter are fully controlled by the
user. A conversion for a selected channel / gain can be started automatically after the settling time has
elapsed, or manually by the user.
xSequencer Mode
In Sequencer Mode each of the A/D channels can be independently enabled and configured for the
sequencer. The sequencer can run continuously, at specific time intervals, or it may be triggered by an
external event. Conversion data is stored in a data RAM.
The 8 analog output channels are realized by eight 16 bit digital to analog converters (DACs). The conversion
time is 10 μs. An operational amplifier drives the full-scale range of ±10V and is capable to drive high capacitive
loads. Similar to the analog inputs a sequencer can control the analog outputs. Following operation modes are
available:
xImmediate Update: Updates the DAC output immediately when new data is written to the DAC channel.
xSimultaneous Update: DAC data is buffered and all DAC outputs are updated simultaneously on a
trigger event:
oManual Update: Updates all DAC outputs on a manual event (register write)
oTrigger Update: Updates all DAC outputs on a external event
oSequencer Update: Updates all DAC outputs after the sequencer timer has elapsed
Each TPMC851 is factory calibrated. The calibration data is stored in an EEPROM unique to each TPMC851.
The 16 digital TTL tri-VWDWH ,2 OLQHV ZLWK N SXOO XS UHVLVWRUV DUH (6' SURWHFWHG DQG SURWHFWHG DJDLQVW
overvoltage. All 16 lines can be individually programmed as input or output, and can generate an interrupt on
negative and positive transitions. Each input has an electronic debounce circuit to prevent short spikes on the
input lines to cause an interrupt. The digital inputs can supply the external signals for the ADC and DAC
sequencer and the 32 bit counter.
TPMC851 User Manual Issue 1.0.9 Page 8 of 65

Additionally the TPMC851 offers a 32 bit multi-purpose counter. The counter includes a 32 bit preload register
and a 32 bit compare register. The 32 bit counter can be fed with an internal clock or with an external signal
supplied by the digital inputs. The 4 counter input modes determine the interpretation of the input signals.
Additionally 3 count modes, which describe the behavior of the counter, and 4 control modes are available.
xCounter input modes:
oInternal clock with prescaler
oUp/Down count: first counter input counts up, second input counts down
oDirection count: first counter input counts, second input sets count direction
oQuadrature count with 1x, 2x or 4x resolution multiplier
xCount modes:
oCycling Counter: normal wrap-around count mode
oDivide-by-N: counter is reloaded from the preload register upon a borrow or carry
oSingle Cycle: counter stops upon a borrow or carry
xControl Modes:
oLoad on Control: counter is reloaded from the preload register
oLatch on Control: counter value is latched
oGate on Control: counter input is gated
oReset on Control: counter is reset
Figure 1-1 : Block Diagram
TPMC851 User Manual Issue 1.0.9 Page 9 of 65

2 Technical Specification
PMC Interface
Mechanical Interface PCI Mezzanine Card (PMC) Interface
Single Size
Electrical Interface PCI Rev. 2.2 compliant
33 MHz / 32 bit PCI
3.3V and 5V PCI Signaling Voltage
On Board Devices
PCI Target Chip PCI9030 (PLX Technology)
ADC AD7663
DAC DAC7644
Analog Input
Number of Analog Inputs 32 single-ended or 16 differential channels
Input Gain Amplifier Programmable for gain 1, 2, 4 and 8
Input Voltage Range ±10V for gain = 1
±5V for gain = 2
±2.5V for gain = 4
±1.25V for gain = 8
Input Overvoltage Protection 70Vpp
Calibration Data Calibration data for gain and offset correction in ID PROM
Resolution 16 bit with no missing codes
Conversion Time 1.25μs without channel/gain change
17.25μs with channel/gain change
16μs / channel in sequencer mode
Accuracy ±2 LSB @ 25°C after calibration
Linearity ±2 LSB @ 25°C after calibration
ADC INL/DNL Error ±3 LSB
Analog Output
Number of Analog Outputs 8 analog output channels
Output Voltage Range ±10V
Calibration Data Calibration data for gain and offset correction in ID PROM
Resolution 16 bit
Conversion Time 10μs max.
Accuracy ±1 LSB @ 25°C after calibration
Linearity ±2 LSB @ 25°C after calibration
DAC INL/DNL Error ±4/±3 LSB
Capacitive Load Up to 10 000pF
TPMC851 User Manual Issue 1.0.9 Page 10 of 65

Digital I/O
Number of Digital I/O 16 digital I/O channels
Overvoltage Protection 30V
Minimum Pulse Width Programmable, 100ns – 6.55ms
I/O Interface
I/O Connector Front I/O: HD68 SCSI-3 type female connector (AMP 787082-7)
No PMC P14 I/O
Physical Data
Power Requirements 295 mA typical @ +3.3V DC
165 mA typical @ +5V DC
10 mA typical @ -12V DC
Temperature Range Operating
Storage
-40°C to +85 °C
-40°C to +85°C
MTBF 330000 h
MTBF values shown are based on calculation according to MIL-HDBK-217F and
MIL-HDBK-217F Notice 2; Environment: GB20°C.
The MTBF calculation is based on component FIT rates provided by the
component suppliers. If FIT rates are not available, MIL-HDBK-217F and
MIL-HDBK-217F Notice 2 formulas are used for FIT rate calculation.
Humidity 5 – 95 % non-condensing
Weight 82 g
Table 2-1 : Technical Specification
TPMC851 User Manual Issue 1.0.9 Page 11 of 65

3 Local Space Addressing
PCI9030 Local Space Configuration3.1
The local on board addressable regions are accessed from the PCI side by using the PCI9030 local spaces.
PCI9030
Local
Space
PCI9030
PCI Base Address
(Offset in PCI
Configuration Space)
PCI Space
Mapping
Size
(Byte)
Port
Width
(Bit)
Endian
Mode
Description
0 2 (0x18) MEM 512 32 BIG Local Register Address
Space
1 3 (0x1C) MEM 64 16 BIG Sequencer Data RAM
2 4 (0x20) MEM 64 16 BIG ADC/DAC Calibration
ROM Data
3 5 (0x24) - - - - Not Used
Table 3-1 : PCI9030 Local Space Configuration
Local Register Address Space3.2
PCI Base Address: PCI9030 PCI Base Address 2 (Offset 0x18 in PCI Configuration Space).
The register offsets stated below refer to 32 bit accesses. The registers shorter than 32 bit are filled with zeros on
long word read-accesses. Refer to chapter ‘Big/Little Endian’ or the following table for correct word- or byte-wide
accesses.
Access Width Register Bits
[31:24] [23:16] [15:8] [7:0]
32 bit Register Offset
16 bit Register Offset Register Offset +2
8 bit Register
Offset
Register
Offset +1
Register
Offset +2
Register
Offset +3
Table 3-2 : Register word/byte Accesses
Offset to PCI Base
Address 2
Symbol Register Name
0x0000 ADCCONT ADC Control Register
0x0004 ADCDATA ADC Data Register
0x0008 ADCSTAT ADC Status Register
0x000C ADCCONV ADC Conversion Start Register
0x0010 ADCSEQCONT ADC Sequencer Control Register
0x0014 ADCSEQSTAT ADC Sequencer Status Register
0x0018 ADCSEQTIME ADC Sequencer Timer Register
0x001C - Not used
0x0020 – 0x009C ADCSEQIRAM ADC Sequencer Instruction RAM 1-32
0x00A0 – 0x00BF - Not used
TPMC851 User Manual Issue 1.0.9 Page 12 of 65

Offset to PCI Base
Address 2
Symbol Register Name
0x00C0 DACCONT DAC Control Register
0x00C4 DACSEQSTAT DAC Sequencer Status Register
0x00C8 DACSEQTIME DAC Sequencer Timer Register
0x00CC - Not used
0x00D0 – 0x00EC DACDATA DAC Data Register 1-8
0x00F0 – 0x00FF - Not used
0x0100 LINEDIR Line Direction Register
0x0104 LINEDEB Line Debounce Enable Register
0x0108 LINEDBT Line Debounce Time Register
0x010C LINEIN Line Input Register
0x0110 LINEOUT Line Output Register
0x0114 LINEIEN Line Interrupt Enable Register
0x0118 LINEIST Line Interrupt Status Register
0x011C - Not used
0x0120 CNTPRL Counter Preload Register
0x0124 CNTCMP Counter Compare Register
0x0128 CNTDATA Counter Data Register
0x012C CNTCONT Counter Control Register
0x0130 CNTSTAT Counter Status Register
0x0134 CNTCOM Counter Command Register
0x0138 – 0x013F - Not used
0x0140 ICR Interrupt Control Register
0x0144 – 0x014F - Factory use only. Do not Write.
0x0150 – 0x01FF - Not used
Table 3-3 : Register Address Space
Addresses “Not used” will return 0 when read.
TPMC851 User Manual Issue 1.0.9 Page 13 of 65

3.2.1 Analog Input Registers
3.2.1.1 ADC Control Register ADCCONT (Offset 0x0000)
Bit Symbol Description Access Reset
Value
31:12 - Reserved
Write: don't care
Read: always reads as '0'
R0
11 RST ADC Reset
If RST is set to ‘1’, the ADC is reset. Current conversions are aborted.
This bit is cleared immediately after a write access
R/W 0
10 IRQC IRQ after Conversion Enable
0 = IRQ after Conversion disabled
1 = IRQ after Conversion enabled
An interrupt will be generated after a conversion is finished
(ADC_BUSY changes from 1 to 0).
For pending interrupts and interrupt acknowledge see the ADC Status
Register ADCSTAT.
R/W 0
9 IRQST IRQ after Settling Time Enable
0 = IRQ after Settling Time disabled
1 = IRQ after Settling Time enabled
An interrupt will be generated after the settling time has elapsed
(SETTL_BUSY changes from 1 to 0)
For pending interrupts and interrupt acknowledge see the ADC Status
Register ADCSTAT.
R/W 0
8 ASTC Automatic Settling Time Control
0 = OFF (Normal Mode)
A conversion must be initiated manually in the ADC Conversion Start
Register ADCCONV.
1 = ON (Automatic Mode)
A conversion is automatically initiated after the settling time has
elapsed.
The ADC settling time is appr. 16μs.
R/W 0
7:6 GAIN [1:0] Gain Selection (Analog Input Amplifier)
GAIN1 GAIN0 Gain Factor Input Voltage Range
0 0 1 ±10V
01 2 ±5V
1 0 4 ±2.5V
1 1 8 ±1.25V
R/W 00
5 SE/DIFF Single/Differential Mode Control
0 = Single-ended mode
32 single-ended input channels available
1 = Differential mode
16 differential input channels available
R/W 0
TPMC851 User Manual Issue 1.0.9 Page 14 of 65

Bit Symbol Description Access Reset
Value
4:0 CS[4:0] Channel Select (Analog Input Channel)
CS[4:0]
Single-ended
Channel
SE/DIFF = 0
Differential Channel
SE/DIFF = 1
00000 CH1 CH1
………
01111 CH16 CH16
10000 CH17 N/A
………
11111 CH32 N/A
‘N/A’ = ADC Input connected to GND
R/W 00000
Table 3-4 : ADC Control Register
A write to this register sets the new channel and gain. Subsequent write accesses are ignored until the
settling time has elapsed. This register is developed for a word (16 bit) or long word (32 bit) read/write
access. Byte accesses on this register are not supported and will fail.
Do NOT write to this register while the sequencer is running! A write to this register while the sequencer
is running can lead to unpredictable results!
Interrupts are generated only if the Master Interrupt Enable (MIE) is enabled in the Interrupt Control
Register ICR.
TPMC851 User Manual Issue 1.0.9 Page 15 of 65

3.2.1.2 ADC Data Register ADCDATA (Offset 0x0004)
The ADC Data Register contains the converted data value. The output format is two’s complement.
This register is updated if the conversion was initiated with the ADC Conversion Start Register ADCCONV or by
the Automatic Settling Time Control ASTC on the falling edge of ADC_BUSY in the ADC Status Register
(ADCSTAT). Conversions initiated by the sequencer will have no effect to this register.
Bit Symbol Description Access Reset
Value
31:16 - Reserved
Write: don't care
Read: always reads as '0'
R0
15:0 Stores the converted 16 bit data value. R 0
Table 3-5 : ADC Data Register
Description ±10V
(Gain 1)
±5V (Gain 2) ±2.5V
(Gain 4)
±1.25V
(Gain 8)
Two’s
Complement
Full Scale Range ±10V ±5V ±2.5 ±1.25
Least Significant
Bit
305.2μV 152.6μV 76.2μV 38.15μV
FSR - 1LSB 9.999695V 4.999847V 2.499924V 1.249962V 0x7FFF¹
Midscale + 1LSB 305.2μV 152.6μV 76.2μV 38.15μV 0x0001
Midscale 0V 0V 0V 0V 0x0000
Midscale – 1LSB -305.2μV -152.6μV -76.2μV -38.15μV 0xFFFF
-FSR + 1LSB -9.999695V -4.999847V -2.499924V -1.249962V
Full Scale (neg.) -10V -5V -2.5V 1.25V 0x8000²
¹This is also the code for an overrange analog input.
²This is also the code for an underrange analog input.
Table 3-6 : ADC Data Coding
After power up the on board ADC device is in a random state and requires two dummy conversions
before operating correctly. This is based on the chip design of the ADC device.
Software should ignore the data of the first two ADC conversions after power-up.
The software drivers from TEWS TECHNOLOGIES already include these two dummy conversions.
TPMC851 User Manual Issue 1.0.9 Page 16 of 65

3.2.1.3 ADC Status Register ADCSTAT (Offset 0x0008)
Bit Symbol Description Access Reset
Value
31:4 - Reserved
Write: don't care
Read: always read as '0'
R0
3SETTL
IRQ
Pending Settling Time Interrupts (Read),
Interrupt acknowledge (Write)
On a read-access this bit shows a pending Settling Time interrupt.
Pending interrupts are marked with a '1'.
An interrupt is acknowledged by writing a '1' to this bit after the error
flags are cleared.
R/C 0
2 ADC IRQ Pending Conversion Interrupts (Read),
Interrupt acknowledge (Write)
On a read-access this bit shows a pending Conversion interrupt.
Pending interrupts are marked with a '1'.
An interrupt is acknowledged by writing a '1' to this bit after the error
flags are cleared.
R/C 0
1SETTL
BUSY
SETTL_BUSY
Indicates that the required settling time after a write to the CONTREG
register is not yet done.
This bit is set by writing to the CONTREG register. The bit is cleared
when the required settling time has elapsed.
This bit must be read as '0' before a conversion is started by a write to
the ADC Conversion Start Register ADCCONV.
The ADC settling time is appr. 16μs.
R0
0ADC
BUSY
ADC_BUSY
Indicates if an actual data conversion is in progress.
If "Automatic Settling Time Mode" is OFF, this bit is set by writing to
the ADC Conversion Start Register ADCCONV.
If “Automatic Settling Time Mode” is ON, this bit is set automatically
after the settling time has elapsed.
This bit must be read as '0' before the conversion data is read from the
DATAREG register.
R0
Table 3-7 : ADC Status Register
Interrupts are generated only if the Master Interrupt Enable (MIE) is enabled in the Interrupt Control
Register ICR.
TPMC851 User Manual Issue 1.0.9 Page 17 of 65

3.2.1.4 ADC Conversion Start Register ADCCONV (Offset 0x000C)
The ADC Conversion Start Register is used to start an ADC conversion when “Automatic Settling Time Mode” is
OFF. Any write access starts the conversion. The user must read the SETTL_BUSY bit in the ADC Status
Register as '0' or wait for a Settling Time Interrupt before the conversion is started. The ADC_BUSY bit in the
ADC Status Register indicates if the conversion data in the ADC Data Register is valid (ADC_BUSY bit = '0').
It is allowed to set up a new channel/gain by writing to the ADC Control Register CONTREG immediately
after starting an ADC conversion.
If “Sequencer Mode” is selected (SEQCONT register bit 0 is set to ‘1’) all write accesses to the ADC
Conversion Start Register ADCCONV are ignored.
Please pay attention to the chapter “Important Notes”.
TPMC851 User Manual Issue 1.0.9 Page 18 of 65

3.2.1.5 ADC Sequencer Control Register ADCSEQCONT (Offset 0x0010)
Bit Symbol Description Access Reset
Value
31:3 - Reserved
Write: don't care
Read: always reads as '0'
R0
2SEQ INT
ENA
Sequencer Interrupt Enable Control
0 = Sequencer Interrupt Disabled
1 = Sequencer Interrupt Enabled
An interrupt request will be generated if any error flag is set in the
ADCSEQSTAT Register (Sequencer Data Valid or Sequencer Error).
For pending interrupts and interrupt acknowledge see ADC Sequencer
Status Register ADCSEQSTAT.
R/W 0
1SEQ
TRIG
Sequencer Trigger Source
0 = Sequencer Timer
1 = External Signal (Dig I/O Line 0)
R/W 0
0 SEQ ON Sequencer Start / Stop Control
0 = Stops the Sequencer after last Instruction (Sequencer Continuous
Mode: Sequencer stops immediately). No DATA AV will be issued.
1 = Starts the Sequencer immediately
R/W 0
Table 3-8 : ADC Sequencer Control Register
If an error flag (DATA_OVERFLOW_ERROR, TIMER_ERROR, I-RAM_ERROR) is set in the Sequencer
Status Register SEQSTAT, the sequencer will be stopped after the last instruction (SEQ_ON will be set to
'0'). The user must clear the status bits and start the sequencer again.
Interrupts are generated only if the Master Interrupt Enable (MIE) is enabled in the Interrupt Control
Register ICR.
Please pay attention to the chapter “Important Notes” before using the sequencer.
If ADC_OUT in the Line Direction Register LINEDIR is set to ‘1’, the trigger signal for the sequencer is available
for external use on Dig I/O Line 0.
Do not use the External Signal as Sequencer Trigger Source if ADC_OUT is enabled. This will cause the
sequencer to lock.
TPMC851 User Manual Issue 1.0.9 Page 19 of 65

3.2.1.6 ADC Sequencer Status Register ADCSEQSTAT (Offset 0x0014)
Bit Symbol Description Access Reset
Value
31:5 - Reserved
Write: don't care
Read: always reads as '0'
R0
4 SEQ IRQ Pending Sequencer Interrupts (Read),
On a read-access this bit shows a pending Sequencer interrupt.
Pending interrupts are marked with a '1'.
An interrupt is acknowledged when the error flags are cleared.
R0
3I-RAM
ERROR
Instruction RAM Error Flag
Set by the sequencer if the sequencer has been started and there is
no instruction in the Sequencer Instruction RAM.
To clear this flag the user must write ‘1’ to this bit.
R/C 0
2TIMER
ERROR
Timer Error Flag
Set by the sequencer if the sequencer timer has elapsed but the
actual sequence is still in progress.
To clear the Timer Error Flag the user must write ‘1’ to this bit.
If the Sequencer Timer Register is 0 (Sequencer Continuous Mode)
the Timer Error Flag always reads as ‘0’.
R/C 0
1DATA
OVERFLOW
ERROR
Data Overflow Error Flag
Set by the sequencer if the last sequencer instruction is done and
the Data Available Flag of the previous sequence has not yet been
cleared by the user.
To clear the error flag the user must write ‘1’ to this bit.
If the Sequencer Timer Register is 0 (Sequencer Continuous Mode)
the Data Overflow Error Flag always reads as ‘0’.
R/C 0
0 DATA AV Data Available Flag
Set if a sequence is done and new ADC Data is available in the ADC
Data RAM.
After reading the ADC Data RAM the user must clear the Data
Available Flag by writing ‘1’ to this bit.
R/C 0
Table 3-9 : ADC Sequencer Status Register
Description Sequencer
Timer
Continuous
Mode
External
Trigger
Data Available Flag Active, IRQ Active, no IRQ Active, IRQ
Data Overflow Error Flag Active, IRQ Disabled Active, IRQ
Timer Error Flag Active, IRQ Disabled Active, IRQ
Instruction RAM Error Flag Active, IRQ Active, IRQ Active, IRQ
Table 3-10: Error Flag IRQ generation
Also see chapter ‘Sequencer Errors’ for details.
TPMC851 User Manual Issue 1.0.9 Page 20 of 65