Tews Technologies TPMC632 Series User manual

The Embedded I/O Company
TPMC632
Reconfigurable FPGA
with 64 TTL I/O / 32 Differential I/O Lines
Version 1.0
User Manual
Issue 1.0.6
November 2017
TEWS TECHNOLOGIES GmbH
Am Bahnhof 7
25469 Halstenbek, Germany
Phone: [phone]
Fax: [phone]
e-mail: [email protected]
www.tews.com

TPMC632 User Manual Issue 1.0.6 Page 2 of 49
TPMC632-10R
64 TTL I/O Lines, XC6SLX45T-2 Spartan-
6
FPGA,128 MB DDR3
TPMC632-11R
32 Differential I/O Lines, XC6SLX45T-2 Spartan-
6 FPGA,128 MB DDR3
TPMC632-12R
32 TTL and 16
Differential I/O Lines,
XC6SLX45T-2 Spartan-6 FPGA,128 MB DDR3
TPMC632-13R
32 Differential M-LVDS Lines, XC6SLX45T-
2
Spartan-6 FPGA,128 MB DDR3
TPMC632-14R
32 TTL and 16 Differential M-
LVDS Lines,
XC6SLX45T-2 Spartan-6 FPGA,128 MB DDR3
TPMC632-20R
64 TTL I/O Lines, XC6SLX100T-2 Spartan-
6
FPGA,128 MB DDR3
TPMC632-21R
32 Differential I/O Lines, XC6SLX100T-
2
Spartan-6 FPGA,128 MB DDR3
TPMC632-22R
32 TTL and 16
Differential I/O Lines,
XC6SLX100T-2 Spartan-6 FPGA,128 MB DDR3
TPMC632-23R
32 Differential M-LVDS Lines, XC6SLX100T-
2
Spartan-6 FPGA ,128 MB DDR3
TPMC632-24R
32 TTL and 16 Differential M-
LVDS Lines,
XC6SLX100T-2 Spartan-6 FPGA ,128 MB DDR3
This document contains information, which is
proprietary to TEWS TECHNOLOGIES GmbH. Any
reproduction without written permission is forbidden.
TEWS TECHNOLOGIES GmbH has made any
effort to ensure that this manual is accurate and
complete. However TEWS TECHNOLOGIES GmbH
reserves the right to change the product described
in this document at any time without notice.
TEWS TECHNOLOGIES GmbH is not liable for any
damage arising out of the application or use of the
device described herein.
Style Conventions
Hexadecimal characters are specified with prefix 0x,
i.e. 0x029E (that means hexadecimal value 029E).
For signals on hardware products, an ‘
Active Low’ is
represented by the signal name with # following, i.e.
IP_RESET#.
Access terms are described as:
W Write Only
R Read Only
R/W Read/Write
R/C Read/Clear
R/S Read/Set
2017 by TEWS TECHNOLOGIES GmbH
All trademarks mentioned are property of their respective owners.

TPMC632 User Manual Issue 1.0.6 Page 3 of 49
Issue
Description
Date
1.0.0 Initial Issue January 2012
1.0.1 Four further board variants with M-LVDS I/O buffers are
created January 2013
1.0.2 Added chapter “Known Issue” May 2013
1.0.3 Added DDR3 SDRAM Alternative Part May 2015
1.0.4 Added SPI-Flash Alternative Part September 2015
1.0.5 Alternative configurations SPI-Flash assembly May 2017
1.0.6 Rename differential I/O connector Pins November 2017

TPMC632 User Manual Issue 1.0.6 Page 4 of 49
Table of Contents
1PRODUCT DESCRIPTION ...........................................................................................7
2TECHNICAL SPECIFICATION .....................................................................................8
3HANDLING AND OPERATION INSTRUCTION .........................................................10
ESD Protection..............................................................................................................................103.1
Thermal Considerations...............................................................................................................103.2
4FUNCTIONAL DESCRIPTION....................................................................................11
FPGA Block Diagram....................................................................................................................114.1
FPGA ..............................................................................................................................................124.2
Gigabit Transceiver (GTP)............................................................................................................134.3
Configuration.................................................................................................................................144.4
4.4.1 Selecting the Configuration Source........................................................................................14
4.4.2 JTAG.......................................................................................................................................15
4.4.3 Board Configuration CPLD.....................................................................................................15
4.4.4 Programming Configuration devices.......................................................................................16
Clocking.........................................................................................................................................174.5
4.5.1 FPGA Clock Sources..............................................................................................................17
I/O Interface ...................................................................................................................................184.6
Memory ..........................................................................................................................................224.7
4.7.1 DDR3 SDRAM........................................................................................................................22
4.7.2SPI-Flash................................................................................................................................24
User GPIO......................................................................................................................................254.8
On Board Indicators......................................................................................................................264.9
Thermal Management...................................................................................................................264.10
5DESIGN HELP ............................................................................................................27
Example Design ............................................................................................................................275.1
6INSTALLATION ..........................................................................................................28
Pull Up Voltage..............................................................................................................................286.1
I/O Interface ...................................................................................................................................296.2
6.2.1 TTL I/O Interface.....................................................................................................................29
6.2.2 Differential I/O Interface..........................................................................................................30
6.2.3 Multipoint-LVDS Interface.......................................................................................................30
Back I/O Configuration.................................................................................................................316.3
FPGA Debug Connector...............................................................................................................336.4
6.4.1 Connecting TA900 to TPMC632 Debug Connector ...............................................................33
FPGA JTAG Connector.................................................................................................................346.5
7PIN ASSIGNMENT – I/O CONNECTOR.....................................................................35
Overview ........................................................................................................................................357.1
X1 Front Panel I/O Connector......................................................................................................357.2
7.2.1 Connector Type ......................................................................................................................35
7.2.2 Pin Assignment.......................................................................................................................36
Back I/O PMC Connector P14......................................................................................................377.3
7.3.1 Connector Type ......................................................................................................................37
7.3.2 Pin Assignment.......................................................................................................................37

TPMC632 User Manual Issue 1.0.6 Page 5 of 49
X2 JTAG Header............................................................................................................................397.4
7.4.1 Connector Type ......................................................................................................................39
7.4.2 Pin Assignment.......................................................................................................................39
X3 Debug-Connector ....................................................................................................................407.5
7.5.1 Connector Type ......................................................................................................................40
7.5.2 Pin Assignment.......................................................................................................................40
8KNOWN ISSUES.........................................................................................................41
9APPENDIX A...............................................................................................................42

TPMC632 User Manual Issue 1.0.6 Page 6 of 49
List of Figures
FIGURE 1-1 : BLOCK DIAGRAM......................................................................................................................7
FIGURE 4-1 : FPGA BLOCK DIAGRAM.........................................................................................................11
FIGURE 4-2 : GTP BLOCK DIAGRAM...........................................................................................................13
FIGURE 4-3 : CONFIGURATION SOURCE SELECTION .............................................................................14
FIGURE 4-4 : CONFIGURATION DIP-SWITCH SETTINGS..........................................................................14
FIGURE 4-5 : JTAG-CHAIN............................................................................................................................15
FIGURE 4-6 : CONFIGURATION DIP-SWITCH SETTINGS..........................................................................15
FIGURE 4-7 : FPGA CLOCK SOURCES........................................................................................................17
FIGURE 6-1 : PULL (UP) VOLTAGE JUMPER SETTING..............................................................................28
FIGURE 6-2 : TTL I/O INTERFACE................................................................................................................29
FIGURE 6-3 : DIFFERENTIAL I/O INTERFACE.............................................................................................30
FIGURE 6-4 : M-LVDS I/O INTERFACE.........................................................................................................30
FIGURE 6-5 : JUMPER POSITIONS FOR GROUND OPTION......................................................................31
FIGURE 6-6 : JUMPER POSITIONS FOR BACK I/O OPTIONS....................................................................32
FIGURE 6-7 : DEBUG CONNECTOR X3.......................................................................................................33
FIGURE 6-8 : FPGA JTAG CONNECTOR X2................................................................................................34
FIGURE 7-1 : FRONT PANEL I/O CONNECTOR NUMBERING...................................................................35
List of Tables
TABLE 2-1 : TECHNICAL SPECIFICATION.....................................................................................................9
TABLE 4-1 : TPMC632 FPGA FEATURE OVERVIEW ..................................................................................12
TABLE 4-2 : FPGA BANK USAGE..................................................................................................................12
TABLE 4-3 : GTP CONNECTIONS.................................................................................................................13
TABLE 4-4 : MULTI GIGABIT TRANSCEIVER REFERENCE CLOCKS .......................................................13
TABLE 4-5 : AVAILABLE FPGA CLOCKS......................................................................................................17
TABLE 4-6 : DIGITAL I/O INTERFACE...........................................................................................................21
TABLE 4-7 : DDR3 SDRAM INTERFACE.......................................................................................................23
TABLE 4-8 : FPGA SPI-FLASH CONNECTIONS...........................................................................................24
TABLE 4-9 : FPGA GENERAL PURPOSE I/O ...............................................................................................25
TABLE 4-10: BOARD-STATUS AND USER LEDS ........................................................................................26
TABLE 7-1 : PIN ASSIGNMENT FRONT PANEL I/O CONNECTOR X1.......................................................36
TABLE 7-2 : PIN ASSIGNMENT BACK I/O PMC CONNECTOR P14............................................................38
TABLE 7-3 : PIN ASSIGNMENT JTAG HEADER X2 .....................................................................................39
TABLE 7-4 : PIN ASSIGNMENT DEBUG CONNECTOR X3 .........................................................................40

TPMC632 User Manual Issue 1.0.6 Page 7 of 49
1 Product Description
The TPMC632 is a standard single-width 32 bit PMC module providing a user configurable XC6SLX45T-2 or
XC6SLX100T-2 Spartan-6 FPGA. The integrated Spartan-6’s PCIe Endpoint Block is connected to a PCIe-
to-PCI Bridge which routed to the PMC PCI Interface.
Different variants of the TPMC632 provide ESD-protected TTL lines, ESD-protected differential I/O lines and
differential Multipoint-LVDS lines. Also combination of 32 TTL and 16 differential I/O lines are supported.
All lines are individually programmable as input, output or tri-state. The receivers are always enabled, which
allows determining the state of each I/O line at any time. This can be used as read back function for lines
configured as outputs. Each TTL I/O line has a pull resistor. The pull voltage level is selectable to be either
+3.3V, +5V and additionally GND. The differential I/O lines are terminated by 120Ωresistors and the
differential Multipoint-LVDS lines are terminated by 100Ωresistors.
The FPGA is connected to a 128 Mbytes, 16 bit wide DDR3 SDRAM. As SDRAM-interface a hardwired
internal Memory Controller Block of the Spartan-6 is used.
The FPGA is configured by a platform flash or SPI flash. The flash device is in-system programmable. An in-
circuit debugging option is available via a JTAG header for read back and real-time debugging of the FPGA
design (using Xilinx “ChipScope”).
The TPMC632 provides either front panel I/O via a HD68 SCSI-3 type connector and rear panel I/O via P14.
User applications for the TPMC632 with XC6SLX45T-2 FPGA can be developed using the design software
ISE WebPACK which can be downloaded free of charge from www.xilinx.com. The larger FPGA densities
require a full licensed ISE Design Suite.
TEWS offers an FPGA Development Kit (TPMC632-FDK) which consists of well documented basic example
design. It includes an .ucf file with all necessary pin assignments and basic timing constraints. The example
design covers the main functionalities of the TPMC632. It implements a DMA capable PCIe endpoint with
interrupt support, register mapping, DDR3 memory access and basic I/O. It comes as a Xilinx ISE project
with source code and as a ready-to-download bitstream.
Please note: The basic example design requires the Embedded Development Kit (EDK), which is part of the
Embedded or System Edition of the ISE Design Suite from Xilinx (downloadable from www.xilinx.com, a 30
day evaluation license is available).
Software Support (TPMC632-SW-xx) for different operating systems is available.
Figure 1-1 : Block Diagram

TPMC632 User Manual Issue 1.0.6 Page 8 of 49
2 Technical Specification
PMC Interface
Mechanical Interface PCI Mezzanine Card (PMC) Interface confirming to IEEE
P1386/P1386.1
Single Size
Electrical Interface PCI Rev. 3.0 compliant
33 MHz or 66 MHz / 32 bit PCI
3.3V and 5V PCI Signaling Voltage
On Board Devices
PCI to PCI Express Bridge
PEX8112 (PLX Technology)
PCI Express Endpoint
Spartan-6 PCI Express Endpoint Block
User configurable FPGA TPMC632-1xR: XC6SLX45T-2 (Xilinx)
TPMC632-2xR: XC6SLX100T-2 (Xilinx)
Configuration Flash TPMC632-1xR: XCF16P (Xilinx)
TPMC632-2xR: XCF32P (Xilinx)
SPI-Flash W25Q32 (Winbond) 32 Mbit (can be used for FPGA configuration)
W25Q32 (Winbond) 32 Mbit (contains TPMC632 FPGA Example)
DDR3 RAM MT41J64M16 or MT41K64M16 (Micron) 64 Meg x 16 Bit
I/O Interface
Number of Channels
TPMC632-x0R: 64 ESD-protected TTL lines
TPMC632-x1R: 32 differential I/O lines
TPMC632-x2R: 32 TTL and 16 differential I/O lines
TPMC632-x3R: 32 M-LVDS I/O lines
TPMC632-x4R: 32 TTL and 16 M-LVDS I/O lines.
TTL signaling voltage level (maximum current:+/-32 mA),
EIA-422/-485 signaling level or
M-LVDS Standard (TIA/EIA-899)
I/O Connector Front I/O HD68 SCSI-3 type Connector
(AMP 787082-7 or compatible)
PMC P14 I/O (64 pin Mezzanine Connector)
Physical Data
Power Requirements Depends on FPGA design
With TPMC632 FPGA Example Design / without external load
typical @ +3.3V DC typical @ +5.0V DC
Output
disable
enable
disable
drive low
TPMC632-x0R 860mA 900mA <5mA 72mA
TPMC632-x1R 860mA 1600mA <5mA <5mA
TPMC632-x2R 860mA 1260mA <5mA 36mA
TPMC632-x3R 640mA 640mA <5mA <5mA
TPMC632-x4R 860mA 980mA <5mA 36mA

TPMC632 User Manual Issue 1.0.6 Page 9 of 49
Temperature Range Operating
Storage -40°C to +85°C -40°C to +85°C
MTBF TPMC632-10R/-20R: 291000 h
TPMC632-11R/-21R: 336000 h
TPMC632-12R/-22R: 311000 h
TPMC632-13R/-23R: 324000 h
TPMC632-14R/-24R: 306000 h
MTBF values shown are based on calculation according to MIL-HDBK-217F and
MIL-HDBK-217F Notice 2; Environment: GB20°C.
The MTBF calculation is based on component FIT rates provided by the component
suppliers. If FIT rates are not available, MIL-HDBK-217F and MIL-HDBK-217F Notice
2 formulas are used for FIT rate calculation.
Humidity 5 – 95 % non-condensing
Weight TPMC632-xxR: 126 g
Table 2-1 : Technical Specification

TPMC632 User Manual Issue 1.0.6 Page 10 of 49
3 Handling and Operation Instruction
ESD Protection3.1
The TPMC632 is sensitive to static electricity. Packing, unpacking
and all other handling of the TPMC632 has to be done in an ESD/EOS
protected Area.
Thermal Considerations3.2
Forced air cooling is recommended during operation. Without forced
air cooling, damage to the device can occur.

TPMC632 User Manual Issue 1.0.6 Page 11 of 49
4 Functional Description
FPGA Block Diagram4.1
Bank 0
Bank 2
Bank 1
Bank 3
Spartan-6
DDR3 Bank
PCIe to PCI Bridge
VCCO = 3.3V
VCCO = 3.3V
VCCO = 1.5V
VCCO = 3.3V
GTP
GPIO:
- DIP-Switch
- LEDs
- I2C
- User LEDs
- Debug Header
SPI-Flash(User)
PlatformFlash
SPI-Flash (Example Design)
Digital I/O
- 64 x Input
- 64 x Output
- 64 x O. Enable
Config
Figure 4-1 : FPGA Block Diagram

TPMC632 User Manual Issue 1.0.6 Page 12 of 49
FPGA4.2
The FPGA is a Spartan-6 LX45T-2 or LX100T-2 FPGA. Each Spartan-6 FPGA in a FGG484 package
provides two Memory Controller Blocks and one Endpoint Block for PCI Express (x1 Linkage).
Spartan-6
Slices
Flip-
Flops
DSP48A1
Slices
Block
RAM (Kb)
CMTs
GTP
Transceivers
LX45T 6.822 54.576 58 2.088 4 4
LX100T
15.822
126.576
180
4.824
6
4
Table 4-1 : TPMC632 FPGA Feature Overview
The board supports JTAG, master serial mode configuration from SPI-Flash or SelectMAP configuration from
a Platform Flash.
The FPGA is equipped with 4 I/O banks and 4 GTP transceivers.
Bank
VCCO
VREF
Signals
Remarks
Bank 0
3.3V
none
dig. I/O Interface
Bank 1
1.5V
0.75V
DDR3 Bank
+GPIO / LED
/Debug
Bank 2 3.3V none dig. I/O Interface +Configuration
Bank 3 3.3V none dig. I/O Interface
GTP Bank
Description
Remarks
GTP101 PCIe Endpoint Block Lane 0
GTP101
not used
Lane 1
GTP123
not used
Lane 0
GTP123 not used Lane 1
Table 4-2 : FPGA Bank Usage
The FPGA’s VCCAUX is connected to the 3.3V supply.

TPMC632 User Manual Issue 1.0.6 Page 13 of 49
Gigabit Transceiver (GTP)4.3
The TPMC632 provides one GTP as Spartan-6 PCI Express Endpoint Block.
SI5338
PCIe Clock
Bridge Clock
Spartan-6
GTP 101
CLK0 GTP 101
CLK1
GTP 123
CLK1
PCIe to PCI Bridge
GTP 123
CLK0
100 MHz 125 MHz
PMC-Connector
PCIeX1Interface
PCI Interface
Figure 4-2 : GTP Block Diagram
GTP
Signal
FPGA
Pins
Connected to
MGT0_101 MGTTX B6 / A6 used for PCI Express
Endpoint Block
MGTRX
D7 / C7
MGT1_101
MGTTX
B8 / A8
not used
MGTRX D9 / C9
MGT0_123
MGTTX
B14 / A14
not used
MGTRX
D13 / C13
MGT1_123 MGTTX B16 / A16 not used
MGTRX
D15 / C15
Table 4-3 : GTP Connections
The GTP clock MGT0_101 (PCI Express Endpoint Block clock reference) of 125 MHz is generated by the
SI5338 low-jitter clock generator.
MGT1_101, MGT0_123 and MGT1_123 are not used on the TPMC632.
GTP
Signal
FPGA
Pins
Connected to
MGT0_101 MGTREFCLK A10 / B10 125 MHz (derived SI5338
clock generator)
MGT1_101 MGTREFCLK C11 / D11 not used
MGT0_123 MGTREFCLK A12 / B12 not used
MGT1_123 MGTREFCLK E12 / F12 not used
Table 4-4 : Multi Gigabit Transceiver Reference Clocks

TPMC632 User Manual Issue 1.0.6 Page 14 of 49
Configuration4.4
The FPGA can be configured by the following sources:
•Platform Flash
•SPI-Flash
•JTAG
The configuration flash can be selected with a DIP-switch; alternatively, JTAG configuration is always
available. For the XILINX Platform Flash configuration the Master SelectMAP/BPI mode with 8bit bus width is
used. The SPI-Flash configuration uses the Master Serial / SPI mode. Both flashes could be programmed
via JTAG; the SPI-Flash uses the indirect SPI programming mode.
To change the TPMC632 programming, JTAG-capable hardware is needed (i.e. the Xilinx Platform Cable
USB II).
On delivery the configuration Platform Flash and the User SPI-Flash (USER Flash) are blank.
A second SPI-Flash (TEWS Flash) is factory programmed with the TPMC632 Platform Example Application.
4.4.1 Selecting the Configuration Source
Besides direct JTAG configuration, the TPMC632 provides two user configuration sources: a platform flash
and a SPI-Flash. Both devices share common pins, so a selection must be made. With the Configuration DIP
switch the Configuration source could be selected.
Set the Configuration DIP Switch S1 to ON, the SPI Flash interface is selected, with Configuration DIP
Switch S1 set to OFF the FPGA will configure from the Platform Flash.
Set the Configuration DIP Switch S2 to ON the SPI Flash A (USER Flash) is selected. Set the Configuration
DIP Switch S2 to OFF the SPI Flash B (TEWS Flash) is selected.
MUX
S1
FPGA
MUX
S2
SPI A
SPI B
XCF
Figure 4-3 : Configuration Source Selection
After configuration the SPI-Flash A is always user accessible, regardless of the switch setting.
Switch
Signal
Description
S1 ON Configure FPGA from SPI Flash
OFF Configure FPGA from Platform Flash
S2 ON SPI Flash A (USER Flash) selected
OFF SPI Flash B (TEWS Flash) selected
Figure 4-4 : Configuration DIP-Switch Settings

TPMC632 User Manual Issue 1.0.6 Page 15 of 49
4.4.2 JTAG
The JTAG-chain is accessible from the JTAG Header, from the Debug Connector or from the PMC-Interface.
These interfaces are connected in parallel, so only one connection should be made to avoid signal
contentions/possible hardware damage.
For direct FPGA configuration, FPGA readback or in-system diagnostics with ChipScope, the JTAG Header
can be used to access the JTAG-chain. The JTAG-chain can be extended to include the TPMC632
configuration CPLD.
XCF16/32
XC6SLX...T PEX8112 XC2C32
TDI TDO TDI TDO TDI TDO TDI TDO
MUX
PMC-Connector
Debug-Connector
J11/J12 X3 X2
S3
JTAG-Header
Figure 4-5 : JTAG-Chain
S3 ON Include configuration CPLD to JTAG chain.
OFF Bypass configuration CPLD (default)
S4 ON Not used
OFF
Figure 4-6 : Configuration DIP-Switch Settings
4.4.3 Board Configuration CPLD
The Board Configuration CPLD (BCC) is factory configured, and handles the basic board setup.
Changing or erase the BCC content leads to an inoperable TPMC632 FPGA configuration.

TPMC632 User Manual Issue 1.0.6 Page 16 of 49
4.4.4 Programming Configuration devices
Both user configuration devices XILINX Platform Flash and SPI Flash could be programmed via JTAG
interface. The second SPI Flash (TEWS Flash) could not be programmed.
For programming the configuration devices the XILINX programming tool iMPACT can be used. An addition
JTAG programming hardware is needed (i.e. the Xilinx Platform Cable USB II).
To use the maximum configuration speed, the TPMC632 must be configured to use the 32 MHz external
master clock as CCLK. To use these configuration feature, the configuration option ‘Enable External Master
Clock’ (-g ExtMasterCclk_en) must be enabled. Without this option, the configuration time for the Spartan6
FPGA exceed the maximum PCI bus setup time.
TPMC632-1xR configuration devices:
SPI Flash: Winbond W25Q32BV or W25Q32FV; 32M; Data Width = 4bit
XILINX Flash/PROM: XCF16P; 16M; parallel mode
TPMC632-2xR configuration devices:
SPI Flash: Winbond W25Q32BV or W25Q32FV; 32M; Data Width = 4bit
XILINX Flash/PROM: XCF32P; 32M; parallel mode

TPMC632 User Manual Issue 1.0.6 Page 17 of 49
Clocking4.5
4.5.1 FPGA Clock Sources
Si5338
PCIe Clock
USER_CLK
MCB_CLK
Spartan-6
GTP 101
CLK0
GTP 101
CLK1
GTP 123
CLK0
GTP 123
CLK1
32MHz
Clock
USER_CCLK 32MHz
Clock
Figure 4-7 : FPGA Clock Sources
The following table lists the available clock sources on the TPMC632:
FPGA Clock-Pin Name FPGA Pin
Number
Source Description
MGTREFCLK0_101 A10 / B10 SI5338 low-jitter clock
generator 125 MHz
PCIe Reference clock
IO_L30P_GCLK1_D13_2 Y13 SI5338 low-jitter clock
generator MCB CLK
62.5 MHz
IO_L29N_GCLK2_2 U12 SI5338 low-jitter clock
generator USER CLK
83.3325 MHz
IO_L30N_GCLK0_USERCCLK_2 AB13 32MHz, 3,3V oscillator Used for external configuration
clock (CCLK)
After configuration this clock
could be used by FPGA design.
Table 4-5 : Available FPGA clocks

TPMC632 User Manual Issue 1.0.6 Page 18 of 49
I/O Interface4.6
Each of the 64 digital IO channels are realized with single ended or differential digital buffers. Each channel
provides an input; output and an output enable signal which is direct connected to the FPGA device.
The IO channels are accessible through the IO Bank 0, Bank 2 and Bank 3 of the Spartan-6 FPGA. The
subsequent table lists required I/O setting for correct interfacing.
Signal Name
Pin
Number
Direction IO Standard
IO
Bank
Drive
[mA]
Slew
Rate
FPGA_IN<0>#
L4
INPUT
LVCMOS33
3
FPGA_IN<1>#
M3
INPUT
LVCMOS33
3
FPGA_IN<2>#
M4
INPUT
LVCMOS33
3
FPGA_IN<3>#
M5
INPUT
LVCMOS33
3
FPGA_IN<4>#
N4
INPUT
LVCMOS33
3
FPGA_IN<5>#
P3
INPUT
LVCMOS33
3
FPGA_IN<6>#
L1
INPUT
LVCMOS33
3
FPGA_IN<7>#
L3
INPUT
LVCMOS33
3
FPGA_IN<8>#
V17
INPUT
LVCMOS33
2
FPGA_IN<9>#
W18
INPUT
LVCMOS33
2
FPGA_IN<10>#
Y17
INPUT
LVCMOS33
2
FPGA_IN<11>#
V15
INPUT
LVCMOS33
2
FPGA_IN<12>#
W17
INPUT
LVCMOS33
2
FPGA_IN<13>#
Y18
INPUT
LVCMOS33
2
FPGA_IN<14>#
V2
INPUT
LVCMOS33
3
FPGA_IN<15>#
Y1
INPUT
LVCMOS33
3
FPGA_IN<16>#
Y14
INPUT
LVCMOS33
2
FPGA_IN<17>#
Y15
INPUT
LVCMOS33
2
FPGA_IN<18>#
B2
INPUT
LVCMOS33
0
FPGA_IN<19>#
C3
INPUT
LVCMOS33
0
FPGA_IN<20>#
A4
INPUT
LVCMOS33
0
FPGA_IN<21>#
D4
INPUT
LVCMOS33
0
FPGA_IN<22>#
H14
INPUT
LVCMOS33
0
FPGA_IN<23>#
D5
INPUT
LVCMOS33
0
FPGA_IN<24>#
E5
INPUT
LVCMOS33
0
FPGA_IN<25>#
E6
INPUT
LVCMOS33
0
FPGA_IN<26>#
A19
INPUT
LVCMOS33
0
FPGA_IN<27>#
F16
INPUT
LVCMOS33
0
FPGA_IN<28>#
A2
INPUT
LVCMOS33
0
FPGA_IN<29>#
D3
INPUT
LVCMOS33
0
FPGA_IN<30>#
B20
INPUT
LVCMOS33
0
FPGA_IN<31>#
F8
INPUT
LVCMOS33
0
FPGA_IN<32>#
H11
INPUT
LVCMOS33
0
FPGA_IN<33>#
H10
INPUT
LVCMOS33
0
FPGA_IN<34>#
G9
INPUT
LVCMOS33
0
FPGA_IN<35>#
G8
INPUT
LVCMOS33
0
FPGA_IN<36>#
B3
INPUT
LVCMOS33
0
FPGA_IN<37>#
A3
INPUT
LVCMOS33
0
FPGA_IN<38>#
A18
INPUT
LVCMOS33
0
FPGA_IN<39>#
B18
INPUT
LVCMOS33
0

TPMC632 User Manual Issue 1.0.6 Page 19 of 49
FPGA_IN<40>#
A17
INPUT
LVCMOS33
0
FPGA_IN<41>#
A5
INPUT
LVCMOS33
0
FPGA_IN<42>#
C5
INPUT
LVCMOS33
0
FPGA_IN<43>#
C4
INPUT
LVCMOS33
0
FPGA_IN<44>#
G13
INPUT
LVCMOS33
0
FPGA_IN<45>#
G15
INPUT
LVCMOS33
0
FPGA_IN<46>#
D17
INPUT
LVCMOS33
0
FPGA_IN<47>#
E16
INPUT
LVCMOS33
0
FPGA_IN<48>#
G16
INPUT
LVCMOS33
0
FPGA_IN<49>#
F17
INPUT
LVCMOS33
0
FPGA_IN<50>#
D18
INPUT
LVCMOS33
0
FPGA_IN<51>#
D19
INPUT
LVCMOS33
0
FPGA_IN<52>#
F15
INPUT
LVCMOS33
0
FPGA_IN<53>#
F9
INPUT
LVCMOS33
0
FPGA_IN<54>#
C19
INPUT
LVCMOS33
0
FPGA_IN<55>#
F7
INPUT
LVCMOS33
0
FPGA_IN<56>#
G11
INPUT
LVCMOS33
0
FPGA_IN<57>#
F14
INPUT
LVCMOS33
0
FPGA_IN<58>#
C18
INPUT
LVCMOS33
0
FPGA_IN<59>#
C17
INPUT
LVCMOS33
0
FPGA_IN<60>#
A20
INPUT
LVCMOS33
0
FPGA_IN<61>#
H12
INPUT
LVCMOS33
0
FPGA_IN<62>#
F10
INPUT
LVCMOS33
0
FPGA_IN<63>#
H13
INPUT
LVCMOS33
0
FPGA_OE<0>#
T15
OUTPUT
LVCMOS33
2
8
SLOW
FPGA_OE<1>#
AB16
OUTPUT
LVCMOS33
2
8
SLOW
FPGA_OE<2>#
AB11
OUTPUT
LVCMOS33
2
8
SLOW
FPGA_OE<3>#
AB8
OUTPUT
LVCMOS33
2
8
SLOW
FPGA_OE<4>#
AB10
OUTPUT
LVCMOS33
2
8
SLOW
FPGA_OE<5>#
AB7
OUTPUT
LVCMOS33
2
8
SLOW
FPGA_OE<6>#
W8
OUTPUT
LVCMOS33
2
8
SLOW
FPGA_OE<7>#
AB9
OUTPUT
LVCMOS33
2
8
SLOW
FPGA_OE<8>#
R8
OUTPUT
LVCMOS33
2
8
SLOW
FPGA_OE<9>#
AB4
OUTPUT
LVCMOS33
2
8
SLOW
FPGA_OE<10>#
AB17
OUTPUT
LVCMOS33
2
8
SLOW
FPGA_OE<11>#
AB15
OUTPUT
LVCMOS33
2
8
SLOW
FPGA_OE<12>#
W12
OUTPUT
LVCMOS33
2
8
SLOW
FPGA_OE<13>#
R1
OUTPUT
LVCMOS33
3
8
SLOW
FPGA_OE<14>#
V1
OUTPUT
LVCMOS33
3
8
SLOW
FPGA_OE<15>#
T7
OUTPUT
LVCMOS33
2
8
SLOW
FPGA_OE<16>#
U6
OUTPUT
LVCMOS33
2
8
SLOW
FPGA_OE<17>#
AB19
OUTPUT
LVCMOS33
2
8
SLOW
FPGA_OE<18>#
C1
OUTPUT
LVCMOS33
3
8
SLOW
FPGA_OE<19>#
M8
OUTPUT
LVCMOS33
3
8
SLOW
FPGA_OE<20>#
AA18
OUTPUT
LVCMOS33
2
8
SLOW
FPGA_OE<21>#
AB18
OUTPUT
LVCMOS33
2
8
SLOW
FPGA_OE<22>#
U14
OUTPUT
LVCMOS33
2
8
SLOW
FPGA_OE<23>#
W14
OUTPUT
LVCMOS33
2
8
SLOW
FPGA_OE<24>#
Y16
OUTPUT
LVCMOS33
2
8
SLOW
FPGA_OE<25>#
U16
OUTPUT
LVCMOS33
2
8
SLOW
FPGA_OE<26>#
V13
OUTPUT
LVCMOS33
2
8
SLOW

TPMC632 User Manual Issue 1.0.6 Page 20 of 49
FPGA_OE<27>#
W13
OUTPUT
LVCMOS33
2
8
SLOW
FPGA_OE<28>#
U1
OUTPUT
LVCMOS33
3
8
SLOW
FPGA_OE<29>#
AA1
OUTPUT
LVCMOS33
3
8
SLOW
FPGA_OE<30>#
U13
OUTPUT
LVCMOS33
2
8
SLOW
FPGA_OE<31>#
AA2
OUTPUT
LVCMOS33
3
8
SLOW
FPGA_OE<32>#
W6
OUTPUT
LVCMOS33
2
8
SLOW
FPGA_OE<33>#
W4
OUTPUT
LVCMOS33
3
8
SLOW
FPGA_OE<34>#
R3
OUTPUT
LVCMOS33
3
8
SLOW
FPGA_OE<35>#
T6
OUTPUT
LVCMOS33
3
8
SLOW
FPGA_OE<36>#
D1
OUTPUT
LVCMOS33
3
8
SLOW
FPGA_OE<37>#
V3
OUTPUT
LVCMOS33
3
8
SLOW
FPGA_OE<38>#
H5
OUTPUT
LVCMOS33
3
8
SLOW
FPGA_OE<39>#
J6
OUTPUT
LVCMOS33
3
8
SLOW
FPGA_OE<40>#
F2
OUTPUT
LVCMOS33
3
8
SLOW
FPGA_OE<41>#
G1
OUTPUT
LVCMOS33
3
8
SLOW
FPGA_OE<42>#
H2
OUTPUT
LVCMOS33
3
8
SLOW
FPGA_OE<43>#
H1
OUTPUT
LVCMOS33
3
8
SLOW
FPGA_OE<44>#
U3
OUTPUT
LVCMOS33
3
8
SLOW
FPGA_OE<45>#
U4
OUTPUT
LVCMOS33
3
8
SLOW
FPGA_OE<46>#
T3
OUTPUT
LVCMOS33
3
8
SLOW
FPGA_OE<47>#
P6
OUTPUT
LVCMOS33
3
8
SLOW
FPGA_OE<48>#
R7
OUTPUT
LVCMOS33
3
8
SLOW
FPGA_OE<49>#
M7
OUTPUT
LVCMOS33
3
8
SLOW
FPGA_OE<50>#
U8
OUTPUT
LVCMOS33
2
8
SLOW
FPGA_OE<51>#
M2
OUTPUT
LVCMOS33
3
8
SLOW
FPGA_OE<52>#
T4
OUTPUT
LVCMOS33
3
8
SLOW
FPGA_OE<53>#
V5
OUTPUT
LVCMOS33
3
8
SLOW
FPGA_OE<54>#
K1
OUTPUT
LVCMOS33
3
8
SLOW
FPGA_OE<55>#
N1
OUTPUT
LVCMOS33
3
8
SLOW
FPGA_OE<56>#
P5
OUTPUT
LVCMOS33
3
8
SLOW
FPGA_OE<57>#
N6
OUTPUT
LVCMOS33
3
8
SLOW
FPGA_OE<58>#
K2
OUTPUT
LVCMOS33
3
8
SLOW
FPGA_OE<59>#
N7
OUTPUT
LVCMOS33
3
8
SLOW
FPGA_OE<60>#
P7
OUTPUT
LVCMOS33
3
8
SLOW
FPGA_OE<61>#
P1
OUTPUT
LVCMOS33
3
8
SLOW
FPGA_OE<62>#
K5
OUTPUT
LVCMOS33
3
8
SLOW
FPGA_OE<63>#
J4
OUTPUT
LVCMOS33
3
8
SLOW
FPGA_OUT<0>#
Y3
OUTPUT
LVCMOS33
3
8
SLOW
FPGA_OUT<1>#
AB14
OUTPUT
LVCMOS33
2
8
SLOW
FPGA_OUT<2>#
AB12
OUTPUT
LVCMOS33
2
8
SLOW
FPGA_OUT<3>#
AA4
OUTPUT
LVCMOS33
2
8
SLOW
FPGA_OUT<4>#
N3
OUTPUT
LVCMOS33
3
8
SLOW
FPGA_OUT<5>#
W3
OUTPUT
LVCMOS33
3
8
SLOW
FPGA_OUT<6>#
AA10
OUTPUT
LVCMOS33
2
8
SLOW
FPGA_OUT<7>#
Y6
OUTPUT
LVCMOS33
2
8
SLOW
FPGA_OUT<8>#
M6
OUTPUT
LVCMOS33
3
8
SLOW
FPGA_OUT<9>#
L6
OUTPUT
LVCMOS33
3
8
SLOW
FPGA_OUT<10>#
K4
OUTPUT
LVCMOS33
3
8
SLOW
FPGA_OUT<11>#
K3
OUTPUT
LVCMOS33
3
8
SLOW
FPGA_OUT<12>#
P2
OUTPUT
LVCMOS33
3
8
SLOW
FPGA_OUT<13>#
T1
OUTPUT
LVCMOS33
3
8
SLOW
FPGA_OUT<14>#
J3
OUTPUT
LVCMOS33
3
8
SLOW