Tews Technologies TPMC634 Series User manual

The Embedded I/O Company
TPMC634
Re-Configurable FPGA with
64 TTL I/O / 32 Differential I/O
Version 1.0
User Manual
Issue 1.0.1
April 2018
TEWS TECHNOLOGIES GmbH
Am Bahnhof 7
25469 Halstenbek, Germany
Phone: [phone]
Fax: [phone]
e-mail: [email protected]
www.tews.com

TPMC634 User Manual Issue 1.0.1 Page 2 of 93
TPMC634-10R
Re-Configurable FPGA with 64 TTL I/O
TPMC634-11R
Re-Configurable FPGA with 32 Differential
EIA-422 / EIA-485 I/O
TPMC634-12R
Re-Configurable FPGA with 16 Differential
EIA-422 / EIA-485 I/O and 32 TTL I/O
TPMC634-13R
Re-Configurable FPGA with 32 Differential
M-LVDS I/O
TPMC634-14R
Re-Configurable FPGA with 16 Differential
M-LVDS I/O and 32 TTL I/O
This document contains information, which is
proprietary to TEWS TECHNOLOGIES GmbH. Any
reproduction without written permission is forbidden.
TEWS TECHNOLOGIES GmbH has made any
effort to ensure that this manual is accurate and
complete. However TEWS TECHNOLOGIES GmbH
reserves the right to change the product described
in this document at any time without notice.
TEWS TECHNOLOGIES GmbH is not liable for any
damage arising out of the application or use of the
device described herein.
Style Conventions
Hexadecimal characters are specified with prefix 0x,
i.e. 0x029E (that means hexadecimal value 029E).
For signals on hardware products, an ‚Active Low’ is
represented by the signal name with # following, i.e.
IP_RESET#.
Access terms are described as:
W Write Only
R Read Only
R/W Read/Write
R/C Read/Clear
R/S Read/Set
2018 by TEWS TECHNOLOGIES GmbH
All trademarks mentioned are property of their respective owners.

TPMC634 User Manual Issue 1.0.1 Page 3 of 93
Issue Description Date
1.0.0 Initial Issue April 2015
1.0.1 Order Option Description unified April 2018

TPMC634 User Manual Issue 1.0.1 Page 4 of 93
Table of Contents
1PRODUCT DESCRIPTION ...........................................................................................9
2TECHNICAL SPECIFICATION ...................................................................................11
3HANDLING AND OPERATION INSTRUCTIONS.......................................................13
ESD Protection..............................................................................................................................133.1
User FPGA Power Dissipation Limit...........................................................................................133.2
I/O Interface Installation ...............................................................................................................133.3
Default TTL I/O Line States ..........................................................................................................133.4
Pre-Installed User FPGA Example...............................................................................................143.5
4PCI TARGET INTERFACE .........................................................................................15
PCI Configuration Space (PCI Header).......................................................................................154.1
PCI BAR Overview ........................................................................................................................164.2
PCI Configuration EEPROM Parameter......................................................................................174.3
PCI Clock Frequency....................................................................................................................184.4
PCI Access Times.........................................................................................................................184.5
5ADDRESS MAPS........................................................................................................19
PCI Target Register Space...........................................................................................................195.1
5.1.1 Local Bus Interface Register (0x90) .......................................................................................20
5.1.1 Configuration EEPROM Register (0xB0)................................................................................21
5.1.2 Interrupt Enable Register (0xC0)............................................................................................22
5.1.1 Interrupt Status Register (0xC4).............................................................................................23
5.1.2 Interrupt Configuration Register (0xC8)..................................................................................24
5.1.3 User FPGA Configuration Control/Status Register (0xD0).....................................................24
5.1.4 User FPGA Configuration Data Register (Slave SelectMAP) (0xD4).....................................25
5.1.1 ISP Control Register (SPI) (0xE0)..........................................................................................26
5.1.2 ISP Configuration Register (SPI) (0xE4) ................................................................................26
5.1.3 ISP Command Register (SPI) (0xE8).....................................................................................26
5.1.4 ISP Status Register (SPI) (0xEC)...........................................................................................27
5.1.1 Control & Status Register (0xF0)............................................................................................28
5.1.2 Firmware Version Register (0xFC).........................................................................................28
In-System Programming Space...................................................................................................285.2
User Space(s) ................................................................................................................................295.3
6USER PROGRAMMABLE FPGA ...............................................................................30
FPGA Part ......................................................................................................................................306.1
I/O Bank Supply & Supported I/O Standards .............................................................................306.2
User FPGA I/O Signal & Pin Description ....................................................................................306.3
6.3.1 Local Bus Interface Signals ....................................................................................................30
6.3.2 I/O Interface Signals ...............................................................................................................32
6.3.3 Other User Signals..................................................................................................................40
6.3.4 Reserved FPGA I/O Pins........................................................................................................40
User FPGA Power Dissipation Limit...........................................................................................416.4

TPMC634 User Manual Issue 1.0.1 Page 5 of 93
7USER PROGRAMMABLE FPGA CONFIGURATION................................................42
User FPGA Configuration Options..............................................................................................427.1
FPGA Configuration from SPI Flash...........................................................................................427.2
7.2.1 Auto-Configuration at Power-Up.............................................................................................42
7.2.2 SW Controlled Re-Configuration ............................................................................................42
7.2.3 SPI Flash Preparation.............................................................................................................43
7.2.4 FPGA Configuration Time.......................................................................................................43
FPGA Configuration via PCI/Software........................................................................................447.3
7.3.1 Configuration Data Files .........................................................................................................44
7.3.2 Direct FPGA Programming.....................................................................................................46
FPGA Configuration via JTAG Header........................................................................................477.4
8SPI FLASH PROGRAMMING.....................................................................................49
SPI Flash Notes.............................................................................................................................498.1
8.1.1 SPI Flash Device Type ...........................................................................................................49
8.1.2 SPI Flash Programming Options............................................................................................49
8.1.3 SPI Flash Non-Volatile QE Bit ................................................................................................49
8.1.4 Xilinx ISE / BitGen Options.....................................................................................................50
SPI Flash Programming via PCI/Software..................................................................................508.2
8.2.1 SPI Flash Program Data.........................................................................................................50
8.2.2 SPI Flash Instructions.............................................................................................................51
8.2.3 Steps for SPI Flash Chip Erase Operation.............................................................................51
8.2.4 Steps for SPI Flash Sector Erase Operation..........................................................................52
8.2.5Steps for SPI Flash Program Operation.................................................................................52
8.2.6 Steps for SPI Flash Read Operation ......................................................................................53
8.2.7 Steps for setting the SPI Flash Non-Volatile QE Bit...............................................................54
SPI Flash Programming via JTAG Header .................................................................................558.3
8.3.1 MCS Programming File Generation........................................................................................55
8.3.2 SPI Flash Programming..........................................................................................................57
9LOCAL BUS INTERFACE ..........................................................................................62
Local Bus Interface Notes............................................................................................................629.1
Local Bus Cycle Description .......................................................................................................629.2
9.2.1 Local Bus Master Abort (Local Bus Time-Out).......................................................................63
9.2.2 Local Bus Target Error............................................................................................................63
Local Bus Signal Description......................................................................................................649.3
Local Bus Interface Timing..........................................................................................................669.4
Local Bus Signal Protocol Example Diagrams..........................................................................679.5
10 INTERRUPTS..............................................................................................................69
Interrupt Sources..........................................................................................................................6910.1
Interrupt Handling.........................................................................................................................6910.2
10.2.1 SPI Flash In-System Programming Interrupts........................................................................69
10.2.2 Local Bus User Interrupt.........................................................................................................70
10.2.3 Local Bus Error Interrupt.........................................................................................................70
11 LEDS...........................................................................................................................71
12 JTAG HEADER...........................................................................................................72
13 BOARD HW-CONFIGURATION.................................................................................74
Readable DIP-Switch ....................................................................................................................7413.1
TTL I/O Pull-Resistor Reference..................................................................................................7413.2

TPMC634 User Manual Issue 1.0.1 Page 6 of 93
14 I/O INTERFACE ..........................................................................................................75
General I/O Interface Description................................................................................................7514.1
14.1.1 Single-Ended I/O Line Interface..............................................................................................75
14.1.2 Differential I/O Line Interface..................................................................................................77
I/O Connectors ..............................................................................................................................7814.2
14.2.1 Front-I/O Connector Part Number ..........................................................................................78
14.2.2 Rear-I/O Connector Part Number...........................................................................................78
I/O Line Signal Level.....................................................................................................................7814.3
Front-I/O Pin Assignment.............................................................................................................7914.4
Rear-I/O Pin Assignment..............................................................................................................8014.5
15 APPENDIX A: USER FPGA PORT MAP....................................................................81
16 APPENDIX B: USER FPGA CONSTRAINT FILE.......................................................82
17 APPENDIX C: PRE-INSTALLED USER FPGA EXAMPLE APPLICATION..............89
User FPGA Example Register Map..............................................................................................8917.1
User FPGA Example Register Description.................................................................................9017.2
17.2.1 PMC I/O Input Register (Lower) (0x00)..................................................................................90
17.2.2 PMC I/O Input Register (Upper) (0x04)..................................................................................90
17.2.3 PMC I/O Output Register (Lower) (0x08) ...............................................................................90
17.2.4 PMC I/O Output Register (Upper) (0x0C)...............................................................................91
17.2.5 PMC I/O Output Enable Register (Lower) (0x10)...................................................................91
17.2.6 PMC I/O Output Enable Register (Upper) (0x14)...................................................................91
17.2.7 PMC I/O Rising Edge Interrupt Enable Register (0x20).........................................................91
17.2.8 PMC I/O Falling Edge Interrupt Enable Register (0x24).........................................................92
17.2.9 PMC I/O Interrupt Status Register (0x28)...............................................................................92
17.2.10 Clock Counter Control Register (0xE0) ..................................................................................92
17.2.11 Clock Counter Register – Local Bus Clock (0xE4).................................................................93
17.2.12 Clock Counter Register – Auxiliary Clock (0xE8)...................................................................93
17.2.13 Clock Counter Register – Baud Rate Clock (0xEC)...............................................................93
17.2.14 General R/W Test Register (0xF8).........................................................................................93
17.2.15 Version Register (0xFC) .........................................................................................................93

TPMC634 User Manual Issue 1.0.1 Page 7 of 93
List of Figures
FIGURE 1-1 : TPMC634 BLOCK DIAGRAM ..................................................................................................10
FIGURE 4-1 : PCI HEADER............................................................................................................................15
FIGURE 9-1 : LOCAL BUS SIGNAL PROTOCOL EXAMPLE DIAGRAMS ...................................................68
FIGURE 11-1: LED LOCATION......................................................................................................................71
FIGURE 12-1: JTAG HEADER PIN ORDER ..................................................................................................72
FIGURE 12-1: JTAG HEADER LOCATION....................................................................................................73
FIGURE 14-1: SINGLE-ENDED I/O LINE INTERFACE.................................................................................76
FIGURE 14-2: DIFFERENTIAL I/O LINE INTERFACE...................................................................................77
FIGURE 14-3: FRONT PANEL I/O CONNECTOR NUMBERING..................................................................78
List of Tables
TABLE 2-1 : TECHNICAL SPECIFICATION...................................................................................................12
TABLE 4-1 : TPMC634 PCI BAR OVERVIEW................................................................................................16
TABLE 4-2 : PCI CONFIGURATION EEPROM MAP.....................................................................................17
TABLE 4-3 : APPROXIMATE PCI ACCESS TIMES.......................................................................................18
TABLE 5-1 : PCI TARGET REGISTER SPACE..............................................................................................19
TABLE 5-2 : LOCAL BUS INTERFACE REGISTER.......................................................................................21
TABLE 5-3 : CONFIGURATION EEPROM REGISTER .................................................................................21
TABLE 5-4 : INTERRUPT ENABLE REGISTER.............................................................................................22
TABLE 5-5 : INTERRUPT STATUS REGISTER.............................................................................................23
TABLE 5-6 : INTERRUPT CONFIGURATION REGISTER ............................................................................24
TABLE 5-7 : USER FPGA CONFIGURATION CONTROL/STATUS REGISTER..........................................25
TABLE 5-8 : USER FPGA CONFIGURATION DATA REGISTER (SLAVE SELECTMAP) ...........................25
TABLE 5-9 : ISP CONTROL REGISTER (SPI)...............................................................................................26
TABLE 5-10: ISP CONFIGURATION REGISTER (SPI).................................................................................26
TABLE 5-11: ISP COMMAND REGISTER (SPI) ............................................................................................27
TABLE 5-12: ISP STATUS REGISTER (SPI).................................................................................................27
TABLE 5-13: DIP-SWITCH REGISTER..........................................................................................................28
TABLE 5-14: VERSION REGISTER...............................................................................................................28
TABLE 5-15: USER SPACE OVERVIEW .......................................................................................................29
TABLE 6-1 : USER FPGA RESOURCES......................................................................................................30
TABLE 6-2 : LOCAL BUS INTERFACE SIGNALS (FPGA PARAMETERS)..................................................32
TABLE 6-3 : I/O INTERFACE SIGNALS (FPGA PARAMETERS)..................................................................38
TABLE 6-4 : FPGA I/O INTERFACE SIGNAL DESCRIPTION.......................................................................38
TABLE 6-5 : FPGA I/O INTERFACE SIGNAL USAGE FOR TPMC634 VARIANTS......................................39
TABLE 6-6 : OTHER USER SIGNALS............................................................................................................40
TABLE 6-7 : RESERVED FPGA I/O PINS......................................................................................................41
TABLE 7-1 : ESTIMATED FPGA CONFIGURATION TIME ...........................................................................43
TABLE 9-1 : LOCAL BUS SIGNAL DESCRIPTION........................................................................................66
TABLE 9-2 : LOCAL BUS INTERFACE TIMING.............................................................................................66

TPMC634 User Manual Issue 1.0.1 Page 8 of 93
TABLE 11-1: ON-BOARD LEDS.....................................................................................................................71
TABLE 12-1: JTAG HEADER PART NUMBER ..............................................................................................72
TABLE 12-2: JTAG HEADER PIN ASSIGNMENT..........................................................................................72
TABLE 13-1: 4-POS. ROTARY SWITCH CONFIGURATION ........................................................................74
TABLE 14-1 : FRONT I/O CONNECTOR PART NUMBER.............................................................................78
TABLE 14-2: REAR I/O CONNECTOR PART NUMBER ...............................................................................78
TABLE 14-3: I/O LINE SIGNAL LEVEL...........................................................................................................78
TABLE 14-4: TPMC634 FRONT I/O PIN ASSIGNMENT ...............................................................................79
TABLE 14-5: TPMC634 REAR I/O PIN ASSIGNMENT..................................................................................80
TABLE 17-1 : USER FPGA EXAMPLE REGISTER MAP...............................................................................90
TABLE 17-2: PMC I/O INPUT REGISTER (LOWER) (0X00)..........................................................................90
TABLE 17-3: PMC I/O INPUT REGISTER (UPPER) (0X04)...........................................................................90
TABLE 17-4: PMC I/O OUTPUT REGISTER (LOWER) (0X08)......................................................................91
TABLE 17-5: PMC I/O OUTPUT REGISTER (UPPER) (0X0C) ......................................................................91
TABLE 17-6: PMC I/O OUTPUT ENABLE REGISTER (LOWER) (0X10).......................................................91
TABLE 17-7: PMC I/O OUTPUT ENABLE REGISTER (UPPER) (0X14)........................................................91
TABLE 17-8: PMC I/O RISING EDGE INTERRUPT ENABLE REGISTER (0X20).........................................91
TABLE 17-9: PMC I/O FALLING EDGE INTERRUPT ENABLE REGISTER (0X24) ......................................92
TABLE 17-10: PMC I/O INTERRUPT STATUS REGISTER (0X28)................................................................92
TABLE 17-11: CLOCK COUNTER CONTROL REGISTER (0XE0)................................................................92
TABLE 17-12: CLOCK COUNTER REGISTER – LOCAL BUS CLOCK (0XE4).............................................93
TABLE 17-13: CLOCK COUNTER REGISTER – AUXILIARY CLOCK (0XE8) ..............................................93
TABLE 17-14: CLOCK COUNTER REGISTER – BAUD RATE CLOCK (0XEC)............................................93
TABLE 17-15: GENERAL R/W TEST REGISTER (0XF8)...............................................................................93
TABLE 17-16: VERSION REGISTER (0XFC)..................................................................................................93

TPMC634 User Manual Issue 1.0.1 Page 9 of 93
1 Product Description
The TPMC634 is a standard single-width 32 bit PMC module providing a user programmable FPGA with
front-I/O and P14 rear-I/O.
The TPMC634 provides a 32 bit 33MHz PCI Target interface. A dedicated (FPGA based) PCI Target Chip is
used as a target bridge between the PCI bus and an on-board off-chip local bus. The local bus signals are
available at User FPGA I/O pins, so the User FPGA logic design adapts to the local bus and is spared from
implementing a PCI interface adaption.
The user programmable FPGA is a Xilinx Spartan-6 part number XC6SLX25-2-FGG484I.
The User FPGA is typically auto-configured by an on-board serial SPI Flash device after power-up. The
serial SPI Flash device is in-system programmable via the PCI bus or via the JTAG header (indirectly via
FPGA I/O pins using the Xilinx iMPACT software and platform cable programmer hardware).
Other options for volatile FPGA configuration are via JTAG (JTAG header) or in-system direct FPGA
programming via the PCI bus.
An in-system debugging option is available via the on-board JTAG header. After power-up, the FPGA always
attempts auto-configuration from the on-board SPI Flash.
There are five order options which are differing regarding the I/O interface:
•The TPMC634-10R provides 64 single-ended TTL I/O lines
•The TPMC634-11R provides 32 differential EIA-422 / EIA-485 I/O lines
•The TPMC634-12R provides a mix of 16 differential EIA-422 / EIA-485 I/O lines and 32 single-
ended TTL I/O lines
•The TPMC634-13R provides 32 differential M-LVDS I/O lines
•The TPMC634-14R provides a mix of 16 differential M-LVDS I/O lines and 32 single-ended TTL I/O
lines
The I/O line transmitters can be enabled or disabled per I/O line. The I/O line receivers are always enabled,
so each I/O line level can always be monitored.
All I/O lines are ESD protected.
All I/O lines are available on both a 68 pin front-I/O connector and on the 64 pin P14 rear-I/O connector.
The TPMC634 I/O interface circuit and I/O connector pin assignment is compatible to the former TPMC630.

TPMC634 User Manual Issue 1.0.1 Page 10 of 93
Figure 1-1 : TPMC634 Block Diagram

TPMC634 User Manual Issue 1.0.1 Page 11 of 93
2 Technical Specification
PMC Interface
Mechanical Interface
PCI Mezzanine Card (PMC) Interface confirming to IEEE
P1386/P1386.1
Single Size
Electrical Interface
PCI Rev. 3.0 compatible
33 MHz / 32 bit PCI
Minimum PCI Clock Frequency is 8 MHz
3.3V and 5V PCI Signaling Voltage
On-Board Devices
PCI Target Chip (FPGA) Lattice MachXO2 LCMXO2-4000HE-5BG320I
User Programmable FPGA Xilinx Spartan-6 XC6SLX25-2FGG484I
EEPROM M93C56WMN6 (or compatible)
SPI Flash Winbond W25Q32FVZPIG (W25Q32BV compatible)
I/O Interface
I/O Channels TPMC634-10R: 64 TTL I/O
TPMC634-11R: 32 RS422/485 Differential I/O
TPMC634-12R: 32 TTL I/O and 16 RS422/485 Differential I/O
TPMC634-13R: 32 M-LVDS Differential I/O
TPMC634-14R: 32 TTL I/O and 16 M-LVDS Differential I/O
I/O Transceiver TPMC634-10R: 74LVT126 (or compatible)
TPMC634-11R: MAX3078E (or compatible)
TPMC634-12R: 74LVT126 & MAX3078E (or compatible)
TPMC634-13R: SN65MLVD206 (or compatible)
TPMC634-14R: 74LVT126 & SN65MLVD206 (or compatible)
I/O Connector Front I/O HD68 SCSI-3 Type Connector
PMC P14 I/O (64 pin Mezzanine Connector)
Physical Data
Power Requirements The +3.3V and ±12V from the PMC connector are not used.
On-board I/O termination resistor load included, User FPGA
example application running, without any external I/O load:
TPMC634-10R: up to 180mA typical @ +5V DC
TPMC634-11R: up to 620mA typical @ +5V DC
TPMC634-12R: up to 410mA typical @ +5V DC
TPMC634-13R: up to 300mA typical @ +5V DC (estimation)
TPMC634-14R: up to 150mA typical @ +5V DC (estimation)
Approximate values with external load on all I/O channels:
TPMC634-10R: 1.0A @ +5V DC
TPMC634-11R: 1.0A @ +5V DC
TPMC634-12R: 1.0A @ +5V DC
TPMC634-13R: 0.6A @ +5V DC (estimation)
TPMC634-14R: 0.8A @ +5V DC (estimation)
Temperature Range Operating
Storage -40°C to +85°C -40°C to +85°C

TPMC634 User Manual Issue 1.0.1 Page 12 of 93
MTBF
TPMC634-10R: 423000 h
TPMC634-11R: 440000 h
TPMC634-12R: 431000 h
TPMC634-13R: 429000 h
TPMC634-14R: 425000 h
MTBF values shown are based on calculation according to MIL-HDBK-217F and
MIL-HDBK-217F Notice 2; Environment: GB20°C.
The MTBF calculation is based on component FIT rates provided by the
component suppliers. If FIT rates are not available, MIL-HDBK-217F and
MIL-HDBK-217F Notice 2 formulas are used for FIT rate calculation.
Humidity
5 – 95 % non-condensing
Weight
84 g (all variants)
Table 2-1 : Technical Specification

TPMC634 User Manual Issue 1.0.1 Page 13 of 93
3 Handling and Operation Instructions
ESD Protection3.1
The PMC module is sensitive to static electricity. Packing, unpacking
and all other module handling has to be done with the appropriate
care.
User FPGA Power Dissipation Limit3.2
The absolute maximum junction temperature of the Xilinx Spartan-6
XC6SLX25-2FGG484I is +125°C and must not be exceeded.
The recommended maximum junction temperature of the Xilinx
Spartan-6 XC6SLX25-2FGG484I is +100°C and should not be
exceeded.
The user must use appropriate design tools to ensure that the
Spartan-6 FPGA junction temperature stays within the given limits
for the actual User FPGA logic design and environment/system
conditions (ambient temperature, air flow).
I/O Interface Installation3.3
The TPMC634 I/O interface signals are available on both the 68 pin
front-I/O connector and the 64 pin P14 rear-I/O connector.
Only one TPMC634 I/O interface must be used / installed at a time,
either the front-I/O interface or the rear-I/O interface!
Do not use / install both the front I/O interface and the rear I/O
interface at the same time!
Default TTL I/O Line States3.4
The TPMC634 I/O interface transceivers are disabled by default.
However, the TTL I/O lines have on-board pull-to-reference resistors
right at the PMC I/O interface. Hence, TTL I/O lines will show a valid
logic level after power-up.
The common default reference level for all TTL I/O lines is
configurable by the on-board rotary switch (3.3V, 5V or GND).

TPMC634 User Manual Issue 1.0.1 Page 14 of 93
Pre-Installed User FPGA Example3.5
The TPMC634 comes with a factory default User FPGA Example
application stored in the on-board SPI Flash.
After power-up, the Spartan-6 User FPGA is automatically configured
with the User FPGA Example application.
The User FPGA Example application provides registers for enabling
the TPMC634 I/O line drivers!
Care must be taken, not to write accidently data to the registers
implemented by the User FPGA Example application!
A brief description of the User FPGA Example register functions is
appended to this user manual.

TPMC634 User Manual Issue 1.0.1 Page 15 of 93
4 PCI Target Interface
PCI Configuration Space (PCI Header)4.1
PCI
CFG
Reg.
Offs.
Description Config.
by
EEP
Pre-
Configured
Values
31 24 23 16 15 8 7 0
0x00 Device ID
(TPMC634) Vendor ID (TEWS Technologies) Y 0x027A1498
0x04 Status Command N --
0x08 Class Code Revision ID Y 0x11800001
0x0C BIST
not supported Header Type Latency Timer not supported Cache Line Size not supported N 0
0x10 Base Address Register 0 (BAR0)
PCI Target Register Space (256 Byte) N 0xFFFFFF00 (256 Byte)
0x14 Base Address Register 1 (BAR1)
In-System Programming Space (SPI Flash) (256 Byte) N 0xFFFFFF00 (256 Byte)
0x18 Base Address Register 2 (BAR2) [optional] User Space 0 (max 16 Mbyte)
Programmable via Configuration EEPROM Y 0xFFFC0000
(256 Kbyte)
0x1C Base Address Register 3 (BAR3) [optional]
User Space 1 (max 16 Mbyte)
Programmable via Configuration EEPROM Y 0x00000000
0x20 Base Address Register 4 (BAR4) [optional] User Space 2 (max 16 Mbyte)
Programmable via Configuration EEPROM Y 0x00000000
0x24
Base Address Register 5 (BAR5)
[optional]
User Space 3 (max 16 Mbyte)
Programmable via Configuration EEPROM Y 0x00000000
0x28 PCI CardBus Information Structure Pointer
not supported N 0
0x2C Subsystem ID
See below Subsystem Vendor ID (TEWS Technologies) Y s.b. | 0x1498
0x30
Base Address for Local Expansion ROM
not supported N 0
0x34 Reserved New Cap. Ptr. N 0
0x38
Reserved
N
-
0x3C Max_Lat Min_Gnt Interrupt Pin Interrupt Line N 0x00000100
0x40
-
0xFF Reserved N 0
Subsystem-ID: TPMC634-10R = 0x000A, TPMC634-11R = 0x000B, TPMC634-12R = 0x000C
TPMC634-13R = 0x000D, TPMC634-14R = 0x000E
Figure 4-1 : PCI Header

TPMC634 User Manual Issue 1.0.1 Page 16 of 93
PCI BAR Overview4.2
PCI
BAR PCI Space Size (Byte) Prefetch- able
Port
Width
(Bit)
Endian
Mode Description
0 MEM 256 No 32 Little PCI Target Register
Space
1 MEM 256 No 32 Little In-System Programming Space
(SPI Flash)
2 MEM 256K
by default,
16M max No 32 Little Optional User Space 0
Enabled by factory
default
3 MEM Disabled
by default,
16M max
No 32 Little Optional User Space 1
Disabled by factory
default
4 MEM Disabled by default,
16M max No 32 Little Optional User Space 2
Disabled by factory
default
5 MEM Disabled by default,
16M max No 32 Little Optional User Space 3
Disabled by factory
default
Table 4-1 : TPMC634 PCI BAR Overview
PCI BAR 0 & 1 are always enabled and are not configurable by the user.
PCI BARs 2 … 5 are optional user spaces for accessing the User FPGA on the local bus. PCI BARs 2 … 5
are configurable (enable, size) via the Configuration EEPROM.
From the optional user spaces, only PCI BAR2 (user space 0) is enabled with a 256 KB size per factory
default. This space implements the registers of the user FPGA example application which comes with the
TPMC634 (a brief description of the user FPGA example is appended to this user manual). PCI BARs 3-5
are disabled per factory default.
Note that all TPMC634 PCI BAR spaces are operating in little endian mode only.
For PCI BAR 1 PCI read and write commands are terminated directly (within 16 PCI clock cycles) with
Disconnect-with-Data.
For PCI BARs 0 & 2-5 a FIFO (up to 16 PCI commands) is used to pass read/write parameters to/from the
PCI bus. PCI write commands are handled as single-cycle posted writes. PCI read commands are handled
as single-cycle delayed reads. Incoming writes are accepted and queued to the FIFO. Delayed reads are
handled one at a time queued to the FIFO. PCI commands are retried when the FIFO is full.

TPMC634 User Manual Issue 1.0.1 Page 17 of 93
PCI Configuration EEPROM Parameter4.3
The following PCI configuration space parameters are loaded from an on-board serial EEPROM after PCI
reset.
Serial
EEPROM
Word
Offset
Parameter
Default
Value
(Default
EEPROM)
Fallback
Value
(Invalid
EEPROM)
PCI Configuration Space Parameter
0x00 Device ID 0x027A 0x027A
0x01 Vendor ID 0x1498 0x1498
0x02 Class Code 0x1180 0x1180
0x03 Class Code / PCI Rev 0x0001 0x0001
0x04 Subsystem ID Card
Variant 0x0000
0x05 Subsystem Vendor ID 0x1498 0x0000
0x06 Reserved - -
0x07 Reserved - -
0x08 MSW PCI BAR 2 / User Space 0 0xFFFC 0x0000
0x09 LSW PCI BAR 2 / User Space 0 0x0000 0x0000
0x0A MSW PCI BAR 3 / User Space 1 0x0000 0x0000
0x0B LSW PCI BAR 3 / User Space 1 0x0000 0x0000
0x0C MSW PCI BAR 4 / User Space 2 0x0000 0x0000
0x0D LSW PCI BAR 4 / User Space 2 0x0000 0x0000
0x0E MSW PCI BAR 5 / User Space 3 0x0000 0x0000
0x0F LSW PCI BAR 5 / User Space 3 0x0000 0x0000
Table 4-2 : PCI Configuration EEPROM Map
If any of the first two EEPROM words is read as 0xFFFF the EEPROM data is discarded and the listed
parameters are set to their fallback values. If both first EEPROM words are differing from 0xFFFF the listed
parameters are set according to the EEPROM content.
Note that for an invalid/blank EEPROM, the card is still identified as a TPMC634, but there is no valid card
variant coding and there also is no PCI BAR enabled for the optional user space.
If the User FPGA logic design only requires a single PCI BAR space and not more than 256 Kbyte address
space, there usually is no need to alter the factory default Configuration EEPROM content.
See the Configuration EEPROM Register description for details about how to read from or write to the
Configuration EEPROM.

TPMC634 User Manual Issue 1.0.1 Page 18 of 93
PCI Clock Frequency4.4
The TPMC634 provides a 32 bit 33 MHz PCI Target Interface. The minimum PCI clock frequency is 8 MHz
(lower PCI clock frequencies are not supported).
PCI Access Times4.5
The following table shows the approximate TPMC634 PCI access times. Two PCI bus idle cycles after each
PCI access (and between delayed read retries) and 0 address wait states, 1 data wait state on the local bus
are assumed.
PCI
BAR BAR Description Write
[PCI Clock Cycles]
(Time @ 33MHz)
Read
[PCI Clock Cycles]
(Time @ 33MHz)
BAR0 PCI Target
Register Space 5 + 2 Idle (212ns) 14 + 2 Idle (485ns)
BAR1 In-System
Programming Space 5 + 2 Idle
(212ns) 9 + 2 Idle (333ns)
BAR2-5 User Space 0-3
Posted Write on PCI Bus:
5 + 2 Idle
(212ns)
Additional Time for the write
to complete on the Local Bus
is approx. 120ns.
Delayed Read on PCI Bus:
22 + 2 Idle
(727ns)
Table 4-3 : Approximate PCI Access Times

TPMC634 User Manual Issue 1.0.1 Page 19 of 93
5 Address Maps
PCI Target Register Space5.1
PCI BAR 0 implements the Configuration Registers located within the PCI Target Device.
Offset to
PCI BAR Register Name
0x90 Local Bus Interface Control / Status Register
0x94 Reserved
0x98 Reserved
0x9C Reserved
0xA0 Reserved (I/O Interface Control / Status Register)
0xA4 Reserved
0xA8 Reserved
0xAC Reserved
0xB0 Configuration EEPROM Register
0xB4 Reserved
0xB8 Reserved
0xBC Reserved
0xC0 Interrupt Enable Register
0xC4 Interrupt Status Register
0xC8 Interrupt Configuration Register
0xCC Reserved
0xD0 User FPGA Configuration Control & Status Register
0xD4 User FPGA Configuration Data Register (Slave SelectMAP)
0xD8 Reserved
0xDC Reserved
0xE0 ISP Control Register (SPI)
0xE4 ISP Configuration Register (SPI)
0xE8 ISP Command Register (SPI)
0xEC ISP Status Register (SPI)
0xF0 Control & Status Register
0xF4 Reserved
0xF8 Reserved
0xFC Firmware Version Register
Table 5-1 : PCI Target Register Space

TPMC634 User Manual Issue 1.0.1 Page 20 of 93
5.1.1 Local Bus Interface Register (0x90)
Bit Symbol Description Access Reset
Value
Event Flags
31:27 - Reserved - 0
26 LB_PLL_LOS
Local Bus PLL Loss-of-Lock Flag
Set by HW when the local bus clock
PLL lock status
has changed from locked to not-locked
Only functional
for PLL based local bus clock
implementation options
Write ‘1’ to clear the flag
R/C 0
25 LB_TERR
Local Bus Target Error Flag
Set by HW in case the target reports an error
condition during a local bus cycle
Write ‘1’ to clear the flag
R/C 0
24 LB_MABT
Local Bus Master Abort Flag (Time-Out)
Set by HW in case of a master initiated local bus
cycle abort (time-out)
Only functional when the Local Bus Time-Out
function is enabled
Write ‘1’ to clear the flag
R/C 0
Status Bits
23:18 - Reserved - 0
17 LB_PLL_ST
Local Bus Clock PLL Lock Current Status
0: PLL not locked
1: PLL locked
Only for PLL based local bus clock implementation
options
R x
16 LB_RST_ST
Local Bus Reset Line Status
0: Local Bus Reset Line is not active
1: Local Bus Reset Line is active
Note that the local bus reset line is also active while
the user FPGA is not configured
or the local bus
clock PLL is not locked
R x
Control Bits
15:3 - Reserved - 0
2 LB_PLL_RST
Local Bus Clock PLL Reset
0: PLL Operating Mode
1: PLL Reset Mode
Only for PLL based local bus clock implementation
options
R/W 0
1 LB_TO_DIS
Local Bus Time-Out Disable
0: Local Bus Time-Out Enabled (Default)
1: Local Bus Time-Out Disabled
See the Local Bus
Interface chapter for more
information
R/W 0