Texas Instruments THS7002 User manual

THS7002
ProgrammableĆGain Amplifier
Evaluation Module
July 1999 Mixed-Signal Products
User’s Guide
SLOU037

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Copyright 1999, Texas Instruments Incorporated

iii
Chapter Title—Attribute Reference
Preface
Related Documentation From Texas Instruments
J THS7002 PROGRAMMABLE-GAIN AMPLIFIER (literature
number SLOS214) This is the data sheet for the THS7002
amplifier integrated circuit used on the EVM.
J THS4001 HIGH-SPEED LOW-POWER OPERATIONAL
AMPLIFIER
(literature number SLOS206) This is the data sheet
for the THS4001 amplifier integrated circuit used on the EVM.
J PowerPAD  Thermally Enhanced Package (literature number
SLMA002) This is the technical brief for the special PowerPAD
package in which the THS7002 amplifier IC is supplied.
FCC Warning
This equipment is intended for use in a laboratory test environment only. It
generates, uses, and can radiate radio frequency energy and has not been
testedforcompliancewiththelimitsofcomputingdevicespursuanttosubpart
Jofpart 15ofFCCrules,which aredesignedtoprovidereasonableprotection
against radio frequency interference. Operation of this equipment in other
environments may cause interference with radio communications, in which
case the user at his own expense will be required to take whatever measures
may be required to correct this interference.
Trademarks
TI is a trademark of Texas Instruments Incorporated.
PowerPAD is a trademark of Texas Instruments Incorporated.

iv

Running Title—Attribute Reference
v
Chapter Title—Attribute Reference
Contents
1 General Information 1-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1 Features 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 Description 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3 Programmable Gain Amplifier Gain Control 1-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4 EVM DIP Switch Functionality 1-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5 EVM Circuit Configuration 1-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.6 Using the THS7002 EVM 1-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.7 THS7002 EVM Performance 1-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.8 General High-Speed Amplifier Design Considerations 1-16. . . . . . . . . . . . . . . . . . . . . . . . . .
1.9 General PowerPAD t Design Considerations 1-17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.10 THS7002 EVM Specifications 1-20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 Reference 2-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1 THS7002 Programmable-Gain Amplifier EVM Parts List 2-2. . . . . . . . . . . . . . . . . . . . . . . . .
2.2 THS7002 EVM Board Layouts 2-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Running Title—Attribute Reference
vi
Figures
1–1 THS7002 Evaluation Module 1-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1–2 THS7002 EVM Power Conditioning Schematic Diagram 1-3. . . . . . . . . . . . . . . . . . . . . . . . . . . .
1–3 THS7002 EVM Schematic Diagram 1-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1–4 Simplified PGA Section of the THS7002 1-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1–5 THS7002 Evaluation Module Block Diagram 1-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1–6 THS7002 EVM Preamplifier Frequency Response 1-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1–7 THS7002 EVM Preamplifier Phase Response 1-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1–8 THS7002 EVM PGA Frequency Response 1-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1–9 THS7002 EVM PGA Phase Response 1-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1–10 THS7002 EVM Preamplifier + PGA Frequency Response 1-15. . . . . . . . . . . . . . . . . . . . . . . . .
1–11 THS7002 EVM Preamplifier + PGA Phase Response 1-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1–12 PowerPAD PCB Etch and Via Pattern 1-17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1–13 Maximum Power Dissipation vs Free-Air Temperature 1-18. . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–1 THS7002 EVM Component Placement Silkscreen and Solder Pads 2-3. . . . . . . . . . . . . . . . .
2–2 THS7002 EVM PC Board: Top Assembly 2-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–3 THS7002 EVM PC Board: Top Layer 2-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–4 THS7002 EVM PC Board: Bottom Layer 2-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Tables
1–1 THS7002 EVM PGA Nominal Gain/Attenuation 1-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1–2 EVM DIP Switch Functionality 1-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1–3 THS7002 EVM Jumper Settings 1-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1–4 THS7002 EVM DIP Switch Settings 1-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–1 THS7002 Programmable-Gain Amplifier EVM Parts List 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-1
General Information
General
Information
This chapter details the Texas Instruments (TI) THS7002
programmable-gainamplifierevaluationmodule(EVM),SLOP136.Itincludes
alistof EVMfeatures,abriefdescriptionofthemoduleillustratedwithpictorial
and schematic diagrams, EVM specifications, details on configuring,
connecting,andusingtheEVM,andadiscussiononhigh-speedamplifier and
PowerPAD package design considerations.
Topic Page
1.1 Features 1–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 Description 1–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3 Programmable Gain Amplifier Gain Control 1–7. . . . . . . . . . . . . . . . . . . . .
1.4 EVM DIP Switch Functionality 1–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5 EVM CIrcuit Configuration 1–10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.6 Using The THS7002 EVM 1–12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.7 THS7002 EVM Performance 1–13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.8 General High-Speed Amplifier Design Considerations 1–16. . . . . . . . .
1.9 General PowerPADDesign Considerations 1–17. . . . . . . . . . . . . . . . . .
1.10 THS7002 EVM Specifications 1–20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 1

Features
1-2
General Information
1.1 Features
THS7002 programmable-gain amplifier EVM features include:
J Multiple Input Configurations Set Via On-board Jumpers
J DIP Switches Allow Quick and Easy Adjustment of Gain, Shut Down,
Reference Voltage, and Output Clamping
J Includes a THS4001 High-Speed Amplifier as an Inverter
J Standard BNC Connectors Inputs and Outputs
J ±5-V to ±15-V Operation with 5-V Reference Input
J Nominal 50-ΩImpedance Inputs and Outputs
J Includes Test Points for Easy Digital Control of EVM Circuit Gain and
Operating Parameters
J Good Example of PowerPAD Package and High-Speed Amplifier
Design and Layout
1.2 Description
The TI THS7002 programmable-gain amplifier evaluation module (EVM) is a
complete dual-channel low-noise receiver and a highly configurable
programmable-gain amplifier circuit. It consists of the TI THS7002
Programmable-Gain Amplifier IC, a TI THS4001 high-speed, low-power
operational amplifier IC, and a number of passive parts, all mounted on a
multilayer circuit board (Figure 1–1).
Although the THS7002 IC was developed primarily for xDSL receiver
front-ends, there are a large number of different circuits that can benefit from
the many features incorporated into the THS7002. This EVM illustrates a
universal design and can be used for numerous system configurations.
The EVM uses standard BNC connectors for inputs and outputs and also
includes test points for user connections and testing. It is completely
assembled, fully tested, and ready to use — just connect it to power, a signal
source, and a load (if desired).

Description
1-3
General Information
Figure 1–1.THS7002 Evaluation Module
PGA – A
Output
R45
PGA – B
Output
C21L2C5C4L1
+VCC GND +5 V–VCC
Pre-AmpA
Output
Pre-Amp B
Output
Input B
J7
B
J8
C20
JP5
J10
J9
C3
R4
R3
U2
C2
R1C1 R2 R9
InputA J6
J5
R24
R26
R28
R30
R32
C18
C19 R34
R36
R38
R40
R42
R44
R18 R5
U1
AG2
(3)
AG1
(2)
AG0
(1)
S1
S2
VH
(6)
BVREF
(5)
BS/D
(4)
AS/D
(4)
AVREF
(5)
VL
(6)
BG2
(1)
BG1
(2)
BG0
(3)
JP4JP3
R16 R17
C17
JP1
R6
C6
R20
C7
C11
C12
R12 C13
C10
R11
R15
R14
R13
R35
R37
R39
R41
R23
R25
R27
R29
R11
R33
R10
C9
JP2
C14
1998
Texas Instruments
J4J3
J2
J1
SLOP136
Rev. B THS7002 EVM Board
+++
R7
R8
C8
GND
U2 Out
1
1
11
1
InputpowerisappliedtotheEVMthroughbananajacksJ1,J2,J3, and J4. An
LC filter on each power bus isolates the EVM circuits from the external supply
(Figure 1–2). J4 provides a reference point for numerous circuit functions and
draws relatively little current. The schematic for the EVM amplifiers appears
in Figure 1–3.
Figure 1–2.THS7002 EVM Power Conditioning Schematic Diagram
–15 V
L1
0.22 µHC4
6.8 µF
15 V
J1
VCC
+
J2
GND
+
J3
–VCC
+
J4
5 V
5 V
L2
0.22 µH
C5
6.8 µFC21 6.8 µF
TP1

Description
1-4
General Information
+ –
C11
0.1 µF
R9 49.9 Ω
15 V
U1-A
THS7002
8
5
6
–15 V
C12, 0.1 µF
4
J6
Input A
C8, TBD
7R5
49.9 ΩJ5
Pre-amp A Out
3 2
1
R8
499 Ω
R7
499 Ω
+ –
R16 49.9 Ω
15 V
U2
THS4001
7
2 3
–15 V
5
C1, TBD
4
R4
22 Ω
3
2
1
R1
1 kΩ
R2
1 kΩ
C2, 0.1 µF
JP1
TP12
U2-Out
J7
Input B
3
2
JP3
JP2
+ –
U1-C
10
9
11
R3 TBD
R13
TBD
C3, 0.1 µF
C9
TBD
C10, TBD
R11
499 Ω
R10
499 Ω
3 2
1
R17
49.9 ΩJ8
Pre-amp B Output
JP4
C14, TBD
R14
0 Ω
C6, TBD
R6
0 Ω
R20
TBD C7
TBD
R12
TBD C13
TBD
G2
G1
G0
VREF
SID
–Vcc VCC
VH
VL
VO
GND
VIN–
26
28
21
27
C18, 0.1 µF–15 V
13
14
25
22
R29 330 ΩR18
49.9 Ω
R30
3.3 kΩ
5 V
S1-D S1-E
AVREF TP8
AS/D
TP7
C19, 0.1 µF
15 V
R23, 330Ω
R25, 330Ω
R27, 330Ω
R24, 3.3 kΩ R26, 3.3 kΩ R28, 3.3 kΩ3
2
1
S2-F
TP5
VH
R41
49.9 ΩR42
4.7 kΩ
R31
49.9 ΩR32
4.7 kΩ
R44
100 ΩJ9
PGA-A Output
VL
TP6 S1-F
–15 V
5 V15 V JP5
AG2, TP3
C17, 0.1 µF
5 V
G0
G1
G2
15
17
16
R35, 330Ω
R37, 330Ω
R39, 330Ω
20 24
23
3
VIN–
VREF
SID
GND
12 R45
100 ΩJ10
PGA-B Output
19
R33 330 ΩR15
49.9 Ω
R34
3.3 kΩ
5 V
S2-D S2-E
BVREF TP14
BS/D
TP13
2
1
R36, 3.3 kΩ R38, 3.3 kΩ R40, 3.3 kΩ
BG2, TP9
C20, 0.1 µF5 V
S2-A
S2-B
S2-C
BG1, TP10
BG0, TP11
VO
TP2, AG0 TP4, AG1
U1–B
U1–D
18
Figure 1–3.THS7002 EVM Schematic Diagram

Description
1-5
General Information
TheTHS7002EVMis equippedwithaseparateBNCinputconnectorforeach
of the two channels on the module. Each input is terminated with a 50-Ω
resistor to provide correct line impedance matching (Figure 1–3). Note that
using a source with a 50-Ωoutput impedance will create a voltage divider at
the EVM inputs. Thus, accurate knowledge of the source output
characteristics is required to determine proper input signal amplitudes.
The outputs of the preamplifier stages are routed through 50-Ωresistors to
provide proper cable impedance matching and termination impedance
matching. One of the drawbacks of using this type of impedance matching is
that it places an equivalent 100-Ωload on the output of the preamplifiers.
Although the preamplifier sections have a large output current capability, the
programmable gain amplifier (PGA) sections have a limited current drive
capability. It is recommended that the total impedance placed on the outputs
of the PGA section is at least 500 Ω.
The THS4001 IC and the THS7002 IC are voltage feedback amplifiers. They
follow the classic operational amplifier gain equations:
Inverting Gain +
–RF
RG(1)
Non-Inverting Gain + 1 )
RF
RG(2)
The gain of these amplifiers can easily be changed to support different
applications by changing the resistor ratios. Although any of the components
on the EVM board can be replaced with different values, it is imperative that
the THS7002 preamplifier gain be kept to a minimum of +2 or –1 for stability
purposes.Also,componentpadshavebeenplacedinconvenientlocationson
the PCB (shown as components with the value X in the schematic) to allow
numerous modifications to the basic EVM configuration. However, care must
be taken because the surface-mount solder pads on the board are somewhat
fragileandwillnotsurvivealargenumberofsoldering/desolderingoperations.
For single-ended input configurations, a THS4001 is used to invert the
incoming signal to drive the second channel of the THS7002. This allows for
a single-to-differential analysis of the EVM. However, by simply moving a
jumper (JP3) and using the second input BNC connector (J7), a differential
source or independent signals can be seen on the outputs.
For independent evaluation of the preamplifiers, BNC connectors directly at
the preamplifier output pins (J5 and J8) allow the user to investigate these
amplifiers independently of the PGA sections.

Description
1-6
General Information
The shutdown feature of the THS7002 IC is implemented on this EVM. There
is a separate shutdown pin for each half of the THS7002 IC. The shutdown
signals are low for normal THS7002 operation. When a shutdown pin is high
(5 V), the corresponding preamplifier and PGA section is turned off.
ShutdownsontheEVMarecontrolledbyswitchesS1:D(Achannel)andS2:D
(B channel), or by applying an external shutdown signal to test–points TP7 (A
channel)andTP13(Bchannel)withtheswitchessettoOFF.Isolationresistors
on the THS7002 IC shutdown control input pins are used to minimize surges
in the EVM environment and can be omitted in a final system design.

Programmable Gain Amplifier Gain Control
1-7
General Information
1.3 Programmable Gain Amplifier Gain Control
Each channel of the THS7002 IC is provided with three digital control inputs
for setting the gain of the PGA stage (AG0 – AG2 and BG0 – BG2). Standard
TTL or CMOS Logic signals operate these control inputs. The gain control
inputs are not latched and respond to the control signals in real time.
Therefore,thecontrolsignalsontheseinputsmustremainconstantifthePGA
gainistoremainconstant.Forstand-aloneevaluationofthisfunction,onboard
DIP switches (S1:A to S1:C and S2:A to S2:C) are used to control the gain for
each PGA. Note that all DIP switch gain control elements must be set to OFF
if gain is to be set by digital control signals. For convenience, test points (TP2
–TP4andTP9–TP11)areplacedoneachoftheselinestoalloweasyexternal
connections. There are 330-Ωisolation resistors in series with each IC gain
control input pins. These were added only for surge suppression and are not
required for actual system design. Nominal gain/attenuation is shown in
Table 1–1.
Table 1–1.THS7002 EVM PGA Nominal Gain/Attenuation
G2 G1 G0 PGA Gain (dB) PGA Gain (V/V)
0 0 0 –22 0.08
0 0 1 –16 0.16
0 1 0 –10 0.32
0 1 1 –4 0.63
1 0 0 2 1.26
1 0 1 8 2.52
1 1 0 14 5.01
1 1 1 20 10
OneaspectoftheTHS7002PGAsignalinputsthatmustbeconsideredisthat
there are internal variable resistors (RF and RG) that set the gain. The
resistance of RG changes from about 270 Ω(gain = +20 dB) to about 3 kΩ
(gain = –22 dB). Therefore, any source impedance at the input to the PGA
amplifiers will cause a gain error to be seen at the output. A buffer/amplifier is
highly recommended to directly drive the input of the PGA section to help
minimize this effect.
Another consideration is that when each amplifier VREF is connected to
ground, the internal RG resistor is connected to a virtual ground. Therefore,
if a termination resistor is used on the source side, the total terminating
resistance is the parallel combination of the terminating resistance and the
internal RG resistor. This, in conjunction with the series impedance problem
mentioned previously, can potentially cause a voltage mismatch between the
output of a 50-Ωsource and the expected PGA output voltage.
These points are illustrated by the following formula and in the simplified
diagram of the THS7002 PGA section shown in Figure 1–4.
RTOTALTERMINATION
+
RTERMINATION (RSOURCE ) RG)
RTERMINATION
) (RSOURCE ) RG)(3)

Programmable Gain Amplifier Gain Control
1-8
General Information
Figure 1–4.Simplified PGA Section of the THS7002
+
–PGA
VOUT
No Source Impedance
VIN
RGRF
PGA
G0G1G2
PGA
–VIN
Negative
Clamp VL
Positive
Clamp VH
THS7002 IC
PGA
VREF
RTERMINATION
RSOURCE
The PGA VREF terminals are also accessible via test points TP8 and TP14.
Typically, the DIP switches are used to keep this point at ground. If a voltage
is applied to this terminal, then the output of the PGA section will amplify the
appliedreferencevoltagebyoneplus the selected gain. Thus, the outputgain
due only to VREF will be from +0.6 dB to +21 dB according to the following
formula:
ǒ
VOUT
VREF
Ǔ+
20 Log10
ƪ
1 )ǒ PGA Gain(V ń V
ǓǓƫ
Typically, the output of the PGA will directly drive an A/D converter. Because
of the limited linear input range and saturation characteristics of most ADCs,
the PGA outputs incorporate a voltage clamp. Because the internal clamps
use the same clamping reference voltages, the outputs of both PGAs are
clamped to the same values. These clamps are typically connected to the
powersupplypinstoallowafulloutputrange.However,bysettingswitchS1:F
to OFF and setting switch S2:F to ON, the outputs will be clamped to either
+Vcc or +5V (depending on JP5) and ground. The outputs can be further
limited by applying an external reference voltage to test points TP5 (VH) and
TP6 (VL). The accuracy of this clamp is dependant on the amount of current
flowing through the internal clamping diodes. As is typical with all diodes, the
voltagedropacrossthisdiodeincreaseswithcurrent.Therefore,theaccuracy
oftheclampishighlydependantupontheoutputvoltage,theclampingvoltage
differences, and the output current. The 50-Ωseries resistors are placed on
this EVM only for surge suppression. In a final system layout, these resistors
are not required for proper operation.

EVM DIP Switch Functionality
1-9
General Information
1.4 EVM DIP Switch Functionality
The THS7002 can be fully evaluated without any external digital control
signals applied. This is accomplished through the use of two banks of DIP
switches. Each DIP switch bank incorporates six SPST switches labeled A
through F. The functionality of each switch is described in Table 1–2.
Table 1–2.EVM DIP Switch Functionality
SWITCH LABEL POSITION DESCRIPTION
S1:A
AG0
0PGA – A-Channel Gain Bit 0 (LSB): Value = 0 (Low)
S1
:
A
A
–
G0
1PGA – A-Channel Gain Bit 0 (LSB): Value = 1 (High)
S1:B
AG1
0PGA – A-Channel Gain Bit 1: Value = 0 (Low)
S1
:
B
A
–
G1
1PGA – A-Channel Gain Bit 1: Value = 1 (High)
S1:C
AG2
0PGA – A-Channel Gain Bit 2 (MSB): Value = 0 (Low)
S1
:
C
A
–
G2
1PGA– A-Channel Gain Bit 2 (MSB): Value = 1 (High)
S1:D
A S/D
0A-Channel Shutdown: Value = 0 (Low) — A Side Active
S1
:
D
A
–
S/D
1A-Channel Shutdown: Value = 1 (High) — A Side Shutdown
S1:E
A VREF
0A-Channel VREF Floating (Connect TP8 to Ext. Ref.)
S1
:
E
A
–
VREF
1A-Channel VREF Connected to Ground
S1:F
VL
0Low Side Clamp Ground (Connect TP6 to Ext Ref)
S1
:
F
VL
1Low Side Clamp Connected to –Vcc
S2:A
BG2
0PGA – B-Channel Gain Bit 2 (MSB): Value = 0 (Low)
S2
:
A
B
–
G2
1PGA – B-Channel Gain Bit 2 (MSB): Value = 1 (High)
S2:B
BG1
0PGA – B-Channel Gain Bit 1: Value = 0 (Low)
S2
:
B
B
–
G1
1PGA – B-Channel Gain Bit 1: Value = 1 (High)
S2:C
BG0
0PGA – B-Channel Gain Bit 0 (LSB): Value = 0 (Low)
S2
:
C
B
–
G0
1PGA – B-Channel Gain Bit 0 (LSB): Value = 1 (High)
S2:D
B S/D
0B-Channel Shutdown: Value = 0 (Low) — B Side Active
S2
:
D
B
–
S/D
1B-Channel Shutdown: Value = 1 (High) — B Side Shutdown
S2:E
B VREF
0B-Channel VREF Floating (Connect TP14 to Ext Ref)
S2
:
E
B
–
VREF
1B-Channel VREF Connected to Ground
S2:F
VH
0High Side Clamp Ground (Connect TP5 to Ext Ref)
S2
:
F
VH
1High Side Clamp Connected to JP5 (Vcc or 5 V)

EVM Circuit Configuration
1-10
General Information
1.5 EVM Circuit Configuration
The THS7002 EVM design allows evaluation of each section of the THS7002
amplifier IC separately as well as a differential system. Configuration of the
EVM is accomplished through jumpers mounted on the module PCB. Each
jumper is a three-pin header that acts as an SPDT switch when a shunt is
placedacrosstwoofthethreepinstoselecteither of two signal routes (Figure
1–5).
Figure 1–5.THS7002 Evaluation Module Block Diagram
1
3
2
J6
JP1
1
3
2
JP2
3
2
JP3
–
+
J7
THS7002
THS7002
THS7002
THS7002
THS4001
U1:A
U2
U1: B
U1: D
Preamp A
Output
PGA A
Output
Input A
Input B
Preamp A PGA A
Inverter
J9
J8
J5
J10
U1:C
1
JP4
21
3
PGA B
PGA B
Output
Preamp B
Output
Preamp B
JP5
VH Clamp 15 V
5 V
1
32
- Jumper JP1:
J 1–2 — Connects the input of A-channel PGA (U1: B) to the input A
BNC (J6), bypassing the THS7002 A-channel preamplifier (U1:A)
J 2–3 — Connects the input of A-channel PGA (U1: B) to the output of
the A-channel preamplifier (U1:A)
- Jumper JP2:
J 1–2 — Connects the inverting input terminal of the B-channel
preamplifier (U1:C) to the signal from JP3 (either the THS4001
inverting amplifier (U2) output or the input B BNC (J7) signal,
depending on the setting of JP3). In order to use this functionality,
components R3, R13, and C9 must be selected and installed on the
EVM by the user
J 2–3 — Connects the noninverting input terminal of the B-channel
preamplifier (U1:C) to the signal from JP3
- Jumper JP3:
J 1–2—Connects theinputoftheB-channelpreamplifier(U1:C)orthe
B-channel PGA (U1:D) to the output of the THS4001 inverting
amplifier (U2). This signal is an inverted version of the input A BNC
(J6) signal
J 2–3—Connects theinputoftheB-channelpreamplifier(U1:C)orthe
B-channel PGA (U1:D) to the input B BNC (J7)

EVM Circuit Configuration
1-11
General Information
- Jumper JP4:
J 1–2 — Connects the input of the B-channel PGA (U1: D) to the signal
from JP3
J 2–3—Connects the input oftheB-channel PGA (U1: D)tothe output
of the B-channel preamplifier (U1:C)
- Jumper JP5:
J 1–2—Connects theTHS7002ICpositiveclampinputpin(VH)toVcc
when switch S2:F is set appropriately
J 2–3—ConnectstheTHS7002ICpositiveclampinputpin(VH)to+5V
when switch S2:F is set appropriately
For example, to use a single-ended input and use the preamplifiers as buffers
and gain:
1) Set JP1 to 2–3
2) Set JP2 to 2–3
3) Set JP3 to 1–2
4) Set JP4 to 2–3
5) Apply the input to input A (J6)
The output of the THS7002 PGAs is a differential signal due to the inverter
(U2).Foreitheranindependentordifferentialsignalsource,JP3shouldbeset
to the 2–3 position.

Using the THS7002 EVM
1-12
General Information
1.6 Using the THS7002 EVM
The THS7002 EVM operates from a split power supply with voltages ranging
from ±5 V to ±15 V. It also uses 5 volt logic control signals to configure the
operation of the EVM when the DIP switches are used. The use of a single
supplyforthisEVMisnotrecommended.Asshipped,thepreamplifiersareset
to a gain of 2 and the EVM is configured for a single-ended input that uses the
preamplifierstodirectlydrivethePGAstages.Anoscilloscopeistypicallyused
to view and analyze the EVM output signals.
1) Ensurethatallpowersuppliesaresetto
OFF beforemakingpowersupply
connections to the THS7002 EVM.
2) Select the operating voltage for the EVM and connect appropriate split
powersuppliestothebananajacks on the module marked
+V
CC
(J1)and
–V
CC
(J3).
3) Connect a 5-V power supply to the banana jack marked +5 V (J4).
4) Connect all power supply grounds to the banana jack marked GND (J2).
5) Connect an oscilloscope probe to the PGA–A amplifier output BNC (J9).
ConnectingdirectlytoJ9witha50-Ωnominalimpedancecableandprobe
is not recommended. The output drive capability of the PGAs is very
limited. Such a connection will load the output excessively, reducing the
outputvoltage range of the amplifier and is not a true measurement ofthe
amplifier performance.
6) Set EVM jumpers as shown in Table 1–3.
Table 1–3.THS7002 EVM Jumper Settings
JP1 JP2 JP3 JP4 JP5
2–3 2–3 1–2 2–3 1–2
7) Set DIP switch 1 and 2 elements as shown in Table 1–4.
Table 1–4.THS7002 EVM DIP Switch Settings
SWITCH S1 LABEL POSITION SWITCH S2 LABEL POSITION
S1:A A–G0 0 S2:A B–G2 1
S1:B A–G1 0 S2:B B–G1 0
S1:C A–G2 1 S2:C B–G0 0
S1:D A–S/D 0 S2:D B–S/D 0
S1:E A–VREF 1 S2:E B–VREF 1
S1:F VL 1 S2:F VH 1
8) Set the power supplies to ON .
9) Connect a signal input to the INPUT A BNC (J6).
Note that each input connector on this EVM is terminated with a 50-Ωresistor
to ground. With a 50-Ωsource impedance, the voltage seen by the THS7002
amplifierIContheEVMwill be ½ thesourcesignal voltageappliedtotheEVM
input connector.
10) Verifytheoutputsignalontheoscilloscopeusingahigh-impedanceprobe
— a voltage gain of approximately 2.5 to 1 should be observed.

THS7002 EVM Performance
1-13
General Information
1.7 THS7002 EVM Performance
Figure 1–6 shows the typical frequency response and Figure 1–7 shows the
typical phase response of the THS7002 EVM preamplifiers. Typical –3 dB
bandwidth with a ±15-V power supply is 100 MHz for the preamplifier in each
channel and 90 MHz with a ±5-V power supply.
Figure 1–6.THS7002 EVM Preamplifier Frequency Response
f – Frequency – Hz
100k 1M 10M 100M
6
4
2
7
5
3
1
500M
VO= 0.4 Vp–p
RL= 150 Ω
Output Amplitude – dB
0
VCC = ±5 V
VCC=±15V
Figure 1–7.THS7002 EVM Preamplifier Phase Response
f – Frequency – Hz
–180 1M
–60
100k
–150
–120
500M
–30
30
0
10M 100M
VCC = ±5 V
VCC = ±15 V
Output Phase – °
VO= 0.4 Vp–p
RL= 150 Ω
–90

THS7002 EVM Performance
1-14
General Information
Figure 1–8 shows the typical frequency response and Figure 1–9 shows the
typical phase response of the THS7002 EVM PGAs. This data was collected
with the gain set to +2 dB. Typical –3 dB bandwidth is 65 MHz with a ±5-V
power supply and 70 MHz with a ±15-V power supply.
Figure 1–8.THS7002 EVM PGA Frequency Response
f – Frequency – Hz
100k 1M 10M 100M
3
1
4
2
0
–2
–1
500M
VO= 0.4 Vp–p
RL= 500 Ω
Output Amplitude – dB
–3
VCC = ±5 V
VCC=±15V
Figure 1–9.THS7002 EVM PGA Phase Response
f – Frequency – Hz
01M
90
100k
30
60
500M
120
210
150
10M 100M
VO= 0.4 Vp–p
RL= 500 Ω
VCC = ±5 V
VCC = ±15 V
Output Phase – °
180