Texas Instruments TAS54 4C Series Guide

Developer's Guide
SLOA196–June 2014
TAS54x4C Design Guide
The TAS5414C-Q1 and TAS5424C-Q1 devices are 4-channel class-D amplifiers in one integrated circuit
(IC). The devices were developed for automotive use and are qualified in accordance with the AECQ100
specification. When designing the control code to operate the TAS5414B, TAS524B, TAS5414C,
TAS5424C, and TAS5412 devices through I2C, the unique device characteristics must be taken into
account for proper system function. This design guide includes software development guidelines as well
as hardware instructions to provide the necessary circuit topologies and part types to meet strict OEM-
audio specifications and the EMI standards of CISPR25.
Contents
1 TAS54x4C Hardware Design Guidelines................................................................................. 3
1.1 Circuit Design ....................................................................................................... 3
1.2 I2C Communication ................................................................................................ 4
1.3 Oscillator............................................................................................................. 5
1.4 Output ................................................................................................................ 7
1.5 Component Selection............................................................................................. 10
1.6 Protection........................................................................................................... 12
1.7 Load Diagnostics.................................................................................................. 13
1.8 Power Supply...................................................................................................... 15
1.9 Charge Pump...................................................................................................... 15
1.10 EMI and PCB Layout Considerations........................................................................... 16
1.11 Filtering ............................................................................................................. 16
1.12 Paralleling Outputs................................................................................................ 17
1.13 Mute................................................................................................................. 17
1.14 Standby............................................................................................................. 17
1.15 Line Output......................................................................................................... 18
1.16 Harmonic Crosstalk ............................................................................................... 18
1.17 THD+N Versus Frequency....................................................................................... 19
2 TAS54x4C Software Design Guidelines................................................................................. 20
2.1 Definitions .......................................................................................................... 20
2.2 Power Up and Initialization ...................................................................................... 21
2.3 Using the Device to Play Music ................................................................................. 22
2.4 Using the Device to Stop Playing Musing...................................................................... 23
2.5 Load Diagnostics.................................................................................................. 24
2.6 Fault Handling ..................................................................................................... 25
2.7 Device Mode Summary........................................................................................... 26
List of Figures
1 TAS5414C Input Circuit..................................................................................................... 3
2 Clock Synchronization Options ............................................................................................ 6
3 One-Half of the Typical Output Stage With Snubbers .................................................................. 8
4 Typical Output Demodulation Filter........................................................................................ 9
5 Inductance Versus Current and Q Factor............................................................................... 10
6 CLIP_OTW Pin Voltage Versus % of THD ............................................................................. 13
7 Load-Diagnostic Output-Waveforms Timing Diagram................................................................. 14
8 Channel 1 →Channel 3 Harmonic Crosstalk With Default Switching Phase Settings ........................... 18
9 THD+N vs Frequency Improvements.................................................................................... 19
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10 Power Up and Initialization................................................................................................ 21
11 Turnon flowchart............................................................................................................ 22
12 Turnoff Flowchart .......................................................................................................... 23
13 Load Diagnostics, Four Channels........................................................................................ 24
14 Global Fault Handling...................................................................................................... 25
15 Channel Fault Handling ................................................................................................... 26
16 Mode Summary, Excluding Faults ....................................................................................... 26
List of Tables
1 Oscillator Configuration and I2C Addresses.............................................................................. 4
2 Recommended Switching Frequencies for AM Mode Operation...................................................... 7
3 Load Diagnostic Timing ................................................................................................... 14
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C1
1 µF R1
499 
+
R2
499 
C2
1200 pF
R3
250 
C4
4 µF
In_P 1, 2, 3, 4
In_M
Audio Source
co 1
¦2 R C
u S u u
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1 TAS54x4C Hardware Design Guidelines
When designing an audio amplifier with the TAS5414C and TAS5424C class-D integrated devices, the
details of the full system design are not included in the data sheet. This design guide supplements the
data sheet with detailed hardware-related information on designing an audio amplifier product.
1.1 Circuit Design
1.1.1 Input
The input stage of the TAS5414C devices is single ended. The TAS5424C input stage is either differential
or balanced. The audio input pins have a bias voltage of 3.25 VDC with a tolerance of 2.8 VDC to 3.7
VDC. Therefore direct coupling to the input pins is not possible. An input coupling capacitor must be used.
The value of the capacitor is based on two criteria. The value of the capacitor must be large enough to
pass low frequencies, but not so large that the charge time on this capacitor is too long which can cause
pop and click noise at the output of the amplifier.
The input impedance of each input pin is 80 kΩ±20 kΩ. Use Equation 1 to calculate the low-frequency
cutoff frequency (–3 dB).
where
• ƒCO = cutoff frequency in Hertz
• R = 80 kΩ
• C = coupling capacitor (1)
The recommended capacitor values for the TAS54x4C devices are 0.47 µF or 1 µF. For a 0.47 µF
capacitor with 20% tolerance the highest cutoff frequency can be calculated using 60 kΩand 0.38 µF. The
worst-case cutoff frequency for this example is 7.1 Hz which allows for flat gain in the audio band.
The common mode rejection ratio, CMRR, is also affected by the input circuit. The balanced inputs of the
TAS5424C must have equal-value capacitors so that the CMRR is maximized at lower frequencies.
The single-ended input of the TAS5414C must also have the proper input capacitors for good low-
frequency common-mode performance. Because all four IN_P channels in the TAS5414C device share
the IN_M pin, the capacitor from IN_M to ground should be close to the sum of the capacitors on the four
IN_P pins. Additionally, a resistor in series with the IN_M capacitor should be placed between the IN_M
pin and ground that is equal to the parallel equivalent of the input series resistance on all IN_P channels
combined, including the output resistance of the DAC. For example, if 1-kΩof series input resistance is on
each channel of the TAS5414C, a 250-Ωresistor should be placed between the IN_M pin and GND in
series with the IN_M capacitor. Following these guidelines will optimize noise performance. Figure 1
shows an example input circuit that follows this practice.
Figure 1. TAS5414C Input Circuit
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During the turn-on of the amplifier, the input coupling capacitors must charge to the common mode
voltage of 3.25 VDC. If the amplifier is passing a signal during this time, the speakers can have large
excursions, pops, and click. The TAS54x4C devices have a precharge resistor on the inputs to quickly
charge the coupling capacitors. After the capacitor is charged, the resistor is taken out of the circuit and
the 80 kΩresistor is in place. This worst-case value of the precharge resistor is 600 Ω.Equation 2
calculates the charge time using the worse case value from the example in Figure 1 of 1.2 µF and 600 Ω.
VI(x) = VI(x)max × (1 – e–t / RC) (2)
The input capacitors should have good audio qualities as the audio input signal to the amplifier passes
directly through it. A good-quality capacitor can be a film type or a very-low leakage electrolytic. Ceramic
capacitors can be used, but can degrade the sound quality. Low leakage on the capacitor is important for
low direct-current (DC) offset at the output of the amplifier. The TAS54x4C amplifiers provide gain at DC.
Any leakage current will flow through the 80-kΩinput impedance and cause a small DC offset between
the input pins. This small DC offset will be amplified by the gain setting.
1.2 I2C Communication
Three pins are associated with the I2C communication protocol. Both devices have the clock pin (SCL)
and the data pin (SDA), while the address selection pin is labeled I2C_ADDR on the TAS54x4C devices.
1.2.1 Device Address Selection
The TAS54x4C devices have the capability of using four different I2C addresses. The devices in this family
share the same I2C device addresses which allows for up to four TAS5414C and TAS5424C devices to be
controlled by one I2C controller without I2C bus switches. The I2C address is determined by the DC voltage
present on the address selection pin. The I2C-address pin voltage is sensed when the device is released
from standby mode. This voltage is then latched at 300 µs. Therefore, any noise or voltage glitch cannot
change the I2C address during operation. Because this pin latches when released from standby, a
capacitor is not necessary on this pin. The charge time on the capacitor may cause an incorrect I2C
address.
NOTE: Do not confuse the master-slave notation with a master-slave I2C.
A slave device must have an external oscillator connected to the OSC_SYNC pin (see Section 1.3.1).
Table 1. Oscillator Configuration and I2C Addresses
OSCILLATOR CONFIGURATION I2C_ADDR PIN CONNECTION I2C ADDRESS
Master To SGND Pin 0xD8, 0xD9
Slave 1 35% DVDD (resistive voltage divider 0xDA, 0xDB
through D_BYP Pin and SGND Pin)
Slave 2 65% DVDD (resistive voltage divider 0xDC, 0xDD
through D_BYP Pin and SGND Pin)
Slave 3 To D_BYP Pin 0xDE, 0xDF
1.2.2 I2C Communications
The SDA and SCL pins communicate with an I2C controller. The SDA pin carries the data and the SCL pin
carries the clock. The TAS54x4C devices are I2C slave-only devices. The device cannot start I2C
transactions and cannot generate an I2C clock. The SCL pin is set for input signals only, whereas the SDA
pin is bidirectional. The TAS54x4C devices send data when the I2C controller sends a read command. The
SDA and SCL pins require pullup resistors to 3.3 VDC or 5 VDC because these pins are 5 VDC tolerant.
A resistor value of 4.7 kΩcan be used for proper operation. The resistor value should be adjusted to the
number of devices on the I2C bus according to the I2C specification.
The TAS5414C and TAS5424C devices have the capability to receive and send sequential data. All
registers can be read sequentially except the fault registers. All registers with write capabilities can be
written sequentially.
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1.2.3 I2C Register Details
The TAS54x4C devices have several different types of registers. These registers can be broken into four
basic categories: fault registers (0x00 to 0x01, 0x13), load diagnostic registers (0x02 to 0x03), status
registers (0x04 to 0x07), and control registers (0x08 to 0x0D, 0x10).
The fault registers report any faults that occurred in the device. If the fault is no longer present when the
register is read, the register will still report that a fault occurred in the past because these registers are
latched. The registers will only clear the fault after the fault has cleared and being read.
The load diagnostic registers report the results of load diagnostics that are performed. These registers are
also latched and will clear when a successful load diagnostic is run.
The status registers report the current status of the device including faults and the operational mode of
each channel. These registers are not latched and report the present state in the device at all times.
The control registers allow the system to modify the settings of the device. Note that some settings may
only be changed in hi-Z.
See Section 2 for more information about the proper usage of the registers.
1.3 Oscillator
The TAS54x4C devices incorporate an internal oscillator to provide all the necessary clocks and the
output PWM switching clock. The oscillator frequency is set by the current on the REXT pin. The current is
set by placing a resister between REXT and ground. The value of the resistor should be 20 kΩwith a
tolerance of 1% for proper operation of the IC. This value sets the frequencies correctly as stated in the
data sheet of the device.
The internal oscillator is 20 MHz which is then divided by 5 for 4 MHz, 6 for 3.33 MHz, or 7 for 2.85 MHz.
These three frequencies synchronize the ICs and are present on the OSC_SYNC pin. This oscillator is
then divided again by 8 to provide 500 kHz, 417 kHz, and 357 kHz switching frequency options. The
divide ratio is set through the I2C.
1.3.1 Oscillator Synchronization
Some designs require more than one TAS54xx device. As previously mentioned in Section 1.2, one I2C
bus can have up to four separate devices. One device is considered the master and the other devices are
considered the slaves. The master provides an oscillator clock on the OSC_SYNC pin and the slave
devices require an oscillator input on the OSC_SYNC pin. All devices are synchronized to avoid beat
frequencies in the audio spectrum. If the clock is lost on the slave, the internal watchdog places the
outputs into hi-Z.
To synchronize the devices, use the following procedure:
1. Bring all the devices out of standby and into hi-Z mode
2. Send the I2C command on the clock master to place the clock signal on the OSC_SYNC pin. Bit 7 in
register 0x0B must be set to 1.
The slave devices are not allowed to enter play mode until the master has sent a clock
For phase synchronization of the devices which minimizes harmonic crosstalk between devices, use the
previous method to synchronize the devices and add these I2C commands after step 2:
1. Place the slave devices in sync-receive mode by changing bit 6 in register 0x0A.
2. Send a sync pulse from the master device by changing bit 6 on register 0x0A.
Bit 6 automatically clears when the synchronization is complete on both the master and slave devices.
Phase synchronization applies to the switching phase and not the audio phase because the audio phase
is always aligned. The inverter allows a new sync pulse between each of the devices to align the 45° or
180° switching phases.
To summarize, two options occur between the OSC_SYNC pin and synchronization of the devices.
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45 90 135 1800 225 270 315 360
Position of the Ch1
phase of the slave
Master
Ch1
Master
Ch2
Master
Ch3
Master
Ch4
Slave
Ch1
45 90 135 1800 225 270 315 360
Position of the Ch1
phase of the slave
Master
Ch1
Master
Ch2
Master
Ch3
Master
Ch4
Slave
Ch1
22.5
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1.3.1.1 Option 1: 45° Phase
Option 1 includes the following features:
• Eight switching phases in each output cycle (0°, 45°, 90°, 135°, 180°, 225°, 270°, 315°)
• Device 1 switching phase: 0°, 45°, 90°, 135°, 180°, 225°, 270°, 315°
• Device 2 switching phase: 22.5°, 67.5°, 112.5°, 157.5°, 202.5°, 247.5°, 292.5°, 337.5° (offset by 22.5°
which is half of the switching phase)
• The best EMI performance out of all the options (16 switching phases per output cycle allows for more
energy distribution)
• Reduced harmonic crosstalk because there is no 90° offset phase, but the performance of Option 2 is
better
1.3.1.2 Option 2: 180° Phase
Option 2 includes the following features:
• Two switching phases in each output cycle (0° and 180°)
• Device 1 switching phase: 0° and 180°
• Device 2 switching phase: 90° and 270° (offset by 90° which is half of the switching phase)
45° Phase 180° Phase
Figure 2. Clock Synchronization Options
NOTE: The PCB layout for the OSC_SYNC should be a direct route or the shortest route from the
master to slave devices for best operation. A star connection is preferred instead of a daisy
chain.
The REXT resistor that sets the 20-MHz oscillator must still be used in the slave devices.
The 20-MHz oscillator is still needed to derive the clock for the internal state machine.
The REXT pin is sensitive. Caution should be used when taking any measurements at this
point. Measurements should be taken with high impedance and low capacitance methods,
because micro amperes of current can change the performance of the TAS54x4C devices.
An external oscillator can also be used to drive one or many TAS54x4C devices in a system. The
oscillator must have a frequency between 2.85 MHz and 4 MHz to maintain proper functionality. To use all
four I2C addresses in a system and an external clock, a special I2C register bit is available that allows the
master address to use an external clock. In register 0x0B, set bit D6 to 1.
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1.3.2 AM Mitigation
A potential issue in a radio is that a switching power supply or a switching amplifier may interfere with the
AM radio reception. The interference is typically a tone that is found at a harmonic of the PWM frequency.
The AM mitigation system provides a method to change the PWM switching frequency using I2C
commands. The controller that provides the I2C commands would require the AM frequency information so
that the correct PWM frequency could be selected. No noise, clicks, or pops occur during the frequency
change so the frequency can be changed while audio is present. Table 2 lists the recommended switching
frequencies and shows that the harmonics fall outside the associated AM frequency band which avoids
tones in the AM band.
Table 2. Recommended Switching Frequencies for AM Mode Operation
US EUROPEAN
AM FREQUENCY (kHz) SWITCHING FREQUENCY AM FREQUENCY (kHz) SWITCHING FREQUENCY
(kHz) (kHz)
522 to 540 417
540 to 917 500 540 to 914 500
917 to 1125 417 914 to 1122 417
1125 to 1375 500 1122 to 1373 500
1375 to 1547 417 1373 to 1548 417
1547 to 1700 357 1548 to 1701 357
1.3.3 Spread Spectrum Oscillator
Situations occur where the AM-tuned frequency is not available in the system. In these situations potential
interference can be overcome by creating an oscillator that varies slightly over time which is typically
called spread spectrum or dither. The oscillator in the TAS54x4C devices can be dithered by changing the
current in the REXT pin. The current in the REXT pin can be varied by up to ±2.5% of the nominal value
without sacrificing functionality. This variation moves the oscillator frequency enough to avoid the AM
receiver from locking on the frequency and producing a tone. The next design characteristic for dither is to
determine the dither frequency or how fast the REXT pin current changes. Any change in the PWM
frequency is demodulated as an output signal. Because the TAS54x4C devices have feedback this
change is reduced by the amount of feedback in the amplifier. The TAS54x4C devices have the greatest
amount of open loop gain at DC and will therefore have the greatest amount of feedback at DC.
Obviously, DC cannot work, so using a frequency close to DC, but not so low the AM interference is not
eliminated. Testing proves that 15 to 20 Hz is a good frequency. The optimum dither oscillator shape is a
triangle wave. The dithered oscillator tracks the voltage change of this low frequency oscillator. The linear
ramps with the abrupt changes of a triangle wave will provide the best spread spectrum oscillator.
The EMI measurements can be improved with spread spectrum oscillators. The results vary depending on
the type of measurement. Peak measurements typically do not show any improvements in the
measurements, but quasi-peak measurements may improve the EMI by 6 to 10 dB.
1.4 Output
Class D amplifiers require special consideration when working with the output stages. These amplifiers
require a proper demodulation filter in order to recover the audio signal with a flat frequency response. In
the TAS54x4C devices the output stages are BTL so the demodulation filter must be a fully balanced filter.
Another issue regarding the recovery of a quality audio signal is overshoot on the PWM signal. Overshoot
can be reduced using snubbers.
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Rx
R(SNUBBER)
Cx
C(SNUBBER)
C(BYPASS)
0.1 µF
PVDD
High-side FET current-loop
Low-side FET
current-loop
Q2
Low-side FET
Q1
High-side FET
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1.4.1 Snubbers
A snubber is an RC network placed at the output of the amplifier to perform several tasks. The snubber
will damp any ringing or overshoot on the PWM output waveform. Overshoot can over voltage stress the
MOSFETs. The overshoot and ringing are also potential sources of EMI. The overshoot and ringing are
caused by the stray inductance in the IC leads, IC bondwires, and PCB traces. The current stored in these
inductances must have a low impedance drainage path to ground. If a path is not provided the stored
current will find a path through parasitic capacitance on the PCB and cause the overshoot and ringing.
Another property of the snubber is the reduction of the total harmonic distortion (THD) of the amplifier. The
overshoot and ringing at the output is present in the feedback signal to the amplifier. The amplifier must
then try to eliminate this overshoot and ringing from the signal. The amplifier cannot completely remove
this signal which is then present on the output as distortion.
To calculate the proper output snubber, measure the voltage spike at the output pin. Use section 4 in
Voltage Spike Measurement Technique and Specification,SLEA025, as a reference on performing this
measurement.
Figure 3 shows the basic output circuit. A bypass capacitor, C(BYPASS), must be included in the design
because it is part of the current path for snubbing the inductance of the high-side FET. The terminals of
C(BYPASS) must be close to the PVDD pins and the PGND pins of the IC. Rxand Cxshould be close to the
output pin and the PGND pins of the IC. This necessary to reduce the series inductance of the PCB
traces. The current loops that are formed by Rxand Cxare labeled in Figure 3 as High-side FET current-
loop and Low-side FET current-loop. If Rxand Cxare not present, the current stored in the drain, source,
and lead inductances have no place to sink to during dead time. This current then flows through parasitic
capacitances on the PCB and appears on the waveform as ringing. Good control of the high-side and low-
side current loops is necessary for good over-voltage protection because of spikes and for good EMI
results.
Figure 3. One-Half of the Typical Output Stage With Snubbers
Use a value of Rxthat is a little higher than the estimate value. A good starting Rxvalue for the
TAS5414C and TAS5424C device is 10 Ω. Use surface mounted devices (SMD) because the series
inductance (ESL) is low.
For Cxselect a small value of 470 pF to 1000 pF. Also use SMD parts. Use the techniques listed in this
design guide to measure the spike and the associated ringing. Measure the frequency of the ringing. If
there is no ringing, use a higher value resistor for Rxor a smaller capacitor for Cx. The final Cxshould be
labeled as C1 and the ringing frequency is ƒ1.
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C(DM)
C(CM)
C(CM)
Load (RL)
L
L
 
2 2 2
2 1
1 1 1
L& &  ¦ ¦
ª º ª º
« » 
« »
 u u S
« » « »
¬ ¼
¬ ¼
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Change Cxto a value that is about 1.5 to 2 times the previous value. Keep Rxthe same. Again, measure
the frequency of the ringing on the waveform. If no ringing is available to measure, change Cxto a slightly
smaller value. The value of Cxshould be labeled as C2 and the ringing frequency is ƒ2.
Use Equation 3 to calculate the value for L.
where
• L is the value of the stray inductance that should be snubbed (3)
L is a bulk inductance and is not any individual inductance.
Find the appropriate values of Cxand Rx. Use Equation 4 to calculate the appropriate Rx.
Rx= 2 × π× ƒx× L
where
• ƒxcorresponds with the selected value of Cx(4)
If C1 is used then use ƒ1, and if C2 is used, then use ƒ2.
To account for tolerances and differences in production units, use a value that is 0.7 to 0.8 of the
calculated Rx. Too high a value for the Rxcould allow for a spike, but too low of a value for Rxcould
cause the snubber to draw excessive current and overheat. Use Equation 5 to calculate the power loss in
the resistor.
P = Cx× V2× ƒS
where
• V is the voltage at PVDD
• ƒSis the switching frequency (5)
1.4.2 Demodulation Filter Design
An output LC-demodulation filter is required to reconstruct the audio signal and protect the amplifier. The
components must be carefully selected for proper operation of the Class-D amplifier. The inductor is
especially of concern because an improper inductor can cause a class-D amplifier to shutdown or fail.
The circuit consists of two inductors and three capacitors as shown in Figure 4. The main demodulation
filter consists of the two inductors, L, and the difference mode capacitor, CDM. The two common mode
capacitors, CCM, filter any common mode signals from the switching waveform.
Figure 4. Typical Output Demodulation Filter
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Inductance (µH)
Current and Q factor (A)
10 µH
5 µH
4 A 8 A
Q = 35
Q = 15
Q = 60
Causes High THD
Core Saturation
Initial Inductance
2 A
0 A 6 A 10 A
11 µH
9 µH
8 µH
7 µH
6 µH
4 µH
3 µH
2 µH
1 µH
High Q
Moderate Q
Low Q
L
co
R
Q ¦ /
u S u u
2L
2co
L
R
2 Q L
C L  ¦ 4
R
u u
u S u u
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The calculation of these components is based on the nominal load impedance RLand the desired
frequency response. The frequency response is dependent on two values, the cutoff frequency and a
characteristic of the roll-off.
where
• Q = a characteristic of the ƒCO roll-off
• ƒCO = the cutoff frequency (6)
For a typical amplifier response the value of Q should be 0.7071
The unloaded condition of the TAS54xx family of devices must be understood. The Q of the filter is
directly proportional to the load. In an unloaded condition the load resistance is infinity and therefore the
value of Q would be infinity also. See Equation 7.
(7)
The peak of the Q value is located at ƒCO. The signal at this frequency is greatly amplified and can be
measured on an oscilloscope. This signal is seen as a sine wave and can be mistaken as an oscillating
amplifier.
1.5 Component Selection
1.5.1 Inductors
When the inductance value has been determined, three additional specifications must still be considered
when specifying an inductor. Aside from the inductance, the Q factor, current rating, and DC resistance
(RDC) values must be considered. Do not confuse the inductor Q with filter Q; these are two different
parameters.
The inductance value is usually specified at 0 A which is typically called the initial inductance. A typical
tolerance is 20%. As current increases through the inductor, the inductance eventually decrease because
of the Q Factor.
Figure 5. Inductance Versus Current and Q Factor
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