Texas Instruments TPA3008D2 User manual

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FEATURES DESCRIPTION
APPLICATIONS
10 µF
220 nF 220 nF
PVCC PVCC
220 nF 220 nF
PVCC PVCC
220 pF
Left Differential
Inputs
Right Differential
Inputs
Shutdown/Mute
Gain
Control
BSLP
PVCCL PVCCL
LOUTP LOUTP
PGNDL
PGNDL LOUTN
LOUTN PVCCL
PVCCL BSLN
TPA3008D2
VCLAMPR
SHUTDOWN
V2P5
RINP
LINN
LINP
AVDDREF
NC
GAIN0
GAIN1
NC
NC
AVDD
AGND
COSC
ROSC
AVCC
VCLAMPL
BSRP
PVCCR PVCCR
ROUTP ROUTP
PGNDR PGNDR
ROUTN ROUTN PVCCR PVCCR
BSRN
RINN
AVCC
AGND
10 µF
0.1 µF0.1 µF
0.47 µF
0.47 µF
0.47 µF
0.47 µF
0.47 µF
0.1 µF0.1 µF
10 µF10 µF
1 µF
120 kΩ
1 µF
NC
NC
NC
FAULT
0.1 µF10 µF
1 µF
Control
†Optional output filter for EMI suppression
†
TPA3008D2
SLOS435A – MAY 2004 – REVISED JULY 2004
10-W STEREO CLASS-D AUDIO POWER AMPLIFIER
•10-W/Channel Into an 16-ΩLoad From a
The TPA3008D2 is a 10-W (per channel) efficient,17-V Supply
class-D audio amplifier for driving bridged-tied stereospeakers. The TPA3008D2 can drive stereo speakers•Up to 92% Efficient, Class-D Operation
as low as 8 Ω. The high efficiency of the TPA3008D2Eliminates Need For Heatsinks
eliminates the need for external heatsinks when•8.5-V to 18-V Single-Supply Operation
playing music.•Four Selectable, Fixed Gain Settings
The gain of the amplifier is controlled by two gain•Differential Inputs Minimizes Common-Mode
select pins. The gain selections are 15.3, 21.2, 27.2,Noise
and 31.8 dB.•Space-Saving, Thermally Enhanced
The outputs are fully protected against shorts toPowerPAD™ Packaging
GND, VCC, and output-to-output shorts. A fault ter-•Thermal and Short-Circuit Protection
minal allows short-circuit fault reporting and automaticWith Auto Recovery Option
recovery. Thermal protection ensures that the maxi-mum junction temperature is not exceeded.•Pinout Similar to TPA3000D Family
•LCD Monitors and TVs•All-In-One PCs
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 2004, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.

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ABSOLUTE MAXIMUM RATINGS
DISSIPATION RATING TABLE
RECOMMENDED OPERATING CONDITIONS
TPA3008D2
SLOS435A – MAY 2004 – REVISED JULY 2004
These devices have limited built-in ESD protection. The leads should be shorted together or the deviceplaced in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
over operating free-air temperature range (unless otherwise noted)
(1)
TPA3008D2
Supply voltage range AV
CC
, PV
CC
-0.3 V to 20 VLoad Impedance, R
L
≥6ΩSHUTDOWN -0.3 V to VCC + 0.3 VInput voltage range, V
I
GAIN0, GAIN1, RINN, RINP, LINN, LINP -0.3 V to 6 VContinuous total power dissipation See Dissipation Rating TableOperating free–air temperature range, T
A
- 40°C to 85°COperating junction temperature range, T
J
- 40°C to 150°CStorage temperature range, T
stg
- 65°C to 150°CLead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operatingconditions” is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
DERATINGPACKAGE T
A
≤25°Cθ
JC
FACTOR T
A
= 70°C T
A
= 85°C(1/θ
JA
)
PHP 4.3 W 1.14 °C/W
(1)
34.7 mW/°C
(1)
2.7 W 2.2 W
(1) Based on a JEDEC high-K PCB with the PowerPAD™ soldered to a thermal land on theprinted-circuit board. See the PowerPAD Thermally Enhanced Package application note (SLMA002).The PowerPAD must be soldered to the PCB.
T
A
= 25°C (unless otherwise noted)
MIN MAX UNIT
Supply voltage, V
CC
PV
CC
, AV
CC
8.5 18 VHigh-level input voltage, V
IH
SHUTDOWN, GAIN0, GAIN1 2 VLow-level input voltage, V
IL
SHUTDOWN, GAIN0, GAIN1 0.8 VSHUTDOWN, V
I
= V
CC
= 18 V 10 µAHigh-level input current, I
IH
GAIN0, GAIN1, V
I
= 5.5 V, V
CC
= 18 V 1 µASHUTDOWN, V
I
= 0 V, V
CC
= 18 V 1 µALow-level input current, I
IL
GAIN0, GAIN1, V
I
= 5.5 V, V
CC
= 18 V 1 µAHigh-level output voltage, V
OH
FAULT, I
OH
= 100 µA AV
DD
- 0.8 V VLow-level output voltage, V
OL
FAULT, I
OL
= -100 µA AGND + 0.8 V VFrequency is set by selection of ROSC and COSCOscillator frequency, f
OSC
200 300 kHz(see the Application Information Section).Operating free–air temperature, T
A
-40 85 °C
2

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AVAILABLE OPTIONS
DC ELECTRICAL CHARACTERISTICS
AC ELECTRICAL CHARACTERISTICS
TPA3008D2
SLOS435A – MAY 2004 – REVISED JULY 2004
T
A
PACKAGED DEVICE48-PIN HTQFP (PHP)
(1)
-40°C to 85°C TPA3008D2PHP
(1) The PHP package is available taped and reeled. To order a tapedand reeled part, add the suffix R to the part number (e.g.,TPA3008D2PHPR).
T
A
= 25°C, V
CC
= 12 V, R
L
= 8 Ω(unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Class-D output offset voltage INN and INP connected together,|V
OO
| 2 5 55 mV(measured differentially) Gain = 31.8 dBV2P5 2.5-V Bias voltage No load 2.5 VI
L
= 10 mA, SHUTDOWN = 2 V,AV
DD
+5-V internal supply voltage 4.5 5 5.5 VV
CC
= 8.5 V to 18 VPSRR Power supply rejection ratio V
CC
= 11.5 V to 12.5 V -76 dBI
CC
Quiescent supply current SHUTDOWN = 2 V, no load 11 22 mAQuiescent supply current in shut-I
CC(SD)
SHUTDOWN = 0 V 1.6 25 µAdown mode
High side 600V
CC
= 12 V,r
DS(on)
Drain-source on-state resistance I
O
= 1 A, Low side 500 mΩT
J
= 25°C
Total 1100 1300GAIN0 = 0.8 V 14.6 15.3 16.2GAIN1 = 0.8 V
GAIN0 = 2 V 20.5 21.2 21.8G Gain dBGAIN0 = 0.8 V 26.4 27.2 27.8GAIN1 = 2 V
GAIN0 = 2 V 31.1 31.8 32.5t
on
Turnon time C
(V2P5)
= 1 µF, SHUTDOWN = 2 V 16 mst
off
Turnoff time C
(V2P5)
= 1 µF, SHUTDOWN = 0.8 V 60 µs
T
A
= 25°C, V
CC
= 12 V, R
L
= 8 Ω, (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
200 mV
PP
ripple from 20 Hz to 1 kHz,k
SVR
Supply voltage rejection ratio -70 dBGain = 15.6 dB, Inputs ac-coupled to GNDTHD+N = 0.13%, f = 1 kHz, R
L
= 8 Ω5THD+N = 10%, f = 1 kHz, R
L
= 8 Ω8.5THD+N = 0.16%, f = 1 kHz, R
L
= 16 Ω,P
O
Continuous output power W5V
CC
= 17 VTHD+N = 10%, f = 1 kHz, R
L
= 16 Ω,
10V
CC
= 17 VTotal harmonic distortion plusTHD+N P
O
= 1 W, f = 1 kHz, R
L
= 8 Ω0.1%noise
20 Hz to 22 kHz, A-weighted filter,V
n
Output integrated noise floor -80 dBGain = 15.6 dBCrosstalk P
O
= 1 W, R
L
= 8 Ω, Gain = 15.6 dB, -93 dBf = 1 kHzMaximum output at THD+N < 0.5%,SNR Signal-to-noise ratio 97 dBf = 1 kHz, Gain = 15.6 dBThermal trip point 150 °CThermal hystersis 20 °C
3

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Biases
and
References
TTL Input
Buffer
(VCC Compl)
Start-up and
Protection
Logic
SC
Detect
Thermal
VDDok
RINP
RINN
Ramp
Generator
COSC
ROSC
VCCok
5-V LDO
AVCC
AVDD
AVDD
VDD
and
PWM
Mode
Logic
Gain
Adj.
Gain
Control
Deglitch
and
PWM
Mode
Logic
Gain
Adj.
LINP
LINN
Gate
Drive
VClamp
Gen
Gate
Drive
PVCC
BSRP
PVCCR(2)
ROUTP(2)
PGNDR
PGNDR
ROUTN(2)
PVCCR(2)
BSRN
Gate
Drive
VClamp
Gen
Gate
Drive
PVCC
BSLP
PVCCL(2)
LOUTP(2)
PGNDL
PGNDL
LOUTN(2)
PVCCL(2)
BSLN
VCLAMPL
VCLAMPR
GAIN0 4To Gain Adj.
Blocks and
Start-up Logic
SHUTDOWN
V2P5
V2P5 V2P5
AVCC
AGND(2)
V2P5
V2P5
Deglitch
GAIN1
AVDDREF
FAULT
TPA3008D2
SLOS435A – MAY 2004 – REVISED JULY 2004
FUNCTIONAL BLOCK DIAGRAM
4

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13 14 15 16 17 18 19 20 21 22 23 24
25
26
27
28
29
30
31
32
33
34
35
36
48 47 46 45 44 43 42 41 40 39 38 37
1
2
3
4
5
6
7
8
9
10
11
12
BSRN PVCCR PVCCR ROUTN ROUTN PGNDR PGNDR ROUTP ROUTP PVCCR PVCCR BSRP
VCLAMPR
NC
NC
NC
NC
AGND
COSC
ROSC
AGND
VCLAMPL
SHUTDOWN
RINN
RINP
V2P5
LINP
LINN
NC
GAIN0
GAIN1
FAULT
NC
BSLN
PVCCL PVCCL
LOUTN LOUTN
PGNDL PGNDL
LOUTP LOUTP PVCCL PVCCL
BSLP
TPA3008D2
AVCC
AVDD
AVDDREF
TPA3008D2
SLOS435A – MAY 2004 – REVISED JULY 2004
PHP PACKAGE
(TOP VIEW)
5

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TPA3008D2
SLOS435A – MAY 2004 – REVISED JULY 2004
TERMINAL FUNCTIONS
PIN NAME PIN NUMBER I/O DESCRIPTION
AGND 26, 30 - Analog ground for digital/analog cells in coreAV
CC
33 - High-voltage analog power supply, not connected internally to PVCCR or PVCCL5-V Regulated output for use by internal cells and GAIN0, GAIN1 pins only. NotAV
DD
29 O
specified for driving other external circuitry.AV
DD
REF 7 O 5-V Reference output—connect to gain setting resistor or directly to GAIN0, GAIN1.BSLN 13 - Bootstrap I/O for left channel, negative high-side FETBSLP 24 - Bootstrap I/O for left channel, positive high-side FETBSRN 48 - Bootstrap I/O for right channel, negative high-side FETBSRP 37 - Bootstrap I/O for right channel, positive high-side FETCOSC 28 I/O I/O for charge/discharging currents onto capacitor for ramp generator.Short-circuit detect fault output.FAULT = high, short-circuit detected.FAULT 11 O
FAULT = low, normal operation.Status is reset when power is cycled or SHUTDOWN is cycled.GAIN0 9 I Gain select least significant bit. TTL logic levels with compliance to AV
DD
.GAIN1 10 I Gain select most significant bit. TTL logic levels with compliance to AV
DD
.LINN 6 I Negative audio input for left channelLINP 5 I Positive audio input for left channelLOUTN 16, 17 O Class-D 1/2-H-bridge negative output for left channelLOUTP 20, 21 O Class-D 1/2-H-bridge positive output for left channel8, 12, 31, 32,NC - No internal connection34, 35PGNDL 18, 19 - Power ground for left channel H-bridgePGNDR 42, 43 - Power ground for right channel H-bridgePower supply for left channel H-bridge (internally connected to pins 22 and 23), notPVCCL 14, 15 -
connected to PVCCR or AV
CC
.Power supply for left channel H-bridge (internally connected to pins 14 and 15), notPVCCL 22, 23 -
connected to PVCCR or AV
CC
.Power supply for right channel H-bridge (internally connected to pins 46 and 47),PVCCR 38, 39 -
not connected to PVCCL or AV
CC
.Power supply for right channel H-bridge (internally connected to pins 38 and 39),PVCCR 46, 47 -
not connected to PVCCL or AV
CC
.RINP 3 I Positive audio input for right channelRINN 2 I Negative audio input for right channelROSC 27 I/O I/O current setting resistor for ramp generator.ROUTN 44, 45 O Class-D 1/2-H-bridge negative output for right channelROUTP 40, 41 O Class-D 1/2-H-bridge positive output for right channelShutdown signal for IC (low = shutdown, high = operational). TTL logic levels withSHUTDOWN 1 I
compliance to V
CC
.VCLAMPL 25 - Internally generated voltage supply for left channel bootstrap capacitors.VCLAMPR 36 - Internally generated voltage supply for right channel bootstrap capacitors.V2P5 4 O 2.5-V Reference for analog cells.Connect to AGND and PGND—should be the center point for both grounds. InternalThermal Pad - -
resistive connection to AGND.
6

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TYPICAL CHARACTERISTICS
0.01 20 20 k
100 1 k 10 k
THD+N −Total Harmonic Distortion + Noise − %
VCC = 18 V,
RL= 16 
Gain = 21.6 dB
f − Frequency − Hz
10
0.1
PO= 2.5 W
PO= 0.5 W
PO= 1 W
1
0.005
10
0.01
0.1
20 20 k 100 1 k 10 k
PO= 2.5 W
THD+N −Total Harmonic Distortion + Noise − %
VCC = 12 V,
RL= 16 ,
Gain = 21.6 dB
f − Frequency − Hz
PO= 1 W
1
PO= 0.5 W
TPA3008D2
SLOS435A – MAY 2004 – REVISED JULY 2004
TABLE OF GRAPHS
FIGURE
THD+N Total harmonic distortion + noise vs Frequency 1, 2, 3, 4THD+N Total harmonic distortion + noise vs Output power 5, 6Closed-loop response 7Output power vs Supply voltage 8, 9Efficiency vs Output power 10Efficiency vs Total output power 11V
CC
Supply current vs Total output power 12Crosstalk vs Frequency 13k
SVR
Supply ripple rejection ratio vs Frequency 14CMRR Commom-mode rejection ratio vs Frequency 15
TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISEvs vsFREQUENCY FREQUENCY
Figure 1. Figure 2.
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0.005
10
0.01
0.1
20 20 k 100 1 k 10 k
PO= 5 W
THD+N −Total Harmonic Distortion + Noise − %
VCC = 18 V,
RL= 8 ,
Gain = 21.6 dB
f − Frequency − Hz
PO= 1 W
PO= 2.5 W
1
0.01
0.1
10
20 20 k 100 1 k 10 k
THD+N −Total Harmonic Distortion + Noise − %
VCC = 12 V,
RL= 8 
Gain = 21.6 dB
f − Frequency − Hz
PO= 1 W
PO= 2.5 W
PO= 0.5 W
1
0.01
10
0.1
1
20m 10100 m 1
THD+N −Total Harmonic Distortion + Noise − %
PO− Output Power − W
VCC = 12 V,
RL= 8 ,
Gain = 21.6 dB
20200 m 2
1 kHz
20
20 Hz
20 kHz
0.01
10
0.1
1
20m 10100 m 1
THD+N −Total Harmonic Distortion + Noise − %
PO− Output Power − W
VCC = 18 V,
RL= 16 ,
Gain = 21.6 dB
20 Hz
20200 m 2
20 kHz
1 kHz
TPA3008D2
SLOS435A – MAY 2004 – REVISED JULY 2004
TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISEvs vsFREQUENCY FREQUENCY
Figure 3. Figure 4.
TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISEvs vsOUTPUT POWER OUTPUT POWER
Figure 5. Figure 6.
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28
24
20
16
10 100 1k
Gain − dB
32
36
f − Frequency − Hz
40
10k
12
8
4
080k
VCC = 12 V,
RL= 8 Ω,
Gain = 32 dB
33 kHz, RC LPF
Gain
Phase
Phase −
50
0
100
−150

−100
−50
150
0
1
2
3
4
5
6
7
8
9
10
11
12
8 9 10 11 12 13 14 15 16 17 18
PO− Output Power − W
THD+N = 10%
THD+N = 1%
RL= 16 
VCC − Supply Voltage − V
2
3
4
5
6
7
8
9
8 9 10 11 12 13 14
THD+N = 1%
THD+N = 10%
RL= 8 
VCC − Supply Voltage − V
PO− Output Power − W
10
11
12
Power represented by dashed line
may require external heatsinking
0
10
20
30
40
50
60
70
0 1 2 3 4 5 6
PO− Output Power (Per Channel) − W
Efficiency − %
80
90
100
7 8 9 10
VCC = 18 V,
RL= 16 
TPA3008D2
SLOS435A – MAY 2004 – REVISED JULY 2004
OUTPUT POWER
vsCLOSED-LOOP RESPONSE SUPPLY VOLTAGE
Figure 7. Figure 8.
OUTPUT POWER EFFICIENCYvs vsSUPPLY VOLTAGE OUTPUT POWER
Figure 9. Figure 10.
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0
10
20
30
40
50
60
70
80
90
100
0 1 2 3 4 5 6 7 8 9 10
Efficiency − %
16 
8 
PO− Total Output Power − W
11 12
VCC = 12 V,
LC Filter,
Resistive Load,
Stereo Operation
0
0.2
0.4
0.6
0.8
1
1.2
1.4
0 2 4 6 8 10 12
PO− Total Output Power − W
1.6
1.8
2.0
14 16 18 20
LC Filter,
Resistive Load,
Stereo Operation
− Supply Current − AVCC
VCC = 18 V,
RL= 16 
VCC = 12 V,
RL= 16 
VCC = 12 V,
RL= 8 
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
20 100 1 k 10 k
Crosstalk − dB
f − Frequency − Hz
VCC = 12 V,
PO= 2.5 W,
Gain = 21.6 dB
RL= 8
20 k
−100
−90
−80
−70
−60
−50
−40
20 100 1 k 10 k
f − Frequency − Hz
kSVR − Supply Ripple Rejection Ratio − dB
VCC = 12 V,
V(RIPPLE) = 200 mVPP,
RL= 8 ,
Gain = 15.6 dB
20 k
−30
−20
−10
0
TPA3008D2
SLOS435A – MAY 2004 – REVISED JULY 2004
EFFICIENCY SUPPLY CURRENTvs vsTOTAL OUTPUT POWER TOTAL OUTPUT POWER
Figure 11. Figure 12.
CROSSTALK SUPPLY RIPPLE REJECTION RATIOvs vsFREQUENCY FREQUENCY
Figure 13. Figure 14.
10