Texas Instruments ADC1xD1x00CVAL Series User manual

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ADC1xD1x00CVAL Board User’s Guide
User's Guide
SNAU212–June 2017
ADC1xD1x00CVAL Board User’s Guide
The ADC1xD1x00QML products are low-power, high-performance 10b and 12b ADCs with sampling rates
up to 1.6 GSPS as a dual-channel ADC or 3.2 GSPS in a single-channel interleaved mode. These
products come in a hermetic 376 column ceramic grid array package (376 CCGA) for harsh environments,
such as down hole or space.
Contents
1 Overview ..................................................................................................................... 2
2 Lab Equipment .............................................................................................................. 3
2.1 Required Lab Equipment .......................................................................................... 3
2.2 Optional Lab Equipment .......................................................................................... 4
3 Driving the Clock and Inputs ............................................................................................... 4
3.1 Driving the Sampling Clock........................................................................................ 4
3.2 Driving the Analog Inputs.......................................................................................... 5
4 Jumper Settings.............................................................................................................. 5
5 Board Power Up ............................................................................................................. 6
5.1 Power Supply ....................................................................................................... 6
5.2 Power-Up Sequence ............................................................................................... 6
5.3 VBG Pin.............................................................................................................. 6
5.4 Samtec Connector ................................................................................................. 7
6 Using the AARDVARK ..................................................................................................... 9
7 Importing Data into WaveVision5 ....................................................................................... 12
List of Figures
1 ADC1xD1x00CVAL Board.................................................................................................. 3
2 Flow-Through Routing for the Samtec Connector....................................................................... 7
3 Samtec Connector Footprint ............................................................................................... 8
4 Samtec Connector Ordering Information ................................................................................. 8
5 Aardvark I2C/SPI Host Adapter ........................................................................................... 9
6 Level Translator for Aardvark to ADC .................................................................................... 9
7 Logic Analyzer Data Listing View ........................................................................................ 12
List of Tables
1 Output Data Rate Per Bank by Mode..................................................................................... 4
2 ADC12D16x0 Output Data Rate Example ............................................................................... 4
3 Control Pins and Function.................................................................................................. 5
4 Non-ECM Pin Control Settings............................................................................................. 6
Trademarks
All trademarks are the property of their respective owners.

CAUTION
Caution Hot surface.
Contact may cause burns.
Do not touch.
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ADC1xD1x00CVAL Board User’s Guide
1 Overview
The ADC1xD1x00 Evaluation Board (ADC1xD1x00CVAL) provides flexible ADC I/O connections for
laboratory performance evaluation. As configured, the board is equipped with support shrouds for 100 pin
Samtec connectors for interface to a logic analyzer, but capable of being configured for other types of
logic analyzer connectors.
Because the 10- and 12-bit Gig ADCs are pin-compatible with one another, this board can be used with
the following parts:
• ADC10D1000QML
• ADC12D1600QML
• ADC12D1620QML
Refer to the individual product data sheets for information on the absolute maximum ratings and
recommend operating conditions.
NOTE: The top surface of the ADC (U1) can reach temperatures above 55°C during normal
operation. Use caution and avoid touching the top surface of the ADC when it is operating.

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Figure 1. ADC1xD1x00CVAL Board
2 Lab Equipment
2.1 Required Lab Equipment
The following lab equipment is required to use the ADC1xD1x00 EVAL board:
• Bench supply to drive 1.9 V at 3 A
• 1 signal generator + bandpass filter + balun to drive sampling clock. Suggested equipment:
– SMA100A with B22 enhanced low phase-noise option
– Trilithic 5VF tunable filter
• 1 signal generator to drive the analog input
• High-speed Logic Analyzer to capture the data. Suggested equipment:
– Keysight 16702B Logic Analysis System
– Keysight 16760A Timing and State Module
– Keysight E5379A Differential Probe Adapter
– Keysight E5386A Half-channel Probe Adapter (for data rates greater than 800MSPS)

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Three key requirements for the sampling clock signal generator are low distortion, broad band noise, and
phase noise. Even the highest quality signal generator will also produce harmonics, which the ADC
performance is very sensitive to. Therefore, a bandpass filter, which can be tuned to the desired sampling
clock frequency, will improve the performance of the system. In addition to this, the bandpass filter will
reduce broadband noise and increase the system performance.
The logic analyzer should be able to capture differential LVDS signals at high speed, as determined by the
sampling clock speed and ADC Demux Mode. In general, the Output Data Rate per Bank can be
determined as follows:
Table 1. Output Data Rate Per Bank by Mode
MODE OUTPUT DATA RATE PER BANK [MSPS]
DES 1:1 Non-Demux Fs/2
DES 1:2 Demux Fs/4
Non-DES 1:1 Non-Demux Fs
Non-DES 1:2 Demux Fs/2
For example, the ADC12D16x0 will generate data at the following rates:
Table 2. ADC12D16x0 Output Data Rate Example
MODE FCLK [MHz] FS [MSPS] OUTPUT DATA RATE PER BANK
[MSPS]
DES 1:1 Non-Demux 1600 3200 1600
DES 1:2 Demux 1600 3200 800
Non-DES 1:1 Non-Demux 1600 1600 1600
Non-DES 1:2 Demux 1600 1600 800
The EVAL board is designed to be used with the Samtec ASP-65067-01 for the logic analyzer probe
connection to the Keysight E5379A Differential Probe Adapter. There is also a footprint for the Keysight
E5405A Pro Series Soft Touch Connectorless Probe, but this option is not recommended, as the signal
integrity is better through the Samtec connector.
2.2 Optional Lab Equipment
If the EVAL board is being used in Extended Control Mode (ECM), then it is also necessary to have a
system which can write to the SPI. One option is the Aardvark I2C/SPI Host Adapter and accessories.
• Aardvark I2C/SPI Host Adapter
http://www.totalphase.com/products/aardvark_i2cspi/
• Level Shifter Board
http://www.totalphase.com/products/level_shifter/
• 10-pin Split Cable
http://www.totalphase.com/products/split_cable/
3 Driving the Clock and Inputs
3.1 Driving the Sampling Clock
The CLK± SMA inputs are connected directly to the ADC; they must be driven AC-coupled and
differentially. Therefore, a set of DC blocks is required at the input. To convert a single-ended signal to
differential, a National Anaren balun board (400 MHz to 3 GHz) may conveniently be used.

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3.2 Driving the Analog Inputs
The analog inputs may be driven AC-coupled and must be driven differentially. Depending upon the
application, an amplifier or balun board may be used to achieve single-ended to differential conversion.
4 Jumper Settings
Most of the jumper pins on the EVAL board are also available for customer use, and are more clearly
explained in the datasheet; some exceptions are the TEST pins as described below. These pins are
related to internal test functions and are not available.
The ADC may be used in either Extended Control Mode (ECM) or Non-ECM, also known as pin-control
mode; this is set by the ECEb pin. In ECM, the ADC modes and settings are written through the Serial
Port Interface. Some control pins remain active in ECM.
Table 3. Control Pins and Function
PIN (BOARD) PIN (DATASHEET) I/O FUNCTION
TEST_LP N/A N/A Internal test function; do not connect
ECEB ECEb Input ECM and Non-ECM: Extended
Control Mode Enable bar select
TPN TPM Input Non-ECM only: Test Pattern Mode
select
NDM NDM Input ECM and Non-ECM: Non-Demux
Mode select
TEST_IO N/A N/A Internal test function; do not connect
POR_EN N/A N/A Internal test function; do not connect
DCLK_RST+/- DCLK_RST+/- Input Differential DCLK Reset DES DES Input Non-ECM only: DES Mode
select
LSPSM LSPSM Input Low sampling power saving mode
DDR_PH DDRPh Input Non-ECM only: DDR Phase select
FSR FSR Input Non-ECM only: Full-Scale Range
select
PDQ PDQ Input ECM and Non-ECM: Power-Down
Q-channel
PDI PDI Input ECM and Non-ECM: Power-Down I-
channel
SCSB SCSb Input SPI: Serial Chip Select bar
SDO SDO Output SPI: Serial Data Out
SDI SDI Input SPI: Serial Data In
SCLK SCLK Input SPI: Serial Clock
TEST_RSV1 N/A N/A Internal test function; do not connect
TEST_RSV2 N/A N/A Internal test function; do not connect
TDIODE TDIODE+/- Output Temperature Sensor Diode
terminals
CALRUN CalRun Output Calibration Running indication
VBG VBG I/O Bandgap Voltage Output / LVDS
Common-mode Voltage select
TEST_CF N/A N/A Internal test function; do not connect
RCLK RCLK+/- Input AutoSync: Reference Clock Input
RCOUT1 RCOut1+/- Output AutoSync: Reference Clock
Differential Output 1
RCOUT2 RCOut2+/- Output AutoSync: Reference Clock
Differential Output 2
In Non-ECM, the following control pins are available.

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Table 4. Non-ECM Pin Control Settings
PIN (BOARD) LOW HIGH FLOATING
ECEB ECM Non-ECM Not valid
TPN Non-TPM TPM Not valid
NDM 1:2 Demux 1:1 NDM Not valid
DES Non-DES DES Not valid
LSPSM Normal Low sampling power saving Not valid
DDR_PH 0˚Mode 90˚Mode Not valid
FSR See data sheet for details Not valid
PDQ Q-channel active Power-Down Q-channel Not valid
PDI I-channel active Power-Down I-channel Not valid
VBG N/A Higher LVDS common-mode
voltage Lower LVDS common-mode voltage
5 Board Power Up
Refer to the individual product data sheets for information about the absolute maximum ratings and
recommend operating conditions.
5.1 Power Supply
For flexibility, each of the different ADC power supply pins has been brought out to a red PWR terminal. TI
recommends powering all supply pins from a single power-supply source. The supply voltage to any of the
PWR terminals must not exceed that applied to X-1 PWR (VA). The supply voltage is a nominal 1.9 V and
should not exceed 2 V.
5.2 Power-Up Sequence
The ADC should be powered up in Non-ECM, by putting the ECEB pin high. The ADC does not have a
Power-on-Reset. If the part is started in extended control mode (ECM), by having the ECEB pin low, the
registers will come up in an unknown random state, and the part will be in an unknown operating
condition. If ECM mode is desired, the board can be placed in ECM by moving the ECEB pin low after
power up with the ECEB pin high.
After the board has stabilized, the ADC should be calibrated by flipping the red CAL switch from low
(CALb) to high (CAL). If the switch remains high, the part cannot be recalibrated in ECM. To enable the
part to be recalibrated, in either ECM or with the switch, the CAL switch must be low (CALb). Recalibrate
the part when there has been a major change in operating conditions, such as change in Fclk, or
temperature.
5.3 VBG Pin
Some versions of this universal board allow for the option to put the VBG pin low. This not a supported
state, and the VBG pin should not be taken low.

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5.4 Samtec Connector
Figure 2. Flow-Through Routing for the Samtec Connector

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5.4.1 Footprint Dimensions
Figure 3. Samtec Connector Footprint
Figure 4. Samtec Connector Ordering Information

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6 Using the AARDVARK
The Aardvark I2C/SPI Host Adapter is a fast and powerful I2C bus and SPI bus host adapter through USB
(see Figure 5). It allows a developer to interface a Linux or Windows PC to a downstream embedded
system environment and transfer serial messages using the I2C and SPI protocols.
Part Number: TP240141
RoHS Compliant: Yes
Figure 5. Aardvark I2C/SPI Host Adapter
For more information, visit the manufacturer website at:
http://www.totalphase.com/products/aardvark_i2cspi/
Level translation is required due to the different signaling levels (3.3 V for the Aardvark vs. 1.9 V for the
ADC). A level shifter can be obtained from Total Phase or can be built as shown Figure 6.
Figure 6. Level Translator for Aardvark to ADC
1. Download the Aardvark control GUI software
(a) Go to: http://www.totalphase.com/products/aardvark_i2cspi/ and select the Downloads tab.
(b) Download and install the Control Center Software.
2. Configure and connect the hardware
(a) Put the ADC into Extended Control Mode (ECM) by setting the ECEB jumper to GND.

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(b) The I2C/SPI Level Shifter board should have jumpers at TPWR, MASTER, and 1.8 V. (The Gig
ADC runs at 1.9 V, but 1.8 V is appropriately close.)
(c) Connect a USB cable from the PC to the Aardvark
(d) Connect the Aardvark cable to the I2C/SPI Level Shifter board, ADAPTER input
(e) Connect the additionally supplied ribbon cable from the I2C/SPI Level Shifter board, TARGET1 port
to the ribbon cable with split outputs
(f) Connect the split output wires to the ADC EVAL board
(i) SS (white) = SCSb
(ii) MOSI (grey) = SDI
(iii) SCLK (purple) = SCLK iv. GND (black) = GND
3. Configure the Aardvark software
(a) Select Configure Aardvark Adapter
(b) Select anywhere on the row of the available port, select the SPI – GPIO radio button and hit OK