Texas Instruments PCI2250 User manual


 
2000 PCI Bus Solutions
User’s Guide
SCPU005

IMPORTANT NOTICE
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
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performed, except those mandated by government requirements.
Customers are responsible for their applications using TI components.
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safeguards must be provided by the customer to minimize inherent or procedural hazards.
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Copyright 2000, Texas Instruments Incorporated

Information About Cautions and Warnings
iii
Read This First
Preface
Read This First
About This Manual
This manual is designed to assist the user of the PCI2250 evaluation module
(EVM). Itprovidesdescriptionsofparts,features,andoperatingrequirements
of the EVM that are necessary or useful to obtain maximum benefit from EVM
use.
How to Use This Manual
This document contains the following chapters:
Chapter 1,
Introduction , provides a brief description of the EVM, and a bill of
materials for the EVM kit.
Chapter 2, Software Requirements , details the minimum software
requirements for any PC system on which the PCI2250 EVM is to be run.
Chapter 3, Configuration , explains secondary bus masters and interrupt
routing as related to the edge connectors on the board.
Chapter 4,
Board Configuration , describes the location and purpose of board
components such as pins, jumpers, connectors, and LEDs.
Information About Cautions and Warnings
This book may contain cautions and warnings.
This is an example of a caution statement.
A caution statement describes a situation that could potentially
damage your software or equipment.
This is an example of a warning statement.
A warning statement describes a situation that could potentially
cause harm to you.

Trademarks
iv
The information in a caution or a warning is provided for your protection.
Please read each caution and warning carefully.
Related Documentation From Texas Instruments
PCI2250 PCI-to-PCI Bridge Data Manual , TI Literature Number – SCPS051
PCI2250 Implementation Guide , SCPU008
Connecting ENUM Terminal to an External Open-Drain Buffer , TI Literature
Number – SCPA027
FCC Warning
Thisequipmentisintendedforuseinalaboratorytestenvironmentonly.Itgen-
erates,uses,andcanradiateradiofrequencyenergy and has not been tested
for compliance with the limits of computing devices pursuant to subpart J of
part 15 of FCC rules, which are designed to provide reasonable protection
against radio frequency interference. Operation of this equipment in other en-
vironmentsmaycauseinterferencewithradio communications, in which case
the user at his own expense will be required to take whatever measures may
be required to correct this interference.
Trademarks
Intel is a trademark of Intel Corporation.
Windows is a trademark of Microsoft Corporation. (Windows95, Windows)
Windows NT is a trademark of Microsoft Corporation. (Windows NT)
CompactPCI is a trademark of PICMG – PCI Industrial Computer Manufacturers Group, Inc.
Other trademarks are the property of their respective owners.

Running Title—Attribute Reference
v
Chapter Title—Attribute Reference
Contents
1 Introduction 1-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1 Introduction 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 Evaluation Kit Bill of Materials 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 Software Requirements 2-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1 Software Requirements 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 Configuration 3-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1 Configuration 3-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4 Board Configuration 4-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1 Board Jumpers 4-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2 PCI2250 Mode Select Pins 4-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.1 Clock Run Mode 4-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.2 CompactPCIHot Swap 4-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.3 IntelMode 4-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3 LED Indicators 4-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3.1 D1 ENUM 4-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3.2 D2 HSLED 4-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3.3 D3 C1_PRES 4-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3.4 D4 C2_PRES 4-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3.5 D5 C3_PRES 4-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3.6 D6 EVM3V 4-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3.7 D7 PCU3V 4-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4 Power Measurements 4-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5 Mictor Connector Definition 4-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.6 Board Description 4-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Running Title—Attribute Reference
vi
Figures
4–1 Part and Jumper Locations 4-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–2 Schematic Diagram 4-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Tables
3–1 Edge Connector Device ID 3-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–2 Edge Connector Interrupt Routing 3-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–1 Jumper Definitions 4-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–2 Mode Select Jumper Settings 4-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–3 HP Logic Analyzer POD Definition 4-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–4 PCI2250 EVM Bill of Materials 4-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-1
Introduction
This chapter provides a brief overview of the PCI2250 evaluation module,
along with a bill of materials for the EVM kit.
Topic Page
1.1 Introduction 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 Evaluation Kit Bill of Materials 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 1

Introduction
1-2
1.1 Introduction
ThisdocumentisintendedtoassisttheuserofthePCI2250evaluationmodule
(EVM), EVM2250B. Included within this document are instructions detailing
the proper setup and configuration necessary to operate the PCI2250 EVM.
1.2 Evaluation Kit Bill of Materials
The PCI2250 EVM consists of the following items:
Item Nomenclature Quantity
EVM2250B PCI to PCI adapter card assembly 1
3.5” Diskette PCIBus and PCIBus95 utility programs 1

2-1
Software Requirements
Software Requirements
Thischapter provides theminimum software requirementsfor any PCsystem
on which the PCI2250 EVM is to be used.
Topic Page
2.1 Software Requirements 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 2

Software Requirements
2-2
2.1 Software Requirements
The EVM2250B evaluation board will work in any system that meets the
following requirements:
BIOS which supports the PCI Bridge Specification 1.0 .
Operating system that supports the PCI Bridge Specification 1.0 .
In the majority of today’s computer systems, bridge support is built into the
BIOS. Many operation systems, like Windows 95/98and Windows NT,
have support for bridges.

3-1
Configuration
Configuration
This chapter explains secondary bus masters and interrupt routing as related
to edge connectors on the board.
Topic Page
3.1 Configuration 3-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 3

Configuration
3-2
3.1 Configuration
ThePCI2250supports four secondary busmasters.Due to board space, only
three masters are supported with the EVM2250B board. The three supported
masters can be plugged into three edge connectors labeled P1, P2, and P3.
These edge connectors are configured based on the Table 3–1.
Table 3–1.Edge Connector Device ID
Edge Connector Resistor Installed Slot ID
P1 R20
R21 (default)
R22
0
4 (default)
8
P2 R23 (default)
R24
R25
1 (default)
5
9
P3 R26 (default)
R27
R28
2 (default)
6
A
The interrupts for each connector on the secondary bus are routed according
to the
PCI Local Bus Specification Revision 2.2 , section 2.2.6. Table 3–2
depicts how the interrupts are routed on the EVM2250B evaluation board.
Table 3–2.Edge Connector Interrupt Routing
Edge Connector Interrupt Routed on INTX on P1
P1 INTA
INTB
INTC
INTD
INTA
INTB
INTC
INTD
P2 INTA
INTB
INTC
INTD
INTB
INTC
INTD
INTA
P3 INTA
INTB
INTC
INTD
INTC
INTD
INTA
INTB

4-1
Board Configuration
Board Configuration
This chapter describes the location and purpose of board components such
as pins, jumpers, connectors, and LEDs.
Topic Page
4.1 Board Jumpers 4-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2 PCI2250 Mode Select Pins 4-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3 LED Indicators 4-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4 Power Measurements 4-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5 Mictor Connector Definition 4-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.6 Board Description 4-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 4

Board Jumpers
4-2
4.1 Board Jumpers
Built into the evaluation board is the ability to monitor and test all the
capabilitiesofthePCI2250.Therearemanyjumperslocatedontheevaluation
board(J1throughJ12),whichallowanengineer to perform tests rangingfrom
measuring power to changing the arbitration of the PCI2250. All of these
jumpers are defined in Table 4–1.
Table 4–1.Jumper Definitions
Jumper Description
J1 P_MFUNC select. This jumper is used to select whether to route
P_MFUNC to P_LOCK or P_CLKRUN/HS_ENUM.
J5 & J6 Jumpers J5 and J6 are used to control the mode select inputs to the
PCI2250.
J7 S_MFUNC select. This jumper is used to select whether to route
S_MFUNC to S_LOCK or S_CLKRUN/HS_SWITCH.
J8 Arbitration support. By cutting the trace across this jumper and installing
R10 an external arbiter can be used.
J9 S_VCCPforthePCI2250.Thisjumpercanbeusedtomeasurethepower
consumed through the S_VCCP.
J10 P_VCCPforthePCI2250.Thisjumpercanbeusedtomeasurethepower
consumed through the P_VCCP.
J11 Core VCC for the PCI2250. This jumper can be used to measure the
power consumed by the PCI2250 core logic.
J12 S_VIO select. This jumper is used to select between 3.3-V and 5.0-V
signaling environments on the secondary bus.

PCI2250 Mode Select Pins
4-3
Board Configuration
4.2 PCI2250 Mode Select Pins
The PCI2250 has three modes of operation based on the value of the mode
select pins MS0 (J6-2) and MS1 (J5-2). Table 4–2 shows the jumper settings
for the different modes of operation.
Table 4–2.Mode Select Jumper Settings
J6 J5 P_MFUNC S_MFUNC Mode
2–3 2–3 HS_ENUM HS_SWITCH TI hot-swap
2–3 1–2 P_CLKRUN S_CLKRUN TI clock run
1–2 2–3 P_LOCK S_LOCK Intel B2 support
1–2 1–2 P_LOCK S_LOCK Intel B3 support
4.2.1 Clock Run Mode
When the PCI2250 is in clock run mode, jumpers J1 and J7 should not be
jumpered.Theclockrunsignalscanbe pulled directly from pin2ofthejumper
headers.
4.2.2 CompactPCIHot Swap
When hot-swap mode is selected, jumpers J1 and J7 should have a jumper
between pins 2 and 3, routing the multifunction pins to the CompactPCI test
points.
4.2.3 IntelMode
When Intel mode is selected, jumpers J1 and J7 should have a jumper
between pins 1 and 2, routing the multifunction pins to the LOCK pins on the
connectors.

LED Indicators
4-4
4.3 LED Indicators
4.3.1 D1 ENUM
When the PCI2250 is configured in CompactPCI mode, this LED lights when
the ENUM signal is driven low.
4.3.2 D2 HSLED
When the PCI2250 is configured in Compact PCI mode, this LED lights when
the HSLED signal is driven low.
4.3.3 D3 C1_PRES
D3lightswhenaPCI board thathasthePRSNT2pintiedtoground isinserted
in connector P1.
4.3.4 D4 C2_PRES
D4lightswhenaPCI board thathasthePRSNT2pintiedtoground isinserted
in connector P2.
4.3.5 D5 C3_PRES
D5lightswhenaPCI board thathasthePRSNT2pintiedtoground isinserted
in connector P3.
4.3.6 D6 EVM3V
D6 lights to indicate that 3.3 V is available on the secondary bus.
4.3.7 D7 PCU3V
D7 lights to indicate that the PCI2250 has power applied to the core logic.
4.4 Power Measurements
In order to measure the current drawn by the core logic or one of the VIO rails
ofthe PCI2250 itis necessary to isolate the power suppliedto these pinsfrom
the rest of the system. This can be done by cutting the trace that connects the
power pins to the system. Jumpers J6, J7, and J8 have default traces that are
provided for this purpose. After the traces are cut, an external power supply
can be used along with a current meter to measure the current used by the
selected power rail. The power rail can then be reconnected to the system by
placing a jumper across the cut trace.

Mictor Connector Definition
4-5
Board Configuration
4.5 Mictor Connector Definition
Connectors MC1 and MC2 can be used to connect a logic analyzer to the
secondary PCI bus. See Table 4–3 for a listing of the signals for each logic
analyzer POD.
Table 4–3.HP Logic Analyzer POD Definition
Pin Number POD 1 POD 2 POD 3 POD 4
0 S_AD0 S_AD16 S_PAR S_REQ64
1 S_AD1 S_AD17 S_SERR S_ACK64
2 S_AD2 S_AD18 S_PERR C1_IDSEL
3 S_AD3 S_AD19 S_STOP C1_GNT
4 S_AD4 S_AD20 S_DEVSEL C1_REQ
5 S_AD5 S_AD21 S_C/BE0 C2_IDSEL
6 S_AD6 S_AD22 S_C/BE1 C2_GNT
7 S_AD7 S_AD23 S_C/BE2 S_FRAME
8 S_AD8 S_AD24 S_C/BE3 S_IRDY
9 S_AD9 S_AD25 S_RST C2_REQ
10 S_AD10 S_AD26 INTA S_TRDY
11 S_AD11 S_AD27 INTB C3_IDSEL
12 S_AD12 S_AD28 INTC C3_GNT
13 S_AD13 S_AD29 INTD C3_REQ
14 S_AD14 S_AD30 NC NC
15 S_AD15 S_AD31 NC NC

Board Description
4-6
4.6 Board Description
The board layout isshown in Figure 4–1. The schematic diagram of the board
is in Figure 4–2. Table 4–4, bill of materials, is a list of the parts used to
assemble the board.
Figure 4–1.Part and Jumper Locations
P1B1
P4B1
P4A1
P3A1
P3B1
J12
U6
MC2MC1
P2B1
TP3
GND
POD1 & POD2 POD3 & POD4
J11 EVM3V
S_VIO
EVM5V
TP2
EVM3V
TP1
EVM5V
J5 J4
MSO
S_VIO
GND GND
S_VIO
EVM3V PCU3V
MS1/BPCC
U5
J8
GND
S_CFN
J10
P_VCCP
S_VCCP
J9
J1 P_MFUNC
D1
D2
D3
HSLED
D4
D5
D6
C1_PRES
C2_PRES
C3_PRES
EVM3VD7
PCU3V
J7 S_MFUNC
HS_SWITCH
POD1
15 14 13 12
11
10
9 8
S_AD15 S_AD14 S_AD13 S_AD12 S_AD11 S_AD10 S_AD09 S_AD08
7 6 5 4 3 2 1 0
S_AD07 S_AD06 S_AD05 S_AD04 S_AD03 S_AD02 S_AD01 S_AD00
POD2
15 14 13 12
11
10
9 8
S_AD31 S_AD30 S_AD29 S_AD28 S_AD27 S_AD26 S_AD25 S_AD24
7 6 5 4 3 2 1 0
S_AD23 S_AD22 S_AD21 S_AD20 S_AD19 S_AD18 S_AD17 S_AD16
POD3
15 14 13 12
11
10
9 8
NC NC INTD
INDC INTB INTA S_RST C/BE3
7 6 5 4 3 2 1 0
S_C/BE2
S_C/BE1 S_C/BE0 S_DEVSEL S_STOP S_PERR S_SERR S_PAR
POD4
15 14 13 12
11
10
9 8
NC NC C3_REQ
C3_GNT C3_IDSEL S_TRDY C2_REQ S_IRDY
7 6 5 4 3 2 1 0
S_FRAME
C2_GNT C2_IDSEL C1_REQ C1_GNT C1_IDSEL S_ACK64 S_REQ64
POD 3 CLK C1_PCLK
P_LOCK
HS_ENUM
S_LOCK
ENUM

Figure 4–2. Schematic Diagram (Sheet 1 of 8)
C3
.1uF
C13
.1uF
C8
.1uF
C2
.1uF
C7
.1uF
C6
.1uF
C12
.1uF
C5
.1uF
C11
.1uF
C1
.1uF
P1B1 PCI Connector B
–12V
1TCK 2GND 3TDO 4+5V 5
+5V
6INTB# 7INTD# 8PRSNT1# 9RESERVED
10 PRSNT2# 11
RESERVED
14 GND 15 CLK 16 GND 17 REQ# 18
AD[31]
20
GND
22
GND
34
IRDY#
35 +3.3V 36 DEVSEL# 37 GND 38 LOCK# 39 PERR# 40
SERR#
42
+3.3V
43
GND
57
+5V
61
+V I/O
19
AD[29]
21
AD[27]
23 AD[25] 24 +3.3V 25 C/BE[3]# 26 AD[23] 27
GND
28 AD[21] 29 AD[19] 30 +3.3V 31 AD[17] 32 C/BE[2]# 33
+3.3V
41
C/BE[1]#
44 AD[14] 45 GND 46 AD[12] 47 AD[10] 48 GND 49
AD[08]
52 AD[07] 53 +3.3V 54 AD[05] 55 AD[03] 56
AD[01]
58 +V I/O 59 ACK64# 60
+5V
62
C4
.1uF
C14
.1uF
C10
.1uF
P1A1 PCI Connector A
TRST#
1+12V 2TMS 3TDI 4+5V 5
INTA#
6INTC# 7+5V 8RESERVED 9
RESERVED
11
RST#
15
GNT#
17 GND 18 RESERVED 19 AD[30] 20
AD[28]
22 AD[26] 23
AD[24]
25 IDSEL 26
AD[22]
28 AD[20] 29 GND 30 AD[18] 31 AD[16] 32 +3.3V 33 FRAME# 34
GND
35 TRDY# 36 GND 37 STOP# 38 +3.3V 39 SDONE 40 SBO# 41 GND 42
+3.3V
45
+3.3V
53
GND
56
+5V
61
+V I/O
10
RESERVED
14
+V I/O
16
+3.3V
21
GND
24
+3.3V
27
PAR
43 AD[15] 44
AD[13]
46 AD[11] 47 GND 48 AD[09] 49
C/BE[0]#
52
AD[06]
54 AD[04] 55
AD[02]
57 AD[00] 58 +V I/O 59 REQ64# 60
+5V
62
C9
.1uF
S_DEVSEL# S_TRDY# S_STOP# S_PAR S_PERR# S_SERR#
S_IRDY# S_RST# C1_PRES S_FRAME#
S_RST#
S_LOCK# C1_PCLK C1_GNT#
C1_REQ# S_AD31 S_AD30 S_AD29 S_AD28
C1_REQ# S_AD27 S_AD26 C1_GNT# S_AD25 S_AD24
S_C/BE#3 C1_IDSEL
C1_PCLK S_AD23 S_AD22 C1_IDSEL S_AD21 S_AD20 C1_PRES S_AD19 S_AD18
S_AD17 S_AD16 S_C/BE#2 S_FRAME# S_IRDY# S_TRDY# S_DEVSEL# S_STOP#
S_LOCK#
S_PERR# S_SERR# S_PAR S_C/BE#1 S_AD15 S_AD14 S_AD13 S_AD12 S_AD11 S_AD10 S_AD9
S_ACK64#
S_AD8 S_C/BE#0 S_AD7 S_REQ64#
S_AD6
S_AD5 S_AD4 S_AD3 S_AD2 S_AD1 S_AD0 S_ACK64# S_REQ64#
S_C/BE#[0..3]
S_VIO
EVM3V EVM–12V EVM12V
EVM3V EVM12V
S_VIO EVM5V
EVM5V
S_C/BE#[0..3] S_IRDY# S_RST#
S_FRAME#
S_LOCK#
EVM3V S_VIO EVM12V EVM5V EVM–12V
S_AD[0..31]
S_DEVSEL#
S_TRDY#
S_STOP#
S_PAR
S_PERR# S_SERR#
C1_REQ# C1_GNT# C1_PCLK C1_IDSEL C1_PRES
INTA# INTB# INTC# INTD#
S_ACK64# S_REQ64#
INTA INTB INTC INTD
Mictor Connector Definition
4-7
Board Configuration

Fi
g
ure 4–2. Schematic Dia
g
ram (Sheet 2 of 8)
C23
.1uF
C17
.1uF
P1B2 PCI Connector B
–12V
1TCK 2GND 3TDO 4+5V 5+5V 6INTB# 7INTD# 8PRSNT1# 9RESERVED
10 PRSNT2# 11
RESERVED
14 GND 15 CLK 16 GND 17 REQ# 18
AD[31]
20
GND
22
GND
34 IRDY# 35 +3.3V 36 DEVSEL# 37 GND 38 LOCK# 39 PERR# 40
SERR#
42 +3.3V 43
GND
57
+5V
61
+V I/O
19
AD[29]
21
AD[27]
23 AD[25] 24 +3.3V 25 C/BE[3]# 26 AD[23] 27 GND 28 AD[21] 29 AD[19] 30 +3.3V 31 AD[17] 32 C/BE[2]# 33
+3.3V
41
C/BE[1]#
44 AD[14] 45 GND 46 AD[12] 47 AD[10] 48 GND 49
AD[08]
52 AD[07] 53 +3.3V 54 AD[05] 55 AD[03] 56
AD[01]
58 +V I/O 59 ACK64# 60
+5V
62
C27
.1uF
C22
.1uF
P1A2 PCI Connector A
TRST#
1+12V 2TMS 3TDI 4+5V 5INTA# 6INTC# 7+5V 8RESERVED 9
RESERVED
11
RST#
15
GNT#
17 GND 18 RESERVED 19 AD[30] 20
AD[28]
22 AD[26] 23
AD[24]
25 IDSEL 26
AD[22]
28 AD[20] 29 GND 30 AD[18] 31 AD[16] 32 +3.3V 33 FRAME# 34 GND 35 TRDY# 36 GND 37 STOP# 38 +3.3V 39 SDONE 40 SBO# 41 GND
42
+3.3V
45
+3.3V
53
GND
56
+5V
61
+V I/O
10
RESERVED
14
+V I/O
16
+3.3V
21
GND
24
+3.3V
27
PAR
43 AD[15] 44
AD[13]
46 AD[11] 47 GND 48 AD[09] 49
C/BE[0]#
52
AD[06]
54 AD[04] 55
AD[02]
57 AD[00] 58 +V I/O 59 REQ64# 60
+5V
62
C16
.1uF
C21
.1uF
C20
.1uF
C15
.1uF
C26
.1uF
C19
.1uF
C25
.1uF
C18
.1uF
C28
.1uF
C24
.1uF
EVM5V EVM3V S_VIO EVM12V
C2_PRES
S_RST#
C2_PCLK C2_GNT# C2_REQ# S_AD31 S_AD30 S_AD29 S_AD28 S_AD27 S_AD26 S_AD25 S_AD24 S_C/BE#3 C2_IDSEL S_AD23 S_AD22 S_AD21 S_AD20 S_AD19 S_AD18 S_AD17 S_AD16 S_C/BE#2 S_FRAME# S_IRDY# S_TRDY# S_DEVSEL# S_STOP#
S_LOCK#
S_PERR# S_SERR# S_PAR S_C/BE#1 S_AD15 S_AD14 S_AD13 S_AD12 S_AD11 S_AD10 S_AD9 S_AD8 S_C/BE#0 S_AD7 S_AD6 S_AD5 S_AD4 S_AD3 S_AD2 S_AD1 S_AD0 S_ACK64# S_REQ64#
S_ACK64#
S_REQ64#
S_C/BE#[0..3] S_IRDY# S_RST# S_FRAME# S_LOCK#
INTA# INTD#
INTC#
INTB#
C2_PRES C2_IDSEL C2_PCLK C2_GNT# C2_REQ#
S_SERR# S_PERR#
S_PAR
S_STOP# S_TRDY#
S_DEVSEL# EVM–12V EVM5V EVM12V S_VIO EVM3V
S_AD[0..31]
INTA INTB INTC INTD
Mictor Connector Definition
4-8
Board Configuration