Texas Instruments ADS1258EVM-PDK User manual

User's Guide
ADS1258EVM-PDK Evaluation Module
ABSTRACT
This user’s guide describes the characteristics, operation, and use of the ADS1258 evaluation module (EVM).
This EVM is an evaluation platform for the ADS1258, a 24-bit, 125-kSPS, 16-channel (multiplexed), delta-sigma
(ΔΣ) analog-to-digital converter (ADC). The ADS1258 offers excellent noise performance, fast sampling speeds,
a programmable channel sequencer, and access to the multiplexer output for efficient signal conditioning. The
ADS1258EVM eases the evaluation of the device with hardware, software, and computer connectivity through
the universal serial bus (USB) interface. This user's guide includes complete circuit descriptions, schematic
diagrams, and a bill of materials. Throughout this document, the abbreviation EVM and the term evaluation
module are synonymous with the ADS1258EVM.
Note
The ADS1258EVM and software can also support the 16-bit ADS1158 device. However, the user
must manually remove the ADS1258 and install the ADS1158. See Section 8.3 for the location of the
ADS1258 on the EVM. The ADS1158 is not discussed further in this document.
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Table of Contents
1 ADS1258EVM Overview......................................................................................................................................................... 3
1.1 ADS1258EVM Kit...............................................................................................................................................................3
1.2 ADS1258EVM.................................................................................................................................................................... 3
2 Getting Started With the ADS1258EVM................................................................................................................................ 4
3 Analog Interface......................................................................................................................................................................5
3.1 Analog Input Options..........................................................................................................................................................5
3.2 ADC Connections and Decoupling.....................................................................................................................................6
3.3 Configurable Multiplexer Loop........................................................................................................................................... 7
3.4 Clocking............................................................................................................................................................................. 8
3.5 Voltage Reference..............................................................................................................................................................9
4 Digital Interface.....................................................................................................................................................................10
4.1 GPIO................................................................................................................................................................................ 10
5 Power Supplies..................................................................................................................................................................... 11
6 Software Installation.............................................................................................................................................................12
7 EVM Operation and GUI....................................................................................................................................................... 14
7.1 Connecting the Hardware................................................................................................................................................ 14
7.2 EVM GUI Global Settings for ADC Control...................................................................................................................... 15
7.3 Time-Domain Display....................................................................................................................................................... 16
7.4 Frequency-Domain Display..............................................................................................................................................17
7.5 Histogram Display............................................................................................................................................................ 18
8 Bill of Materials, Layout, and Schematics.......................................................................................................................... 19
8.1 Bill of Materials.................................................................................................................................................................19
8.2 EVM PCB Layout............................................................................................................................................................. 22
8.3 Schematics.......................................................................................................................................................................23
9 Revision History................................................................................................................................................................... 26
Trademarks
LabVIEW™ is a trademark of National Instruments.
Microsoft® and Windows® are registered trademarks of Microsoft Corporation.
All trademarks are the property of their respective owners.
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1 ADS1258EVM Overview
The ADS1258EVM is a platform for evaluating the performance of the ADS1258, a 24-bit, 125-kSPS, 16-channel
(multiplexed), ΔΣ ADC. The evaluation kit includes the ADS1258EVM and the precision host interface (PHI)
controller board that enables the accompanying computer software to communicate with the ADC over USB
for data capture and analysis. The ADS1258EVM includes the ADS1258 ADC as well as the high-performance
peripheral analog circuits necessary to extract the best performance from the ADC. The PHI board primarily
serves three functions:
• Provides a communication interface from the EVM to the computer through a USB port
• Provides the digital input and output signals necessary to communicate with the ADS1258
• Supplies power to all active circuitry on the ADS1258EVM board
1.1 ADS1258EVM Kit
The ADS1258 evaluation kit includes the following features:
• Hardware and software required for diagnostic testing as well as accurate performance evaluation of the
ADS1258 ADC.
• USB powered: No external power supply is required.
• PHI controller that provides a convenient communication interface to the ADS1258 ADC over USB 2.0 (or
higher) for power delivery as well as digital input and output.
• Microsoft® Windows® 8, and Windows 10 operating systems.
• Easy-to-use evaluation software for 64-bit Windows operating systems.
• The software suite includes graphical tools for data capture, histogram analysis, and spectral analysis. This
suite also has a provision for exporting data to a text file for post-processing.
Figure 1-1 shows system connections for the EVM.
Figure 1-1. System Connection for Evaluation
1.2 ADS1258EVM
The ADS1258EVM includes the following features and configuration options:
• An OPA2320 precision amplifier buffer between the multiplexer output and ADC input, or bypass external
circuitry
• Low-noise, low-drift, 2.5-V REF6025 as the default reference source, or use an external reference source
• A 16-MHz clock signal provided by the PHI controller, or use an external clock source
• Eight general-purpose input-output (GPIO) pins brought out to a dedicated header
• Ultra-low noise TPS7A4700 low-dropout (LDO) linear regulator supplies 5-V ADC analog voltage (AVDD), or
use an external voltage supply
• 3.3-V ADC digital voltage (DVDD) supplied by PHI controller, or use external voltage supply
• Test points for power, GND, reference, and all digital signals to and from the PHI controller
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2 Getting Started With the ADS1258EVM
The following list of instructions provides an overview to quickly get the ADS1258EVM set up and operational.
The subsequent sections in this document expand on each step to explain in detail the available features on the
EVM and the corresponding GUI. Links are provided to navigate from this quick-start guide to the appropriate
section at each applicable step.
1. Remove the ADS1258EVM, PHI board, and USB cable from the ADS1258EVM-PDK box.
2. If necessary, connect the PHI board to the ADS1258EVM (see Figure 7-1).
3. Configure the ADS1258EVM:
a. Power supplies (see Section 5).
b. Clocking (see Section 3.4, if applicable).
c. Voltage reference (see Section 3.5, if applicable)
4. Connect the micro-USB-to-USB cable from the PHI directly to a USB port on the computer. Do not connect
the cable to the computer through a USB hub.
5. Open the latest version of the ADS1258EVM GUI on the connected computer.
a. First-time users must download the latest version of the EVM GUI installer from the Tools and Software
folder of the ADS1258EVM and run the GUI installer to install the EVM GUI software on the host
computer.
6. Connect the analog input (see Section 3.1) to the input terminal blocks (J1-J2).
7. Capture and analyze data (see Section 7.2) using the GUI.
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3 Analog Interface
The ADS1258EVM is designed for convenient interfacing with analog input signals. This section covers
the details of the front-end circuit, including jumper configurations for different input test signals and board
connectors for signal sources.
3.1 Analog Input Options
The ADS1258EVM allows for up to 16 single-ended inputs or eight differential inputs, as well as combinations of
single-ended and differential inputs. As shown in Figure 3-1, connect analog input signals to terminal blocks J1
and J2 on the EVM.
AIN0
AIN1
AIN2
A0
A1
A2
A3
Differential-Mode Input Anti-Aliasing Filter
Attenuation at Modulator Data Rate (8 MHz): 33.49 dB
AIN3
GND
GND
AIN4
AIN5
AIN6
A4
A5
A6
A7
AIN7
GND
GND
AIN8
AIN9
AIN10
A8
A9
A10
A11
AIN11
GND
GND
AIN12
AIN13
AIN14
A12
A13
A14
A15
AIN15
GND
GND
1.00k
R22
1.00k
R26
1.00k
R28
1.00k
R33
1.00k
R37
1.00k
R39
1.00k
R46
1.00k
R59
1.00k
R23
1.00k
R27
1.00k
R29
1.00k
R34
1.00k
R38
1.00k
R40
1.00k
R47
1.00k
R60
3-dB Cutoff: 168.51 kHz
Common-Mode Input Anti-Aliasing Filter
3-dB Cutoff: 3.37 MHz
47pF
C25
47pF
C29
47pF
C31
47pF
C35
47pF
C26
47pF
C30
47pF
C32
47pF
C36
47pF
C12
47pF
C16
47pF
C19
47pF
C24
47pF
C18
47pF
C23
47pF
C11
47pF
C15
470pF
C21
470pF
C13
470pF
C22
470pF
C14
470pF
C34
470pF
C28
470pF
C33
470pF
C27
5
4
1
2
3
6
7
8
J2
AIN12
AIN13
AIN14
AIN15
AIN8
AIN9
AIN10
AIN11
5
4
1
2
3
6
7
8
J1
AIN4
AIN5
AIN6
AIN7
AIN0
AIN1
AIN2
AIN3
Figure 3-1. ADS1258EVM Analog Input Channels and Filtering
Each analog input signal passes through a set of low-pass filters to prevent aliasing. The differential filters
have a 3-dB cutoff of 168.5 kHz, resulting in 33.49 dB of attenuation at the 8-MHz modulator frequency. As an
example, Figure 3-1 shows that capacitor C13 and resistors R22 and R26 create the differential filter between
analog inputs AIN0 and AIN1. The common-mode filters have a 3-dB cutoff of 3.37 MHz. As an example, Figure
3-1 shows that capacitor C11 and resistor R22 create the common-mode filter for analog input AIN0. Precision
5% C0G or NPO-type capacitors and 0.1% resistors are used in the analog signal chain to reduce measurement
error.
Use adjacent input pins when measuring differential input signals to benefit from differential filtering and to
achieve best performance. For example, AIN0 and AIN1 are set up for differential signaling because C13
connects these two inputs. Conversely, do not use AIN1 and AIN2 as a differential pair because there is no
capacitor connecting these two inputs.
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3.2 ADC Connections and Decoupling
Figure 3-2 shows all ADC connections. Each power-supply and reference connection have a 100-nF decoupling
capacitor. Place these capacitors as close as possible to the ADC pins and make sure each component has a
low-impedance connection to the GND plane.
Each digital pin of the ADC has a 49.9-Ω series resistor. These resistors smooth the edges of the digital signals
so that the signals have minimal overshoot and ringing. A resistor is most important on the serial clock (SCLK)
trace because the SCLK signal can toggle as quickly as 8 MHz. Resistors on the other pins are not strictly
required, though these components can be included in the final design to improve digital signal integrity.
Pullup resistors R8, R9, R10, and R11 prevent CS, START, RESET, and PWDN, respectively, from floating when
not driven. The differential voltage across test points TP4 and ground is the reference voltage used by the ADC.
DVDD
ADC.SCLK
ADC.DIN
ADC.DOUT
ADC.CS
ADC.DRDY
ADC.START
ADC.RESET
AVDD
6
DVDD
28
AIN0
4
AIN1
3
AIN2
2
AIN3
1
AIN4
48
AIN5
47
AIN6
46
AIN7
45
AIN8
40
AIN9
39
AIN10
38
AIN11
37
AIN12
36
AIN13
35
AIN14
34
AIN15
33
XTAL1 8
XTAL2 9
GPIO0 14
GPIO1 15
GPIO2 16
GPIO3 17
GPIO4 18
GPIO5 19
GPIO6 20
GPIO7 21
CS 27
DRDY 25
PWDN 10
RESET 11
ADCINN
41 ADCINP
42
AINCOM
32 CLKIO 13
CLKSEL 12
DIN 23
DOUT 24
EP 49
MUXOUTN 43
MUXOUTP 44
PLLCAP 7
SCLK 22
START 26
VREFN
30 VREFP
31
AVSS 5
DGND 29
ADS1258IRTCR
U3
ADCINP
ADCINN
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
ACOM
GND
GND
DVDD
MUXOUTP
MUXOUTN
ADS1258
REFOUT
CLK
GND
ADC.PWDN
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
AVDD
TP4
REFOUT
Place
capacitors
near ADC
supply pins
DVDD
49.9
R12
49.9
R13
49.9
R14
49.9
R15
49.9
R16
49.9
R18
49.9
R19
49.9
R20
100k
R8
100k
R9
100k
R10
100k
R11
100nF
C7
100nF
C6
100nF
C8
GND
Figure 3-2. ADS1258EVM ADC Power-Supply Decoupling and Analog and Digital Connections
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3.3 Configurable Multiplexer Loop
The ADS1258 multiplexer has optional differential output connections (MUXOUTx) that enable a single signal-
conditioning circuit to be used for all analog inputs. The default signal conditioning circuit is a differential
unity-gain buffer (OPA2320) between each MUXOUTx and ADCINx pin. A low-pass filter is connected to the
output of the buffer. As shown in Figure 3-3, capacitor C20 is used to bypass the ADC sampling currents and
resistors R25 and R35 are used to isolate the op-amp outputs from the filter capacitor.
GND
ADCINP
MUXOUTP
2200pF
C20
1
3
2
OPA2320AQDGKRQ1
U4A
0
R24
47.5
R25
0
R31
0
R30
DNP
OPA2320 is a dual op-amp
package used here in a single-
supply configuration
Only one decoupling cap is
needed at positive supply (pin
8) for both op-amps
100nF
A
ADCINP
MUXOUTP
7
5
6
OPA2320AQDGKRQ1
U4B
47.5
R35
B
GND
AVDD
C17
V+ V-
OPA2320AQDGKRQ1
U4C
84
Figure 3-3. ADS1258EVM Configurable Multiplexer Loop With a Signal-Conditioning Circuit
The signal-conditioning circuit shown in Figure 3-3 can also be configured into a differential-input, differential-
output gain stage by changing resistors R24, R30, and R31 as per Equation 1.
G = 1 + 2 × (R24) / R30 (1)
Importantly, Equation 1 assumes that R31 = R24.
As an example, replacing R24 and R31 with 10-kΩ resistors and R30 with a 2.2-kΩ resistor creates a gain of
10 V/V between the MUXOUTx and ADCINx pins. Choose R24, R30, and R31 to be size 0603 resistors with a
tolerance ≤0.1% to maintain system accuracy.
Enable the multiplexer loop by setting BYPAS = 1 in the CONFIG0 register. To bypass the multiplexer loop,
set BYPAS = 0. One important caveat to the multiplexer bypass option is that the signal-conditioning circuit is
only disconnected from the ADCINx pins. In other words, the signal-conditioning circuit is still connected to the
MUXOUTx pins regardless of the state of the BYPAS bit.
3.3.1 Measuring Single-Ended Inputs Using a Pseudo-Differential Configuration
Both the buffer or gain stage configuration can be used to directly measure true differential input signals.
Measuring single-ended inputs requires additional consideration because the OPA2320 is powered by a
unipolar, 5-V supply. Additionally, the OPA2320 requires up to 45 mV of headroom between the output voltage
and either supply (V+ or V–). These two limitations restrict the ability of the default amplifier circuit shown
in Figure 3-3 to measure single-ended signals referenced to ground. Instead, the amplifier negative input
(MUXOUTN) must be level-shifted to a mid-supply voltage. This type of measurement is referred to as pseudo-
differential, or a measurement with respect to some fixed voltage above ground.
Implement a pseudo-differential measurement on the ADS1258EVM by shorting the 2.5-V REFOUT voltage to
the appropriate channel. In Auto-Scan mode, use jumper JP2 to short REFOUT to AINCOM because AINCOM
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is used as the negative channel for all single-ended measurements. In Fixed-Channel mode, short REFOUT to
whichever analog input is selected as AINN in the MUXSCH register. This short can be applied externally using
terminal block J3. Figure 3-4 shows both JP2 and J3.
EXT_VREFP
1
2 3
J3
GND
AINCOM ACOM
REFOUT AINCOM
0
R2
DNP
1.00k
R1
470pF
C1
JP2
Short AINCOM
to REFOUT
Figure 3-4. Shorting AINCOM to REFOUT
A pseudo-differential measurement only sets the voltage on the MUXOUTN pin to be within the amplifier output
voltage limits. The user must also make sure that the voltage applied to the ADCINP pin is within this same
range. To measure signals that are outside of the amplifier output voltage limitations, consider bypassing the
external multiplexer loop as described in Section 3.3.
3.4 Clocking
The ADS1258 requires a high-frequency system clock to oversample the inputs and provide digital data at the
output data rate. By default, a 16-MHz system clock is provided by the PHI controller board. The PHI also
generates the SCLK signal from the same clock domain, which improves overall ADC performance.
An external clock can also be used with the ADS1258EVM, though this setup requires altering the EVM
components. First, install SMA connector J8, then remove termination resistor R17 and install this component
at R7. Figure 3-5 shows the external clocking circuit. See the ADS1258 data sheet for information about the
allowable clock frequency range.
GND
1
2 3 4 5
J8
DNP
EXT Clock
CLK
49.9
R17
0
R7
DNP
ADC.MCLK_OUT
Figure 3-5. ADS1258EVM Clock Circuit
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3.5 Voltage Reference
The ADS1258EVM requires a precision reference voltage to accurately convert the analog inputs to digital
outputs. Figure 3-6 shows the EVM voltage reference circuitry.
REFOUT
EXT_VREFP
VIN
1
SS
3
FILT
4
EN
2
OUT_S 5
OUT_F 6
GND_F 7
GND_S 8
REF6025IDGKR
U1
AVDD
120k
R5
1µF
C5 0.047
R6
22µF
C3
GND
TP1
GND
1
2 3
J3
GND
AINCOM ACOM
REFOUT AINCOM
0
R2
DNP
0
R4
1.00k
R1
10uF
C4
470pF
C1
JP2
Short AINCOM
to REFOUT
Figure 3-6. ADS1258EVM Voltage Reference Circuit
The EVM includes two options to provide a reference voltage to the ADC. The first option is an installed
component: the low-noise, low-drift, buffered-output REF6025. This discrete voltage reference outputs a voltage
of 2.5 V to the ADC reference pins (REFOUT and ground). Additionally, the REF6025 output voltage is also
connected to the J3 terminal block as REFOUT.
The second voltage reference option on the EVM is to use an external voltage source. An external component
can be useful if a reference voltage other than 2.5 V is required. Configure the EVM for an external voltage
reference by moving the 0-Ω resistor at R4 to R2. Then connect EXT_VREFP on J3 to the external reference
output voltage, and connect the external reference ground to the EVM ground. REFOUT on J3 is shorted
to EXT_VREFP to make sure that the reference voltage can still be used to bias external circuitry. See the
ADS1258 data sheet for information about the allowable voltage range on the VREFx pins.
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4 Digital Interface
As noted in Section 1, the EVM interfaces with the PHI and communicates with the host over USB. Figure 4-1
shows how the PHI communicates with two devices on the EVM: the ADS1258 using the serial peripheral
interface (SPI) and the EEPROM using the inter-integrated circuit (I2C) interface. The EEPROM comes
preprogrammed with the information required to configure and initialize the ADS1258EVM. When the hardware
is initialized, no further communication with the EEPROM is necessary and this device can be ignored by the
user.
ADC
1 1
3 3
5 5
7 7
9 9
11 11
13 13
15 15
17 17
19 19
21 21
23 23
25 25
27 27
29 29
31 31
33 33
35 35
37 37
39 39
41 41
43 43
45 45
47 47
49 49
51 51
53 53
55 55
57 57
59 59
2
2
4
4
6
6
8
8
10
10
12
12
14
14
16
16
18
18
20
20
22
22
24
24
26
26
28
28
30
30
32
32
34
34
36
36
38
38
40
40
42
42
44
44
46
46
48
48
50
50
52
52
54
54
56
56
58
58
60
60
GND
MP1
GND
MP2 GND MP3
GND MP4
J5
GND GND
EVM_ID_SDA
EVM_ID_SCL
EVM_ID_PWR
GND
10uF
C10
GND
GND
EVM_REG_5V5
RESET
START
DIN
CS
SCLK
DRDY
DOUT
PWDN
ADC
PWDN
RESET
START
DIN
CS
DRDY
SCLK
DOUT
A0
1
A1
2
A2
3
VSS
4 SDA 5
SCL 6
WP 7
VCC 8
U2
BR24G32FVT-3AGE2
EVM_ID_PWR
EVM_ID_PWR
GND
EVM_ID_SCL
EVM_ID_SDA GND
EVM ID EEPROM
10k
R3
WP
PHI Connector &
SPI Interface
WP
CAP_CLK
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
J6
49.9R62
0
R21
100nF
C2
MCLK_OUT
10uF
C9
GND
EVM_DVDD
17 18
MCLK_OUT
Digital Signal Header
Figure 4-1. ADS1258EVM Digital Interface Connections (SPI and I2C)
The ADS1258 communicates with the PHI using an SPI interface in mode 00 (CPOL = 0, CPHA = 0). Header
J6 in Figure 4-1 provides test points for all digital signals to and from the PHI controller. The test points can be
connected to a logic analyzer for convenient visualization of the digital signals. These test points can also be
used to communicate with the ADS1258EVM using an external controller.
4.1 GPIO
The ADS1258 has eight dedicated GPIO pins. The EVM connects a 100-kΩ pulldown resistor to each GPIO pin.
These resistors prevent the pin voltage from floating because the default ADC settings configure each GPIO as
an input. Additionally, 49.9-Ω resistors are placed in series with each GPIO pin to limit current flow into the ADC.
All eight GPIO pins are terminated at header J7 for easy connection to external circuitry if desired. Figure 4-2
shows the GPIO circuitry.
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
5
4
1
2
3
6
7
8
9
10
J7
49.9R41
49.9
R42
49.9
R43
49.9
R44
49.9
R45
49.9
R48
49.9
R49
49.9R50
100k
R51
100k
R52
100k
R53
100k
R54
100k
R55
100k
R56
100k
R57
100k
R58
GND
GND
DVDD
Figure 4-2. ADS1258EVM GPIO Circuit and Header
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5 Power Supplies
The default ADC power-supply voltages (DVDD and AVDD) are generated by the PHI controller using power
from the USB. The PHI provides 3.3-V and 5.5-V power rails. The 3.3-V power rail directly supplies the ADC
DVDD voltage. The 5.5-V power rail is supplied to the input of the TPS7A4700, a low-noise, configurable-output
LDO, to supply AVDD. The LDO output voltage depends on the internal reference voltage (VLDO_REF) of 1.4
V and the pin connections. Grounding any LDO pin between pins 4 through pin 12 adds that pin voltage to
VLDO_REF and increases the LDO output voltage, LDOVOUT. Figure 5-1 shows that the ADS1258EVM grounds
pins 6 and 10 (3P2V and 0P4V, respectively) to set LDOVOUT equal to 5 V.
5-V Analog LDO
EVM_REG_5V5
10uF
C37
0.1
R61
22µF
C39
5V_LDO
GND
GND
JP1
LDO_PWR
OUT 1
OUT 20
IN
15
IN
16
0P1V
12
0P2V
11
0P4V
10
0P8V
9
1P6V
8
3P2V
6
6P4V1
5
6P4V2
4
EN
13
NR
14
SENSE/FB 3
Thermal_Pad 21
NC 2
NC 17
NC 18
NC 19
GND 7
TPS7A4700RGWR
U5
1µF
C38
EVM/PHI Power
JP3
JP4
5V_LDO AVDD
EVM_DVDD DVDD
3.3V
5V
GND
J4
AVDD_OUT
GND
AVDD_PWR
DVDD_PWR
TP7
5.5V
Figure 5-1. ADS1258EVM LDO Circuit and External Power Source Connections
Figure 5-1 shows that the 5V_LDO output is used for the AVDD connections across the EVM. Additionally, the
user can measure the AVDD current by connecting an ammeter between pins 1 and 2 of JP3 or the DVDD
current by connecting an ammeter between pins 1 and 2 of JP4.
External power sources can also be provided for each supply voltage:
• LDO: Remove the shunt on JP1 and connect external power to JP1:2
• AVDD: Remove the shunt on JP3 and connect external power to JP3:1
• DVDD: Remove the shunt on JP4 and connect external power to JP4:1
When using either internal or external power supplies, LEDs D1 and D2 indicate if power is connected to AVDD
and DVDD, respectively. These LEDs do not necessarily indicate if AVDD is 5 V or if DVDD s 3.3 V. Check the
AVDD voltage using test point TP3 and check the DVDD voltage using test point TP5. Figure 5-2 shows the
portion of the ADS1258EVM schematic that includes the LEDs and test points.
Green
D2
AVDD DVDD
Green
D1
GND GND
6.65k
R63
6.65k
R64
TP3
AVDD
TP5
DVDD
Figure 5-2. ADS1258EVM AVDD and DVDD Indicator LEDs
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6 Software Installation
Download the latest version of the EVM GUI installer from the Tools and Software folder of the ADS1258EVM
and run the GUI installer to install the EVM GUI software on the computer.
CAUTION
Manually disable any antivirus software running on the computer before downloading the EVM GUI
installer onto the local hard disk. Depending on the antivirus settings, an error message may appear
or the installer.exe file may be deleted.
As shown in Figure 6-1, accept the license agreements and follow the on-screen instructions to complete the
installation.
Figure 6-1. Software Installation and Prompts
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As a part of the ADS1258EVM GUI installation, a prompt with a Device Driver Installation, as shown in Figure
6-2, appears on the screen. Click Next to proceed.
Figure 6-2. Device Driver Installation and Prompts
The ADS1258EVM requires the LabVIEW™ run-time engine and can prompt for the installation of this software,
as shown in Figure 6-3, if not already installed.
Figure 6-3. LabVIEW Run-Time Engine Installation
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7 EVM Operation and GUI
7.1 Connecting the Hardware
Connect the EVM as shown in Figure 7-1 after installing the software:
1. Physically connect P2 of the PHI to J5 of the ADS1258EVM. Install the screws to make a robust connection.
2. Connect the USB cable from the computer to the PHI:
a. LED D5 on the PHI lights up, indicating that the PHI is powered up.
b. LEDs D1 and D2 on the PHI start blinking to indicate that the PHI is booted up and communicating with
the PC. Figure 7-1 shows the resulting LED indicators.
3. Start the software GUI as shown in Figure 7-2. The LEDs blink slowly as the FPGA firmware is loaded on the
PHI. This loading takes a few seconds and then the AVDD and DVDD power supplies turn on, as indicated
by LEDs D1 and D2 on the ADS1258EVM.
4. Connect the input signal using terminal blocks J1 and J2. The input range is 0 V to 5 V with the multiplexer
loop bypassed. See Section 3.3 for the input range limitations when the multiplexer loop is enabled.
Figure 7-1. ADS1258EVM Hardware Connections
Figure 7-2. Launch the EVM GUI Software
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7.2 EVM GUI Global Settings for ADC Control
Figure 7-3 shows that the EVM global controls are located on the left side of the GUI. These controls include the
sampling mode, data rate, MUXOUT connection, switch time delay, channel selection, number of samples, and
others. The Pages control in the upper-left corner allows access to the other pages in the GUI. Figure 7-3 also
shows the available ADC register settings. The registers can be used to configure the ADC data rate, channel
sequencer, or integrated features. Change the register settings by clicking on each bit, typing a value directly into
the Value column, or by selecting from the drop-down menus in the Field View control.
Figure 7-3. ADS1258EVM GUI Global Settings for ADC Control Page
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7.3 Time-Domain Display
The time-domain display tool allows visualization of the ADC response to a given input signal. This tool is useful
for studying the behavior of and debugging any gross problems with the ADC or drive circuits. Trigger a data
capture of the selected number of samples from the ADS1258EVM by using the Capture button in Figure 7-4.
The captured data are subject to the current interface mode settings. The time-domain plot has Samples on the
x-axis and by default shows the corresponding Codes on the y-axis relative to the specified reference voltage.
The y-axis units can also be changed to Voltage/Temp/Gain using the Unit control in the bottom right. The Temp
and Gain units are only used with the Temp and Gain channel selections, respectively.
The Measurements control on the bottom of Figure 7-4 calculates the code range, the mean code, and the code
standard deviation. Switching pages to any of the Analysis tools described in the subsequent sections causes
calculations to be performed on the same set of data.
Figure 7-4. ADS1258EVM GUI Time Domain Display Page
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7.4 Frequency-Domain Display
Figure 7-5 shows the spectral analysis tool that evaluates the dynamic performance (SNR, THD, SFDR, SINAD,
and ENOB) of the ADS1258. This dynamic performance is calculated by single-tone sinusoidal signal FFT
analysis using the 7-term Blackman-Harris window setting. The FFT tool includes windowing options that are
required to mitigate the effects of non-coherent sampling (this discussion is beyond the scope of this document).
The 7-term Blackman-Harris window is the default option and has sufficient dynamic range to resolve the
frequency components of a 24-bit ADC. The None option corresponds to not using a window (or using a
rectangular window) and is not recommended.
Figure 7-5. ADS1258EVM GUI Frequency Domain Display Page
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7.5 Histogram Display
Noise degrades ADC resolution and the histogram tool shown in Figure 7-6 can be used to estimate effective
resolution. Effective resolution is a metric describing the ADC resolution loss resulting from noise generated by
the various sources connected to the ADC when measuring a dc signal. The cumulative effect of noise coupling
to the ADC output from sources such as the input drive circuits, the reference drive circuit, the ADC power
supply, and the ADC is reflected in the standard deviation of the ADC output code histogram that is obtained by
performing multiple conversions of a dc input applied to a given channel.
Figure 7-6. ADS1258EVM GUI Histogram Display Page
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8 Bill of Materials, Layout, and Schematics
8.1 Bill of Materials
Table 8-1 lists the bill of materials (BOM) for the ADS1258EVM.
Table 8-1. Bill of Materials
Designator Quantity Value Description Package Reference Part Number Manufacturer
C1, C13, C14, C21,
C22, C27, C28, C33,
C34
9 470 pF
CAP, CERM, 470 pF,
50 V, +/- 5%, C0G/
NP0, 0603
0603 06035A471JAT2A AVX
C2, C6, C7, C8, C17 5 0.1 uF
CAP, CERM, 0.1 uF,
25 V, +/- 5%, X7R,
0603
0603 C0603C104J3RACTU Kemet
C3, C39 2 22 uF
CAP, CERM, 22 µF,
25 V,+/- 10%, X7R,
1210
1210 CL32B226KAJNFNE Samsung Electro-
Mechanics
C4, C9, C10, C37 4 10 uF
CAP, CERM, 10 uF,
25 V, +/- 10%, X7R,
1206_190
1206_190 C1206C106K3RACT
UKemet
C5, C38 2 1 uF
CAP, CERM, 1 µF, 16
V,+/- 10%, X7R, AEC-
Q200 Grade 1, 0603
0603 CGA3E1X7R1C105K
080AC TDK
C11, C12, C15, C16,
C18, C19, C23, C24,
C25, C26, C29, C30,
C31, C32, C35, C36
16 47 pF
CAP, CERM, 47 pF,
50 V, +/- 5%, C0G/
NP0, 0603
0603 C0603C470J5GACT
UKemet
C20 1 2200 pF
CAP, CERM, 2200 pF,
50 V, +/- 5%, C0G/
NP0, 0603
0603 GRM1885C1H222JA
01D MuRata
D1, D2 2 Green LED, Green, SMD LED_0805 APT2012LZGCK Kingbright
H1, H2 2 Machine Screw Pan
PHILLIPS M3 RM3X4MM 2701 APM HEXSEAL
H3, H4 2 ROUND STANDOFF
M3 STEEL 5MM
ROUND STANDOFF
M3 STEEL 5MM 9774050360R Wurth Elektronik
H5, H6, H7, H8 4 Bumpon, Cylindrical,
0.312 X 0.200, Black Black Bumpon SJ61A1 3M
J1, J2 2 Terminal Block,
3.5mm, 8-Pos, TH
Terminal Block,
3.5mm, 8-Pos, TH ED555/8DS On-Shore Technology
J3 1 Terminal Block,
3.5mm, 3x1, Tin, TH
Terminal Block,
3.5mm, 3x1, Tin, TH 691214110003 Wurth Elektronik
J4 1 Terminal Block, 2x1,
3.5mm, TH 2x1 Terminal Block OSTTE020161 On-Shore Technology
J5 1
Header(Shrouded),
19.7mil, 30x2, Gold,
SMT
Header (Shrouded),
19.7mil, 30x2, SMT QTH-030-01-L-D-A Samtec
J6 1 Header, 100mil, 9x2,
Gold, TH 9x2 Header TSW-109-07-G-D Samtec
J7 1 Header, 100mil, 10x1,
Gold, TH 10x1 Header TSW-110-07-G-S Samtec
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Table 8-1. Bill of Materials (continued)
Designator Quantity Value Description Package Reference Part Number Manufacturer
JP1, JP2, JP3, JP4 4 Header, 100mil, 2x1,
Gold, TH 2x1 Header TSW-102-07-G-S Samtec
R1, R22, R23, R26,
R27, R28, R29, R33,
R34, R37, R38, R39,
R40, R46, R47, R59,
R60
17 1.00 k RES, 1.00 k, 0.1%,
0.1 W, 0603 0603 RT0603BRD071KL Yageo America
R3 1 10 k
Res Thin Film 0603
10K Ohm 0.1%
1/10W ±10ppm/°C
Molded SMD SMD
Punched Carrier T/R
0603 ERA-3ARB103V Panasonic
R4, R21, R24, R31 4 0
RES, 0, 5%, 0.1 W,
AEC-Q200 Grade 0,
0603
0603 ERJ-3GEY0R00V Panasonic
R5 1 120 k RES, 120 k, 0.1%, 0.1
W, 0603 0603 RG1608P-124-B-T5 Susumu Co Ltd
R6 1 0.047
RES, 0.047, 1%, 0.1
W, AEC-Q200 Grade
1, 0603
0603 ERJ-L03KF47MV Panasonic
R8, R9, R10, R11,
R51, R52, R53, R54,
R55, R56, R57, R58
12 100 k
RES, 100 k, 0.5%, 0.1
W, AEC-Q200 Grade
0, 0603
0603 CRCW0603100KDHE
AP Vishay-Dale
R12, R13, R14, R15,
R16, R17, R18, R19,
R20, R41, R42, R43,
R44, R45, R48, R49,
R50, R62
18 49.9 RES, 49.9, 0.5%, 0.1
W, 0603 0603 RT0603DRE0749R9L Yageo America
R25, R35 2 47.5 RES, 47.5, 0.1%, 0.1
W, 0603 0603 RT0603BRD0747R5L Yageo America
R61 1 0.1
RES, 0.1, 1%, 0.1 W,
AEC-Q200 Grade 1,
0603
0603 ERJ-L03KF10CV Panasonic
R63, R64 2 6.65 k
RES, 6.65 k, 1%,
0.063 W, AEC-Q200
Grade 0, 0402
0402 CRCW04026K65FKE
DVishay-Dale
SH-J1, SH-J2, SH-J3,
SH-J4 4 1x2 Shunt, 100mil, Flash Gold, Black
Closed Top 100mil
Shunt SPC02SYAN Sullins Connector Solutions
TP1, TP2, TP6, TP8,
TP9 5
Test Point,
Multipurpose, Black,
TH
Black Multipurpose
Testpoint 5011 Keystone Electronics
TP3, TP4, TP5, TP7 4
Test Point,
Multipurpose,
Orange, TH
Orange Multipurpose
Testpoint 5013 Keystone Electronics
Bill of Materials, Layout, and Schematics www.ti.com
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