Texas Instruments TSW14J50 User manual

User's Guide
SLAU576–May 2014
TSW14J50 JESD204B High-Speed Data Capture and
Pattern Generator Card User's Guide
This user's guide describes the characteristics, operation, and use of the TSW14J50 JESD204B high-
speed data capture and pattern generator card. This document details the TSW14J50 functionality,
hardware configuration, the software start-up instructions, and how to download the firmware.
Contents
1 Introduction ................................................................................................................... 2
2 Functionality .................................................................................................................. 2
2.1 ADC EVM Data Capture .......................................................................................... 4
2.2 DAC EVM Pattern Generator (currently, function is not available)........................................... 5
3 Hardware Configuration..................................................................................................... 5
3.1 Power Connections ................................................................................................ 5
3.2 Switches, Jumpers, and LEDs .................................................................................... 6
3.3 LEDs ................................................................................................................. 7
3.4 Connectors .......................................................................................................... 7
4 Software Start-Up .......................................................................................................... 10
4.1 Installation Instructions ........................................................................................... 10
4.2 USB Interface and Drivers ....................................................................................... 10
4.3 Downloading Firmware ........................................................................................... 12
List of Figures
1 TSW14J50EVM ............................................................................................................. 2
2 TSW14J50 EVM Block Diagram........................................................................................... 4
3 GUI Installation ............................................................................................................. 10
4 TSW14J50EVM Serial Number .......................................................................................... 11
5 High-Speed Data Converter Pro GUI Top Level....................................................................... 11
6 Hardware Device Manager................................................................................................ 12
7 Select ADC Firmware to be Loaded..................................................................................... 12
8 Download Firmware Error Message ..................................................................................... 13
9 HSDC Pro GUI with ADS42JBxx EVM GUI Tab....................................................................... 13
List of Tables
1 Switch Description of the TSW14J50 Device ............................................................................ 6
2 Jumper Description of the TSW14J50 Device ........................................................................... 6
3 Power and Configuration LED Description of the TSW14J50 Device ................................................ 7
4 FPGA FMC connector (J5) description of the TSW14J10.............................................................. 7
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Introduction www.ti.com
1 Introduction
The TI TSW14J50 evaluation module (EVM) is a low-cost pattern generator and data capture card used to
evaluate performances of the new TI JESD204B device family of high-speed analog-to-digital converters
(ADC) and digital-to-analog converters (DAC). For an ADC, by capturing the sampled data over a
JESD204B interface when using a high-quality, low-jitter clock, and a high-quality input frequency, the
TSW14J50 can be used to demonstrate datasheet performance specifications. Using Altera JESD204B IP
cores, the TSW14J50 can be dynamically configurable to support lane speeds from 600 Mbps to 6.5
Gbps, from 1 to 8 lanes, multiple converters, and multiple octets per frame with one firmware build.
Together with the accompanying High-Speed Data Converter Pro Graphic User Interface (GUI), it is a
complete system that captures and evaluates data samples from ADC EVMs and generates and sends
desired test patterns to DAC EVMs.
2 Functionality
The TSW14J50EVM has a single industry-standard FMC connector that interfaces directly with TI
JESD204B ADC and DAC EVMs. When used with an ADC EVM, high-speed serial data is captured, de-
serialized and formatted by an Altera Arria V GX FPGA. The data is then stored into an external DDR3
memory bank, enabling the TSW14J50 to store up to 256M 16-bit data samples. To acquire data on a
host PC, the FPGA reads the data from memory and transmits it on a serial peripheral interface (SPI). An
onboard high-speed USB-to-SPI converter bridges the FPGA SPI interface to the host PC and GUI.
In pattern generator mode, the TSW14J50 generates desired test patterns for DAC EVMs under test.
These patterns are sent from the host PC over the USB interface to the TSW14J50. The FPGA stores the
data received into the board DDR3 memory module. The data from memory is then read by the FPGA and
transmitted to a DAC EVM across the JESD204B interface connector. The board contains a 100-MHz
oscillator used to generate the DDR3 reference clock.
Figure 1 shows the TI TSW14J50EVM.
Figure 1. TSW14J50EVM
Microsoft, Windows are registered trademarks of Microsoft Corporation.
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www.ti.com Functionality
The major features of the TSW14J50 are:
• Subclasses: 0 (backward compatible), 1
• Support for deterministic latency
• Serial lane speeds up to 6.5 Gbps (4 lanes or less)
• 8 routed transceiver channels
• 4Gb DDR3 SDRA. Quarter-rate DDR3 controllers supporting up to 667-MHz operation
• 256K 16-bit samples of internal FPGA memory
• Supports 1.8-V to 3.3-V CMOS IO standard
• Onboard FT4232HL USB device for JTAG and SPI emulation
• Reference clocking for transceivers available through FMC port or SMAs
• Supported by TI HSDC PRO software
• FPGA firmware developed with Quartus II 13.0 and QSYS
– JESD RX IP core with support for:
• SPI and JTAG reconfigurable JESD core parameters: L, M, K, F, HD, S, and more
• ILA configuration data accessible through SPI and JTAG
• Lane alignment and character replacement enabled or disabled through SPI and JTAG
– JESD TX IP core with support for:
• SPI and JTAG reconfigurable JESD core parameters: L, M, K, F, HD, S, and more
• ILA data configured through SPI and JTAG
• Character replacement enabled or disabled through SPI and JTAG
– Dynamically reconfigurable transceiver data rate. Operating range from 0.600–6.5 Gbps
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Figure 2 shows a block diagram of the TSW14J50 EVM.
Figure 2. TSW14J50 EVM Block Diagram
2.1 ADC EVM Data Capture
New TI high-speed ADCs and DACs now have high-speed serial data that meets the JESD204B standard.
These devices are generally available on an EVM that connects directly to the TSW14J50EVM. The
common connector between the EVMs and the TSW14J50EVM is a Samtec high-speed, high-density
FMC connector (SEAF-40-05.0-S-10-2-A-K) suitable for high-speed differential pairs up to 21 Gbps. A
common pinout for the connector across a family of EVMs has been established. At present, the interface
between the EVMs and the TSW14J50EVM has defined connections for 8 lanes of serial differential data,
two device clock pairs, two SYSREF pairs, two SYNC pairs, four over-range single-ended indicators, and
26 spare general purpose signals that can be used as CMOS I/O pins or differential LVDS signals. There
are also two differential clock input pairs.
The data format for JESD204B ADCs and DACs is a serialized format, where individual bits of the data
are presented on the serial pairs commonly referred to as lanes. Devices designed around the JESD204B
specification can have up to 8 lanes for transmitting or receiving data. The firmware in the FPGA on the
TSW14J50 is designed to accommodate any of TI's ADC or DAC operating with any number of lanes from
1 to 8.
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The GUI loads the FPGA with the appropriate firmware and a specific JESD204B configuration, based on
the ADC device selected in the device drop-down window. Each ADC device that appears in this window
has an initialization file (.ini) associated to it. This .ini file contains JESD information, such as number of
lanes, number of converters, octets per frame, and other parameters. This information is loaded into the
FPGA registers after the capture button is clicked. After the parameters are loaded, synchronization is
established between the data converter and FPGA and valid data is then captured into the on-board
memory. See the High-Speed Data Capture Pro GUI Software User's Guide (SLWU087) and section 2.3
in the guide for more information. Several .ini files are available to allow the user to load pre-determined
ADC JESD204B interfaces. For example, if the ADC called "ADS42JB69_LMF_421" is selected, the
FPGA will be configured to capture data from the ADS42JB69EVM with the ADC JESD interface
configured for 4 lanes, 2 converters, and 1 octet per frame.
The TSW14J50 device can capture up to 256M 16-bit samples at a maximum line rate of 6.5 Gbps that
are stored inside the on-board DDR3 memory. To acquire data on a host PC, the FPGA reads the data
from memory and transmits it on a serial protocol interface (SPI). An on-board high-speed USB-to-SPI
converter bridges the FPGA SPI interface to the host PC and GUI.
2.2 DAC EVM Pattern Generator (currently, function is not available)
In pattern generator mode, the TSW14J50EVM generates desired test patterns for DAC EVMs under test.
These patterns are sent from the host PC over the USB interface to the TSW14J50. The FPGA stores the
data received into the on-board DDR3 memory. The data from the memory is then read by the FPGA,
converted to JESD204B serial format, then transmitted to a DAC EVM. The TSW14J50 can generate
patterns up to 256M 16-bit samples at a line rate up to 6.5 Gbps.
The GUI comes with several existing test patterns that can be download immediately. The GUI also has a
pattern generation tool that allows the user to generate a custom pattern, then download it to the on-board
memory. See the High-Speed Data Capture Pro Software User's Guide (SLWU087) for information. Like
the ADC capture mode, the DAC pattern generator mode uses .ini files to load predetermined JESD204B
interface information to the FPGA.
3 Hardware Configuration
This section describes the various portions of the TSW14J50EVM hardware.
3.1 Power Connections
The TSW14J50EVM hardware is designed to operate from a single supply voltage of +5 V DC. Connect
the +5 V DC output of the provided AC-to-DC power supply to J11 of the EVM. Connect the other power
supply cable to 100-240 VAC, 50 to 60-Hz source. The board can also be powered up by providing +5 V
DC to the red test point, TP34, and the return to any black GND test point. The TSW14J50 draws
approximately 0.2 A at power-up and 0.8 A when capturing 4 lanes of data from an ADS42JB69EVM at a
line rate of 2.5 Gpbs.
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3.2 Switches, Jumpers, and LEDs
3.2.1 Switches and Pushbuttons
The TSW14J50 contains several switches and pushbuttons that enable certain functions on the board.
The description of the switches is found in Table 1.
Table 1. Switch Description of the TSW14J50 Device
Component Description
SW1 Spare dip switches that are connected to spare FPGA inputs
SW2 and SW3 Spare pushbutton that are connected to spare FPGA inputs
SW4 (CPU RESET) FPGA hardware reset
SW5 Sets IO voltage of FPGA bank 5. All switches open, IO voltage = 1.4 V . Default
is switch 2 closed only to provide 1.8 V to IO of Bank 5.
SW5 switch 1 closed adds 0.2 V to 1.4 V IO voltage
SW5 switch 2 closed adds 0.4 V to 1.4 V IO voltage
SW5 switch 3 closed adds 0.8 V to 1.4 V IO voltage
SW5 switch 4 closed adds 1.6 V to 1.4 V IO voltage
3.2.2 Jumpers
The TSW14J50 contains several jumpers (JP) and solder jumpers (SJP) that enable certain functions on
the board. The description of the jumpers is found in Table 2.
Table 2. Jumper Description of the TSW14J50 Device
Component Description Default
JP4, JP5, JP6, and JP7 USB or JTAG control of FPGA programming. Default is USB control. 1 to 2
JP8 USB or internal 5-V power for USB interface. Default is internal power. 1 to 2
JP9 USB 3.3 V regulator enable. Default is enabled. 2 to 3
SJP2 Direction control for PIO_9 signal of buffer U29. Default is B to A. 1 to 2
SJP3 Direction control for PRESENT signal of buffer U29. Default is B to A. 2 to 3
JP10 Selects either external power or Variable power (default) net for FPGA bank 5 IO 1 to 2
supply. This is the IO voltage set by SW5.
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3.3 LEDs
3.3.1 Power and Configuration LEDs
LEDs are on the TSW14J50 EVM to indicate the presence of power and the state of the FPGA. The
description of these LEDs is found in Table 3.
Table 3. Power and Configuration LED Description of the TSW14J50 Device
Component Description
D10 On if +5-V input power is present
D28 On after FPGA completes configuration
3.3.2 Status LEDs
Eight status LEDs on the TSW14J50EVM indicate the status of the FPGA, DDR3, and JESD204B
interface:
D1 – Indicates DAC EVM established SYNC with the TSW14J50 device when on
D2 – Indicates presence of device clock from DAC EVM when blinking
D3 – Indicates ADC EVM established SYNC with the TSW14J50 device when on
D4 – Indicates presence of device clock from ADC EVM when blinking
D5 – Not used
D6 – DDR3 initialization and calibration complete when off
D7 – DDR3 ready when off
D8 – DDR3 pass calibration and initialization if on
3.4 Connectors
3.4.1 FPGA Mezzanine Card (FMC) Connector
The TSW14J50 EVM has one connector to allow for the direct plug in of TI JESD204B serial interface
ADC and DAC EVMs. The specifications for this connector are mostly derived from the ANSI/VITA 57.1
FPGA Mezzanine Card (FMC) Standard. This standard describes the compliance requirements for a low-
overhead protocol bridge between the IO of a mezzanine card and an FPGA processing device on a
carrier card. This specification is being used by FPGA vendors on their development platforms.
The FMC connector, J4, provides the interface between the TSW14J50EVM and the ADC or DAC EVM
under test. This 400-pin Samtec high-speed, high-density connector (part number SEAF-40-05.0-S-10-2-
A-K) is suitable for high-speed differential pairs up to 21 Gbps.
In addition to the JESD204B standard signals, 26 CMOS single-ended signals are sourced from the FPGA
to the connector. In the future, these signals may allow the HSDC Pro GUI to control the SPI serial
programming of ADC and DAC EVMs that support this feature. The connector pinout description is shown
in Table 4.
Table 4. FPGA FMC connector (J5) description of the TSW14J10
FMC Signal Name FMC Pin Standard JESD204 Description
Application Mapping
DP0_M2C_P/N C6/C7 Lane 0+/- (M->C) JESD Serial data transmitted from Mezzanine and received by Carrier
DP1_M2C_P/N A2/A3 Lane 1+/- (M->C) JESD Serial data transmitted from Mezzanine and received by Carrier
DP2_M2C_P/N A6/A7 Lane 2+/- (M->C) JESD Serial data transmitted from Mezzanine and received by Carrier
DP3_M2C_P/N A10/A11 Lane 3+/- (M->C) JESD Serial data transmitted from Mezzanine and received by Carrier
DP4_M2C_P/N A14/A15 Lane 4+/- (M->C) JESD Serial data transmitted from Mezzanine and received by Carrier
DP5_M2C_P/N A18/A19 Lane 5+/- (M->C) JESD Serial data transmitted from Mezzanine and received by Carrier
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Table 4. FPGA FMC connector (J5) description of the TSW14J10 (continued)
DP6_M2C_P/N B16/B17 Lane 6+/- (M->C) JESD Serial data transmitted from Mezzanine and received by Carrier
DP7_M2C_P/N B12/B13 Lane 7+/- (M->C) JESD Serial data transmitted from Mezzanine and received by Carrier
DP0_C2M_P/N C2/C3 Lane 0+/- (C->M) JESD Serial data transmitted from Carrier and received by Mezzanine
DP1_C2M_P/N A22/A23 Lane 1+/- (C->M) JESD Serial data transmitted from Carrier and received by Mezzanine
DP2_C2M_P/N A26/A27 Lane 2+/- (C->M) JESD Serial data transmitted from Carrier and received by Mezzanine
DP3_C2M_P/N A30/A31 Lane 3+/- (C->M) JESD Serial data transmitted from Carrier and received by Mezzanine
DP4_C2M_P/N A34/A35 Lane 4+/- (C->M) JESD Serial data transmitted from Carrier and received by Mezzanine
DP5_C2M_P/N A38/A39 Lane 5+/- (C->M) JESD Serial data transmitted from Carrier and received by Mezzanine
DP6_C2M_P/N B36/B37 Lane 6+/- (C->M) JESD Serial data transmitted from Carrier and received by Mezzanine
DP7_C2M_P/N B32/B33 Lane 7+/- (C->M) JESD Serial data transmitted from Carrier and received by Mezzanine
GBTCLK0_M2C_P/N D4/D5 DEVCLKA+/- (M->C) Primary carrier-bound reference clock required for FPGA gigabit transceivers.
Equivalent to device clock.
GBTCLK1_M2C_P/M B20/B21 Alt DEVCLKA+/- (M->C) Alternate primary carrier-bound reference clock required for FPGA gigabit
transceivers. Equivalent to device clock.
Device Clock, SYSREF, and SYNC
FMC Signal Name FMC Pin Standard JESD204 Description
Application Mapping
CLK_LA0_P/N G6/G7 DEVCLKB+/- (M->C) Secondary carrier-bound device clock. Used for special FPGA functions such as
sampling SYSREF.
LA01_P/N_CC_A D8/D9 DEVCLK+/- (C->M) Mezzanine-bound device Clock. Used for low noise conversion clock. 2.5V level
SYSREFP/N G9/G10 SYSREF+/- (M->C) Carrier-bound SYSREF signal
LA05_P/N_A D11/D12 SYSREF+/- (C->M) Mezzanine-bound SYSREF differential signal, 2.5V level
RX_SYNC_P/N G12/G13 SYNC+/- (C>M) ADC Mezzanine-bound SYNC signal for use in class 0/1/2 JESD204 systems
TX_SYNC_P/N F10/F11 DAC SYNC+/- (M>C) Carrier-bound SYNC signal for use in class 0/1/2 JESD204 systems.
TX_ALT_SYNC_P/N F19/F20 Alt. DAC SYNC+/- (M>C) Alternate Carrier-bound SYNC signal for use in class 0/1/2 JESD204B systems.
RX_CMOS_SYNC_P H31 Alt. SYNC+/- (C>M) Alternate ADC Mezzanine-bound SYNC signal. For use when SYNC (C->M) is not
available.
RX_ALT_SYNC_N H32 Alt. SYNC+/- (C>M) Alternate ADC Mezzanine-bound SYNC signal. For use when SYNC (C->M) is not
available.
TX_TRG K22 TX trigger input or spare IO, adjustable level*
Special Purpose I/O
FMC Signal Name FMC Pin Direction Description
PG_M2C_A F1 FMC-to-FPGA Power good from mezzanine to carrier
PRESENT H2 FMC-to-FPGA EVM Present indicator or spare IO signal, adjustable level
PIO_0 C14 FPGA-to-FMC Spare output signal, adjustable level*
PIO_1 C15 FPGA-to-FMC Spare output signal, adjustable level*
PIO_2 D14 FPGA-to-FMC Spare output signal, adjustable level*
PIO_3 D15 FPGA-to-FMC Spare output signal, adjustable level*
PIO_4 G15 FPGA-to-FMC Spare output signal, adjustable level*
PIO_5 G16 FPGA-to-FMC Spare output signal, adjustable level*
PIO_6 H16 FPGA-to-FMC Spare output signal, adjustable level*
PIO_7 H17 FPGA-to-FMC Spare output signal, adjustable level*
OVRA K19 ADC-to-FPGA ADC over range indicator or spare IO, adjustable level*
OVRB E18 ADC-to-FPGA ADC over range indicator or spare IO, adjustable level*
OVRC J22 ADC-to-FPGA ADC over range indicator or spare IO, adjustable level*
OVRD J21 ADC-to-FPGA ADC over range indicator or spare IO, adjustable level*
FPGA_CLK2P/N J2/J3 FPGA-to-DAC Spare IO signal, 2.5V level
FPGA_CLK1P/N K4/K5 FPGA-to-DAC Spare IO signal, 2.5V level
PIO_9 C18 FMC-to-FPGA Spare IO signal, adjustable level*
LA13_P_A D17 FPGA-to-ADC Spare IO signal, 2.5V level
LA13_N_A D18 FPGA-to-ADC Spare IO signal, 2.5V level
HA20_N_A E19 FPGA-to-FMC Spare IO signal, adjustable level*
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Table 4. FPGA FMC connector (J5) description of the TSW14J10 (continued)
LA17_P/N_CC_A D20/D21 FPGA-to-FMC Spare IO signal, 2.5V level
LA23_P/N_A D23/D24 FPGA-to-FMC Spare IO signals, 2.5V level
LA16_P_A G18 FPGA-to-FMC Spare IO signal, adjustable level*
SP1 K20 FPGA-to-FMC Spare IO signal, adjustable level*
CLK0_M2C_P/N_A H4/H5 FPGA-to-FMC Spare FPGA CLK input connections
CLK1_M2C_P/N_A G2/G3 FPGA-to-FMC Spare FPGA CLK input connections
* The level of these signals is controlled by SW5 when JP10 has a shunt installed between pins 1-2. With
the shunt installed between pins 2-3, the external voltage applied to TP40 will determine the level of these
signals.
WARNING
In the external supply mode, make sure the external supply does
not exceed 3.3 VDC to prevent damage occurring to the FPGA.
The ANSI/VITA 57.1 standard assigns voltages to certain pins. These are labeled as 12V, 3P3V, and
VADJ nets on the connector page of the schematic. On the TSW14J50, these pins are connected to test
points allowing user-provided voltages at these pin locations.
3.4.2 SMA Connectors
The TSW14J50 has two SMA connectors, J7 and J8, that can be used as a SYNC outputs. These signals
will be driven by the FPGA. Another SMA, J13, can be used as a trigger input to the FPGA. To
synchronize multiple TSW14J50 boards, the user would connect one of the SYNC outputs from a master
TSW14J50 EVM to the EXT Trigger input SMA of a slave TSW14J50 EVM. This function is currently not
available.
3.4.3 JTAG Connectors
The TSW14J50EVM includes one industry-standard JTAG connector that connects to the JTAG ports of
the FPGA. Jumpers on the TSW14J50EVM allow for the FPGA to be programmed from the JTAG
connector or the USB interface. JTAG connector J2 is used for troubleshooting only. The board default
setup is with the FPGA JTAG pins connected to the USB interface. This allows the FPGA to be
programmed by the HSDC Pro software GUI. Every time the TSW14J50EVM is powered-down, the FPGA
configuration is removed. The user must program the FPGA through the GUI after every time the board is
powered-up.
3.4.4 USB I/O Connection
Control of the TSW14J50EVM is through USB connector J9. This provides the interface between the
HSDC Pro GUI running on a Microsoft®Windows®operating system and the FPGA. For the computer, the
drivers needed to access the USB port are included on the HSDC Pro GUI installation software that can
be downloaded from the web. The drivers are automatically installed during the installation process. On
the TSW14J50EVM, the USB port is used to identify the type and serial number of the EVM under test,
load the desired FPGA configuration file, capture data from ADC EVMs, and send test pattern data to the
DAC EVMs.
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4 Software Start-Up
4.1 Installation Instructions
Download the latest version of the HSDC Pro GUI (slwc107x.zip) to a local location on a host PC. Visit
www.ti.com and find the install link on the TSW14J50EVM page.
Unzipping the software package generates a folder called “High Speed Data Converter Pro - Installer
vx.xx.exe", where x.xx is the version number. Run this program to start the installation.
Follow the on-screen instructions during installation.
NOTE: If an older version of the GUI has already been installed, make sure to uninstall it before
loading a newer version.
Figure 3. GUI Installation
Make sure to disconnect all USB cables from any TSW14xxx boards before installing the software.
Click the Install button. A new window opens. Click the Next button.
Accept the license agreement. Click the Nextbutton to start the installation. After the installer has finished,
click the Nextbutton.
The installation is now complete. The GUI executable and associated files reside in the following directory:
C:\Program Files (x86)\Texas Instruments\High Speed Data Converter Pro.
4.2 USB Interface and Drivers
• Connect a USB cable between J9 of the TSW14J50EVM and a host PC.
• Connect the provided +5 VDC source to the EVM and 100-240 VAC, 50 to 60-Hz source.
Click on the High-Speed Data Converter Pro icon that was created on the desktop panel, or go to
C:\Program Files (x86)\Texas Instruments\High Speed Data Converter Pro and double click on the
executable called High Speed Data Converter Pro.exe to start the GUI.
The GUI first attempts to connect to the EVM USB interface. If the GUI identifies a valid board serial
number, a pop-up opens displaying this value, as shown in Figure 4. Several TSW14J50 EVMs can
connect to one host PC, but the GUI can only connect to one at a time. When multiple boards are
connected to the PC, the pop-up displays all of the serial numbers found. The user then selects which
board to associate the GUI with.
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