Texas Instruments TPS7H1101SPEVM User manual

User’s Guide
TPS7H1101SPEVM User’s Guide
Table of Contents
1 Introduction.............................................................................................................................................................................2
1.1 Related Documentation......................................................................................................................................................2
2 Description.............................................................................................................................................................................. 2
3 Test Setup................................................................................................................................................................................3
3.1 Equipment.......................................................................................................................................................................... 3
3.2 Bench Test Setup Conditions............................................................................................................................................. 3
3.3 Power-Up Procedure..........................................................................................................................................................4
4 Board Layout.........................................................................................................................................................................11
4.1 EVM Layout Flexibility...................................................................................................................................................... 11
5 Schematic and Bill of Materials...........................................................................................................................................17
Revision History.......................................................................................................................................................................20
List of Figures
Figure 3-1. Headers Description and Jumper Placement............................................................................................................3
Figure 3-2. IOUT (A) vs IPCL (uA)...............................................................................................................................................5
Figure 3-3. IOUT (A) vs IPCL (A) across CSR range.................................................................................................................. 5
Figure 3-4. VCS (V) vs IOUT (A)................................................................................................................................................. 6
Figure 3-5. IOUT (A) vs ICS (A)...................................................................................................................................................6
Figure 3-6. VDO vs IOUT ............................................................................................................................................................7
Figure 3-7. Load Transient Response: Step Load 0.1 A to 1.6 mA............................................................................................. 7
Figure 3-8. Expanded View Overshoot........................................................................................................................................8
Figure 3-9. Expanded View Undershoot......................................................................................................................................8
Figure 3-10. Current Sharing LDO_1 and LDO_2....................................................................................................................... 9
Figure 3-11. Disabling the LDO via Soft-Start Pin......................................................................................................................10
Figure 3-12. Turn-Off................................................................................................................................................................. 10
Figure 4-1. Component Placement (Top Side)...........................................................................................................................11
Figure 4-2. Component Placement (Bottom Side).....................................................................................................................12
Figure 4-3. PCB Layout (Top Layer).......................................................................................................................................... 13
Figure 4-4. Board Layout - Second Layer (Mid Layer 1)........................................................................................................... 14
Figure 4-5. Board Layout - Third Layer (Mid Layer 2)............................................................................................................... 15
Figure 4-6. Board Layout - Fourth Layer (Bottom Layer)...........................................................................................................16
Figure 5-1. TPS7H1101SPEVM Schematic...............................................................................................................................17
Trademarks
All trademarks are the property of their respective owners.
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TPS7H1101SPEVM User’s Guide 1
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1 Introduction
This user’s guide describes the characteristics, operation, and use of the TPS7H1101SP evaluation module
(EVM). This EVM demonstrates the Texas Instruments TPS7H1101-SP and the TPS7H1101A-SP ultra-low
dropout (LDO) regulator.
It is a radiation-hardened LDO linear regulator that uses a PMOS pass element configuration. It operates over a
wide range of input voltage, from 1.5 V to 7 V while offering excellent PSRR. The TPS7H1101A-SP features a
precise and programmable foldback current limit implementation with a very-wide adjustment range. To support
the complex power requirements of FPGAs, DSPs, or microcontrollers, the TPS7H1101A-SP provides enable on
and off functionality, programmable soft start, current sharing capability, and a Power Good open-drain output.
This user’s guide includes setup instructions, a schematic diagram, a bill of materials (BOM), and PCB layout
drawings for the EVM.
1.1 Related Documentation
1. TPS7H1101A (SLVSDW6) Data Sheet
2 Description
The TPS7H1101SPEVM helps designers evaluate the operation and performance of the TPS7H1101A-SP ultra
LDO regulator.
Table 2-1. Summary of Performance
Test Conditions Output Current Range
VIN = 1.5 V to 7 V Max 3 A
The evaluation module is designed to provide access to the features of the TPS7H1101A-SP. Some
modifications can be made to this module to test performance with various input and output voltages and loads.
Please reference TI E2ETM support forums for information and questions related to this EVM.
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3 Test Setup
3.1 Equipment
3.1.1 Power Supplies
Power Supply #1 (PS#1): a power supply capable of supplying 7-V at 5-A or higher is required.
3.1.2 Load Number 1
Electronic load, that is, Chroma 63640-80-80 module along with 63600-2 DC electronic load Mainframe or
Decade Resistor Box.
3.1.3 Meters
Four (4) Fluke 75, (equivalent or better) or two (2) equivalent voltage meters and two (2) equivalent current
meters.
The current meters must be able to measure 5 A current. Note: Shunt along with DVM can be used to monitor
output current.
3.1.4 Oscilloscope
An Tektronix Oscilloscope, for example, DPO 7104CCurrent Probe Tektronix TCP202 or equivalent.
3.2 Bench Test Setup Conditions
3.2.1 Headers Description and Jumper Placement
Figure 3-1. Headers Description and Jumper Placement
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3.2.2 Testing
Table 3-1. Power Connectors
No. Function
J19 VIN input voltage connector (see Section 3.2.2 for VIN range)
J24 VIN input voltage connector to ground
J27 VOUT output voltage connector
J28 VOUT output connector to ground
J7 Vin_SMA
J22 EN_SMA
J20 SS_Probe
J5 LDO_OUT_Probe
TP8 LDO Vout measure point (+)
TP9 LDO Vout measure point (GND)
J6 LDO_OUT_SMA
TP7 LDO Vin measure point (+)
TP12 LDO Vin measure point (GND)
TP10 PCL
J21 CS_SMA
TP13 PG (Power Good)
TP11 SS
JMP10 VIN alternative connection: 1,2 (+) and 3,4 (GND)
JMP8 VOUT alternative connection 3,4 (+) and 1,2 (GND)
3.3 Power-Up Procedure
The following test proceedure and results are based on testing of the default configuration of the EVM. The EVM
by default is configured to output 1.8 V.
Table 3-2. Test Results
VOUTMIN VOUTMAX Current Limit Current Foldback
VOUT = 1.8 V 1.76 V 1.836 V < 3.8 A < 1.9 A OUTPUT SET POINT
IOUT = 3 A 1.8166 V 3.5 A CURRENT LIMIT
3.3.1 IOUT and VOUT Measurements
1. Make sure all power supplies in workstation are OFF.
2. Locate connectors J19 and J24.
3. Connect VIN(+) to J19 and V(GND) to J24. Set it to 2.3 V.
4. Locate measure points TP7 and TP12.
5. Connect voltmeter: VIN(+) to TP7 and V(GND) to TP12.
6. Locate connectors J27 and J28 and connect load here (be aware of polarities).
7. Locate measure points TP8 and TP9.
8. Connect voltmeter: VOUT(+) to TP8 and V(GND) to TP9.
9. Output voltage should be per Table 2-1. This is done by setting R27 = 19.8 kΩ and R28 = 10 kΩ.
VOUT can be determined by equation highlighted below or per equation 1 in the data sheet.
V =
OUT
( )R + R V
27 28 REF
·
¾
R28
(1)
Where VREF = 0.605 V.
3.3.2 Output Current Limiting
A resistor value R30 connected from PCL pin to GND determines the output current limit set point based on
Equation 2.
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Maximum programmable current limit is 3800 mA.
4L?H =430 =%54k8
NAB o
(+?H F.0403)
(2)
Where VREF = 0.605 V, Icl = programmable current limit (A), CSR = Current sense ratio (typical value = 52000).
CSR between Ics pin and IOUT can be measured as shown in Figure 3-2.
See Figure 3-3 for device Iload vs PCL pin current ranges.
• Make sure all power supplies in workstation are OFF.
• Connect VIN(+) to J19 & V(GND) to J24 and set it to 2.3 V.
• Set VOUT to 1.8V. (R27 = 19.8 kΩ and R28 = 10 kΩ)
• Connect load as previously instructed, set it to zero load.
• Increase Iload (steps of 0.100 A are suggested) until Vload starts to drop.
• Current limit trip point < 3.8 A.
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
0 10 20 30 40 50 60 70 80 90 100
Output Current (A)
PCL Pin Current (µA) C001
VIN = 2.3 V
VOUT = 1.8 V
y = 47394x + 0.0403
Figure 3-2. IOUT (A) vs IPCL (uA)
IPCL (A)
ILOAD (A)
ILOAD Vs IPCL across CSR range
0x10010x10-6 20x10-6 30x10-6 40x10-6 50x10-6 60x10-6 70x10-6 80x10-6
0
1
2
3
4
5
6
CSR_
Min CSR: ILOAD = 45000 * IPCL +0.0403
25c Nom CSR: ILOAD = 52000 * IPCL +0.0403
125c Max CSR: ILOAD = 56000 * IPCL +0.0403
-55c Max CSR: ILOAD = 65000 * IPCL +0.0403
Figure 3-3. IOUT (A) vs IPCL (A) across CSR range
3.3.3 High-Side Current Sense
Monitoring the voltage at the CS pin will indicate voltage proportional to the output current. Figure 3-4 shows
typical curve VCS vs IOUT for Vin = 2.28 V and R23 = 3.65 kΩ. A resistor connected from current sense (CS) pin
to VIN indicates voltage proportional to the output current.
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2.00
2.05
2.10
2.15
2.20
2.25
2.30
2.35
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
CS Pin Voltage (V)
Load Current (A) C003
VIN = 2.3 V
VOUT = 1.8 V
y = 0.078x + 2.2853
Figure 3-4. VCS (V) vs IOUT (A)
Monitoring current in CS pin (ICS vs IOUT) indicates the current sense ratio between the main PMOSFET and the
current sense MOSFET as shown in Figure 3-5. This plot shows that the CSR ratio is independent of VCS
voltage. Note that VCS must be above 0.3V to insure proper biasing, and also must be greater than 0.9 x VREF
(0.544 V) to have foldback current limit enabled.
ICS (uA)
ILOAD (A)
0 10 20 30 40 50 60 70 80
0
0.5
1
1.5
2
2.5
3
3.5
VCS_
ICS (uA) vs ILOAD at VCS = 0.3V
ICS (uA) vs ILOAD at VCS = 2.3V
ICS (uA) vs ILOAD at VCS = 5V
Figure 3-5. IOUT (A) vs ICS (A)
3.3.4 Current Foldback
1. When current sense (CS) pin is held high, foldback current limit is enabled. Shorting CS low will disable the
foldback current limit.
2. With foldback current limit enabled, when current limit trip point is activated,
a. Output voltage will drop low.
b. output current will fold back to approx. 50% of the current limit trip point.
This results in minimizing the power loss under fault conditions.
3.3.5 Power Good
Power good pin is an open-drain connection, connect it high via pull up resistor to external voltage source.
Power Good pin indicates the status of the output voltage.
3.3.6 Dropout Voltage
Drop out voltage (VDO) is the difference between the input voltage and output voltage needed to maintain
regulation. VDO vs IOUT is highlighted in Figure 3-6.
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0
50
100
150
200
250
300
350
0 0.5 1 1.5 2 2.5 3
Dropout Voltage (mV)
IOUT (A)
-55 °C
25 °C
125 °C
Figure 3-6. VDO vs IOUT
3.3.7 Transient Response
Waveforms below indicate the transient response behavior of the LDO for 50% step load change.
Channel 1: Output voltage overshoot / undershoot
Channel 2: Step load in current
Channel 3: Input voltage
Figure 3-7. Load Transient Response: Step Load 0.1 A to 1.6 mA
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Figure 3-8. Expanded View Overshoot
Figure 3-9. Expanded View Undershoot
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3.3.8 Current Sharing
For demanding load requirements, multiple LDOs can be paralleled.
• In parallel mode CS pin of LDO#1 must be connected to PCL pin of LDO#2 via a series resistor
(3.75 kΩ) and CS pin of LDO#2 must be connected to PCL pin of LDO#1 via series resistor (3.75 kΩ).
• In parallel configuration R30 (resistor from PCL to GND) and R23 (resistor from CS pin to VIN) must be left
open (unpopulated).
35.00
40.00
45.00
50.00
55.00
60.00
65.00
0123456
% of total Load
Output Current
LDO1
LDO2
Figure 3-10. Current Sharing LDO_1 and LDO_2
3.3.9 Soft-Start
Connecting a capacitor on CS pin to GND (C35) slows down the output voltage ramp rate. The soft-start
capacitor will charge up to 1.2 V.
C =
35
¾
t I
ss ss
·
VREF
(3)
Where:
tss = Soft-start time
Iss = 2.5 µA
VREF = 0.605 V
3.3.10 Enable and Disable
EVM can be disabled via pulling the enable pin low via shorting JMP7-1 (Enable) to JMP7-2 (GND). Enable pin
is tied high to VIN via R24 ( 20 kΩ) resistor, thus keeping the EVM enabled.
Alternately, EVM can also be disabled via pulling SS pin (U6 pin 1) low via an external circuit comprising of
2N7002 MOSFET as shown in Figure 3-11. A high signal at the gate of Q100 will discharge the SS pin and
disable the device.
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Figure 3-11. Disabling the LDO via Soft-Start Pin
3.3.11 Turn-Off
Figure 3-12. Turn-Off
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