Texas Instruments TPSM8D6C24 User manual

User’s Guide
TPSM8D6C24 2-Phase Power Module Evaluation Module
User's Guide
ABSTRACT
This user's guide describes the characteristics, operation, and use of the TPSM8D6C24EVM-2PH evaluation
module (EVM). In addition, the user's guide includes test information, descriptions, and results. A complete
schematic diagram, printed circuit board layouts, and bill of materials are also included in this document.
Table of Contents
1 Description.............................................................................................................................................................................. 3
1.1 Before You Begin............................................................................................................................................................... 3
1.2 Features............................................................................................................................................................................. 3
2 Electrical Performance Specifications................................................................................................................................. 4
3 Schematic................................................................................................................................................................................5
4 Test Setup................................................................................................................................................................................6
4.1 Test and Configuration Software........................................................................................................................................ 6
4.2 Test Equipment.................................................................................................................................................................. 6
4.3 List of Test Points, Jumpers, and Connectors....................................................................................................................7
4.4 Evaluating Split Rail Input.................................................................................................................................................. 8
5 EVM Configuration Using the Fusion GUI............................................................................................................................8
5.1 Configuration Procedure.................................................................................................................................................... 8
6 Test Procedure........................................................................................................................................................................ 8
6.1 Line and Load Regulation and Efficiency Measurement Procedure.................................................................................. 8
6.2 Efficiency Measurement Test Points.................................................................................................................................. 9
6.3 Control Loop Gain and Phase Measurement Procedure................................................................................................... 9
7 Performance Data and Typical Characteristic Curves...................................................................................................... 10
7.1 Efficiency..........................................................................................................................................................................10
7.2 Load Regulation............................................................................................................................................................... 10
7.3 Line Regulation.................................................................................................................................................................11
7.4 Transient Response......................................................................................................................................................... 11
7.5 Control Loop Bode Plot.................................................................................................................................................... 12
7.6 Output Ripple................................................................................................................................................................... 12
7.7 Control On........................................................................................................................................................................13
7.8 Control Off........................................................................................................................................................................14
7.9 Thermal Image................................................................................................................................................................. 15
8 EVM Assembly Drawing and PCB Layout.......................................................................................................................... 16
9 Bill of Materials..................................................................................................................................................................... 19
10 Using the Fusion GUI......................................................................................................................................................... 22
10.1 Opening the Fusion GUI................................................................................................................................................ 22
10.2 General Settings............................................................................................................................................................ 23
10.3 Changing ON_OFF_CONFIG........................................................................................................................................ 23
10.4 Pop-Up for Some Commands While Conversion is Enabled......................................................................................... 25
10.5 SMBALERT# Mask........................................................................................................................................................ 26
10.6 Device Info..................................................................................................................................................................... 27
10.7 Phase Commands..........................................................................................................................................................28
10.8 All Config........................................................................................................................................................................29
10.9 Pin Strapping..................................................................................................................................................................30
10.10 Monitor......................................................................................................................................................................... 31
10.11 Status........................................................................................................................................................................... 32
11 Revision History..................................................................................................................................................................32
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List of Figures
Figure 3-1. TPSM8D6C24EVM-2PH Schematic......................................................................................................................... 5
Figure 7-1. Efficiency................................................................................................................................................................. 10
Figure 7-2. Load Regulation...................................................................................................................................................... 10
Figure 7-3. Line Regulation........................................................................................................................................................11
Figure 7-4. Transient Response.................................................................................................................................................11
Figure 7-5. Bode Plot, 70-A Load.............................................................................................................................................. 12
Figure 7-6. Output Ripple, No Load...........................................................................................................................................12
Figure 7-7. Output Ripple, 70-A Load........................................................................................................................................13
Figure 7-8. Start-Up From Control, 70-A CC Load.................................................................................................................... 13
Figure 7-9. Shutdown From Control, 70-A CC Load..................................................................................................................14
Figure 7-10. Thermal Image...................................................................................................................................................... 15
Figure 8-1. TPSM8D6C24EVM-2PH Top Side Component View (Top View)............................................................................ 16
Figure 8-2. TPSM8D6C24EVM-2PH Bottom Side Component View (Bottom View).................................................................16
Figure 8-3. TPSM8D6C24EVM-2PH Top Copper (Top View)....................................................................................................16
Figure 8-4. TPSM8D6C24EVM-2PH Internal Layer 1 (Top View)............................................................................................. 16
Figure 8-5. TPSM8D6C24EVM-2PH Internal Layer 2 (Top View)............................................................................................. 17
Figure 8-6. TPSM8D6C24EVM-2PH Internal Layer 3 (Top View)............................................................................................. 17
Figure 8-7. TPSM8D6C24EVM-2PH Internal Layer 4 (Top View)............................................................................................. 17
Figure 8-8. TPSM8D6C24EVM-2PH Internal Layer 5 (Top View)............................................................................................. 17
Figure 8-9. TPSM8D6C24EVM-2PH Internal Layer 6 (Top View)............................................................................................. 18
Figure 8-10. TPSM8D6C24EVM-2PH Internal Bottom Layer (Top View)..................................................................................18
Figure 10-1. Select Device Scanning Mode.............................................................................................................................. 22
Figure 10-2. General Settings....................................................................................................................................................23
Figure 10-3. Configure – ON_OFF_CONFIG............................................................................................................................ 24
Figure 10-4. Pop-up When Trying to Change FREQUENCY_SWITCH With Conversion Enabled...........................................25
Figure 10-5. Configure – SMBALERT # Mask...........................................................................................................................26
Figure 10-6. Configure – Device Info.........................................................................................................................................27
Figure 10-7. Phase Commands.................................................................................................................................................28
Figure 10-8. Configure – All Config........................................................................................................................................... 29
Figure 10-9. Configure – Pin Strapping..................................................................................................................................... 30
Figure 10-10. Monitor Screen.................................................................................................................................................... 31
Figure 10-11. Status Screen...................................................................................................................................................... 32
List of Tables
Table 2-1. TPSM8D6C24EVM-2PH Electrical Performance Specifications................................................................................ 4
Table 4-1. Test Point Functions....................................................................................................................................................7
Table 4-2. Jumpers...................................................................................................................................................................... 7
Table 4-3. JP3 and JP4 Selections.............................................................................................................................................. 7
Table 4-4. JP1 and J2 Selections................................................................................................................................................ 8
Table 4-5. Connector Functions...................................................................................................................................................8
Table 6-1. Test Points for Efficiency Measurements.................................................................................................................... 9
Table 6-2. List of Test Points for Loop Response Measurements................................................................................................9
Table 9-1. TPSM8D624EVM-2PH Bill of Materials.................................................................................................................... 19
Trademarks
PMBus® is a registered trademark of System Management Interface Forum, Inc..
All trademarks are the property of their respective owners.
Trademarks www.ti.com
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1 Description
The TPSM8D6C24 is a configurable dual-output buck converter module. The TPSM8D6C24EVM-2PH uses a
nominal 12-V bus to produce a regulated 0.8-V output at up to 70 A of load current. The TPSM8D6C24EVM-2PH
demonstrates the dual phase capability.
1.1 Before You Begin
The following warnings and cautions are noted for the safety of anyone using or working close to the
TPSM8D6C24EVM-2PH. Observe all safety precautions.
Warning
The TPSM8D6C24EVM-2PH circuit module can become hot during operation due
to dissipation of heat. Avoid contact with the board. Follow all applicable safety
procedures applicable to the laboratory.
!
Caution Do not leave the EVM powered when unattended.
WARNING
The circuit module has signal traces, components, and component leads on the bottom of the board.
This can result in exposed voltages, hot surfaces, or sharp edges. Do not reach under the board
during operation.
CAUTION
The circuit module can be damaged by over temperature. To avoid damage, monitor the temperature
during evaluation and provide cooling, as needed, for the system environment.
CAUTION
Some power supplies can be damaged by application of external voltages. If using more than
one power supply, check the equipment requirements and use blocking diodes or other isolation
techniques, as needed, to prevent damage to the equipment.
CAUTION
The communication interface is not isolated on the EVM. Be sure no ground potential exists between
the computer and the EVM. Also be aware that the computer is referenced to the battery-potential of
the EVM.
1.2 Features
• Regulated 0.8-V output up to 70-ADC output current
• Convenient test points for probing critical waveforms
• PMBus® connector for easy connection with the TI USB adapter
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2 Electrical Performance Specifications
Table 2-1 lists the electrical performance specifications in room temperature (20°C to 25°C). Characteristics are
given for an input voltage of VIN = 12 V, unless otherwise specified.
Table 2-1. TPSM8D6C24EVM-2PH Electrical Performance Specifications
Parameter Test Conditions MIN TYP MAX Unit
Input Characteristics
Input voltage range, VIN 5 12 16 V
Full load input current IOUT = 70 A 5.8 A
VIN = 5 V, IOUT = 70 A 14 A
No load input current IOUT = 0 A, switching enabled 123 mA
Enable switching threshold Set by default resistor divider, JP3 and JP4 in UVLO
position 3.92 V
Disable switching threshold Set by default resistor divider, JP3 and JP4 in UVLO
position 3.50 V
Output Characteristics
Output voltage, VOUT 0.8
Output load current, IOUT 0 70 A
Output voltage regulation Line regulation: VIN = 5 V to 16 V 0.1%
Load regulation: IOUT = 0 A to 70 A 0.1%
Output overcurrent fault threshold Programmed by MSEL2 52 A
Systems Characteristics
Switching frequency Programmed by MSEL1 550 kHz
Operating case temperature IOUT = 70 A, Airflow = 200 LFM, 10 minute soak 99 °C
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3 Schematic
1 2
3 4
5 6
7 8
9 10
J2
P MBus
PMBus
PGND
Gre e n
2 1
LED1
1.00k
R42
47u F
C33
47u F
C29
47u F
C34
47u F
C35
47u F
C31
47u F
C30
47u F
C32
47u F
C26
47u F
C36
47u F
C20
47u F
C27
47u F
C28
PGND
VOUT
47u F
C55
47u F
C51
47u F
C56
47u F
C57
47u F
C53
47u F
C52
47u F
C54
47u F
C48
47u F
C58
47u F
C59
47u F
C49
47u F
C50
PGND
VOUT
VOUT
VOS NS _A
TP1
PVIN
TP8
CHB_Vout
TP2
PGND
100 uF
C8
100 uF
C7
PGND
TP7
CHA_Vout
1
2
T4
AVIN
PGND
PGND
Bode_Input
TP2 4
CLK
TP2 3
CNTL
TP2 6
DATA
TP2 5
S MBALRT
1
2
S MB1
VOUT
TP1 6
PGND
TP4
PGND
PGND
1
2
T1
PVIN
1
2
T2
PGND
47u F
C15
47u F
C16
47u F
C17
47u F
C18
47u F
C19
47u F
C37
47u F
C63
47u F
C64
47u F
C65
47u F
C66
47u F
C67
47u F
C68
47u F
C21
47u F
C22
47u F
C69
47u F
C70
PGND
VOUT
TP5
Re mote Se nse Vo ut (+)
TP9
Re mote Se nse Vo ut (-)
VOUT
S MBALT
CLK DATA
CNTL
PGND
1
2
J P8
P MBus to AVIN
VBUS
1
D-
2
D+
3
ID
4
GND
5
67 8
11 10
9
J1
Micro-US B Po we r
PGND
1
2
J P7
USB to P VIN
PVIN
PVIN
30V
D1
30V
D2
HW1
BS R1 93 A_Ha rdwa re . Sc hDoc
Input: 2.95 V to 16 V
Output: 0.5 V to 3.6 V at 70 A
PGND
SYNC 29
EN_B
25
SMB_ALRT_A 6
P GND 1
AGND_A
21
P GND 4
AGND_B
27
PVIN_A
18
AVIN_A
20
PMB_DATA_A 8
PVIN_A
55
PVIN_B
24
PVIN_B
56
PMB_C LK_A 7
VOS NS_ A 2
VOUT_A 50
VOUT_A 51
P GND 52
BCX_CLK_A 11
S W_A 53
P GND
17
P GND
23
P GND 43
S W_B 58
VOUT_B 47
VOUT_B 48
P GND 49
AVIN_B
26
VOS NS_ B 45
P GND 46
P GD/RS T_ A 9
P GND 30
EN_A
19
PMB_DATA_B 39
PMB_C LK_B 40
SMB_ALRT_B 41
BCX_DATA_A 10
BCX_CLK_B 36
P GD/RS T_ B 38
BCX_DATA_B 37
P GND
54
P GND
57
P GND 59
VDD5_A
22
BP1 V5_A
5
VSEL_A
15
ADRSE L_A
14
MSEL1_ A
13
VSHARE_ A
12
MSEL2_ A
16
VDD5_B
28
GO S NS /FLWR_A 3
BP1 V5_B
42
GO S NS /FLWR_B 44
VSHARE_ B
35
MSEL2_ B
31
VSEL_B
32
ADRSE L_B
33
MSEL1_ B
34
U1
TPS M8 D6x2 4MOW59
AVIN_B
ADRS EL_A
MSE L2_A
VSEL_A
53 .6k
R18
MSE L1_A
14 .7k
R22
14.7k
R24
0
R21
22u F
C5
22u F
C4
6800pF
C6
22u F
C2
100uF
C1
22u F
C3
PVIN
PGND P GND
P VIN_A
P VIN_A
PGND
AGND_A
AVIN_A
PGND
22u F
C13
22u F
C12
6800pF
C14
22u F
C10
100 uF
C9
22u F
C11
PVIN
PGND P GND
P VIN_B
PGND
PGND
AGND_B
AVIN_B
P VIN_B
CLK
DATA
DATA
CLK
S MBALT
S MBALT
PGND
0.1uF
C41
P VIN_A
30 .1k
R2
PGND
12
34
56
J P3
EN_A
EN_A VOS NS _A
S W_A
VOUT
GO S NS_ A
10
R3
10
R1
1
2
3
J P2
AVIN_B
1
2
3
J P1
AVIN_A
AVIN_A
0R26VSHARE _A
VSHARE _A
ADRS EL_B
MSE L2_B
VSEL_B
53 .6k
R30
MSE L1_B
14.7k
R35
0
R32
TP6
VOUT
TP1 0
PGND
S W_B
VOS NS _B
VOUT
GO S NS_ B
BP1 V5_A
VDD5_A
EN_B
PGND
0.1uF
C43
P VIN_B
30 .1k
R6
1 2
3 4
5 6
J P4
EN_B
PGND
BP1 V5_B
VDD5_B
VSEL_A = 0.8V Output
0R19
TP1 5
SYNC
SYNC
0R20
BCX_C LK_A
BCX_C LK_B
BCX_DATA_A
BCX_DATA_B
P GD_A
P GD_B
0.022uFC44
0.022uFC45
VSHARE _B
BCX_C LK_B
BCX_DATA_B
10 .0k
R31
10 .0k
R25
VDD5_A
VDD5_B
1
2
J P5
VDD5_A
BP1 V5_A
BP1 V5_B
AGND_A
AGND_B
TP1 2
VSHARE _A
TP1 3
VSHARE _B
PGND
VDD5_A
1
2
J P6
VDD5_B
PGND
VDD5_B
TP11
PGoo d_ A
TP1 4
PGoo d_ B
AVIN
VOUT
VOS NS _B
TP2 0
CHB_ VoutB
TP1 9
CHA_VoutB
PGND
Bode_Input
1
2
S MB2
VOUT_B
TP1 7
Re mote Se nse Vo ut B (+)
TP2 1
Re mote Se nse Vo ut B (-)
TP1 8
VOUT_B
TP2 2
PGND
0.022uFC71
0.022uFC72
1
2
T5
VOUT
1
2
T6
PGND
TP2 7
PGND
PGND
100pF
C42
100pF
C23
1
2
T7
VOUT
1
2
T8
PGND
470 uF
C39
470 uF
C40
470 uF
C61
470 uF
C62
10µF
C25
10µF
C24
10µF
C47
10µF
C46
47u F
C38
47u F
C60
PVIN
11.0k
R4
11.0k
R8
1
2
T3
PGND
AVIN
GO S NS_ A
GO S NS_ B
BP1 V5_A
BP1 V5_B
NT1
Ne t-Tie
NT2
Ne t-Tie
NT4
Ne t-Tie
NT3
Ne t-Tie
49. 9
R9
49. 9
R12
49. 9
R10
49. 9
R13
10. 0
R7
10. 0
R14
49. 9
R37
49. 9
R39
49. 9
R38
49. 9
R40
10. 0
R36
10. 0
R41
10 .0k
R5
10 .0k
R11
CNTL
CNTL
68 .1k
R33
10 .0k
R27
10 .0k
R28
10 .0k
R17
10 .0k
R16
10 .0k
R15
10 .0k
R23
26 .1k
R29
26 .1k
R34
SW_A and SW_B have a via test point on the bottom of the PCB
TP3
PGND
Figure 3-1. TPSM8D6C24EVM-2PH Schematic
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4 Test Setup
4.1 Test and Configuration Software
To change any of the default configuration parameters on the EVM through PMBus, obtain the TI Fusion Digital
Power Designer software.
4.1.1 Description
The TI Fusion Digital Power Designer is the graphical user interface (GUI) used to configure and monitor the
Texas Instruments TPSM8D6C24 power converter installed on this evaluation module. The application uses the
PMBus protocol to communicate with the controller over serial bus by way of a TI USB adapter described in
Section 4.2.6.
4.1.2 Features
Some of the tasks the user can perform with the GUI include:
• Turn on or off the power supply output, either through the hardware control line or the PMBus operation
command.
• Monitor real-time data. Items such as input voltage, output voltage, output current, die temperature, and
warnings and faults that are continuously monitored and displayed by the GUI.
• Configure common operating characteristics such as the following:
– VOUT trim and margin
– UVLO
– Soft-start time
– Warning and fault thresholds
– Fault response
– On/Off modes
This software is available for download at http://www.ti.com/tool/fusion_digital_power_designer.
4.2 Test Equipment
4.2.1 Voltage Source
The input voltage source, VIN, must be a 0-V to 18-V variable DC source capable of supplying a minimum of 16
ADC to support 70-A load with 5-V input. Connect input VIN and GND to T1 (PVIN) and T2/T3 (PGND). If the
output voltage of the EVM is increased, the power supply may need to supply more current.
4.2.2 Oscilloscope
An oscilloscope is recommended for measuring output noise and ripple. Output ripple must be measured using a
tip-and-barrel method.
4.2.3 Multimeters
TI recommends using two separate multimeters: one meter to measure VIN and the other to measure VOUT.
4.2.4 Output Load
A variable electronic load is recommended for the test setup. To test the full load current this EVM supports, the
load should be capable of sinking at least 70 A.
4.2.5 Fan
During prolonged operation at high loads, it can be necessary to provide forced air cooling with a small fan
aimed at the EVM. Maintain the surface temperature of the devices on the EVM below their rated temperature.
4.2.6 USB-to-GPIO Interface Adapter
A communications adapter is required between the EVM and the host computer. This EVM is designed to use
TI's USB-to-GPIO Adapter. Purchase this adapter at http://www.ti.com/tool/usb-to-gpio.
4.2.7 Recommended Wire Gauge
• Input connection to the VIN and PGND terminal blocks (T1, T2, and T3) – The recommended wire size is
AWG #12, with the total length of wire less than two feet (1 foot input, 1 foot return).
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• Output load connection to the VOUT and PGND terminal blocks (T5, T6, T7, and T8) – The minimum
recommended wire size is AWG #10, with the total length of wire less than two feet (1 foot output, 1 foot
return). A thicker wire gauge can be required to minimize the voltage drop in the wires.
4.3 List of Test Points, Jumpers, and Connectors
Table 4-1 lists the test point functions.
Table 4-1. Test Point Functions
Test Point Name Description
TP1 PVIN PVIN test point
TP2, TP3,
TP4, TP10,
TP16,
TP22, TP27
PGND PGND test point
TP5 Remote Sense Vout (+) VOUT remote sense + voltage point
TP6 VOUT VOUT sensing test point
TP7 CHA_Vout Channel A for VOUT small signal loop gain measurements (B/A setup)
TP8 CHB_Vout Channel B for VOUT small signal loop gain measurements (B/A setup)
TP9 Remote Sense Vout (–) VOUT remote sense — voltage point
TP11 PGood_A PGOOD signal of VOUT
TP12 VSHARE_A VSHARE_A measurement point. Sensitive signal
TP13 VSHARE_B VSHARE_B measurement point. Sensitive signal
TP15 SYNC External clock input (SYNC IN) or output to synchronize other devices (SYNC OUT)
TP18 VOUT_B VOUT sensing test point
TP23 CNTL CNTL signal on J2 header
TP24 CLK CLK signal on J2 header
TP25 SMBALRT SMBALERT signal on J2 header
TP26 DATA DATA signal on J2 header
Table 4-2 lists the EVM jumpers.
Table 4-2. Jumpers
Jumper Name Description
JP1 AVIN_A AVIN_A input source selection
JP2 AVIN_B AVIN_B input source selection
JP3 EN_A EN_A pin selections
JP4 EN_B EN_B pin selections
JP5 VDD5_A External VDD5_A connection
JP6 VDD5_B External VDD5_B connection
JP7 USB to PVIN Short to connect PVIN to Micro USB connector.
JP8 PMBus to AVIN Short to connect USB-to-GPIO 3.3 V to AVIN.
Table 4-3 lists the options for the EN/UVLO pin selections on JP2 and JP4.
Table 4-3. JP3 and JP4 Selections
Shunt Position Selection
CNTL_INPUT PMBus adapter control signal
UVLO Resistor divider to PVIN
DISABLE EN/UVLO short to ground
Table 4-4 lists the options for the AVIN pin selections on JP1 and JP2.
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Table 4-4. JP1 and J2 Selections
Shunt Position Selection
AVIN AVIN pin connected to AVIN input through 10-Ω resistor. Use this selection when testing with a split rail input.
PVIN AVIN pin connected to PVIN through 10-Ω resistor
Table 4-5 lists the EVM connector functions.
Table 4-5. Connector Functions
Connector Name Description
J1 Micro-USB Power Micro USB connector to power EVM from a 5-V USB source
J2 PMBus PMBus socket for TI FUSION adapter
T1 PVIN VIN+ connector
T2, T3 PGND VIN– connector
T4 AVIN External AVIN connector
T5 VOUT VOUT+ connector
T6, T8 PGND VOUT– connector
4.4 Evaluating Split Rail Input
The default configuration of the EVM is for single rail input. Split rail input enables operation with 3.3-V PVIN. For
split rail operation, configure the jumpers on the EVM as follows:
1. Move the jumper JP1 and JP2 to AVIN position to disconnect the AVIN pin from the PVIN pins.
2. Apply the AVIN input to T4. 4-V or greater AVIN is required to bring the VDD5 voltage high enough to enable
conversion.
3. If operation with 3.3-V PVIN is needed and the CNTL jumpers (JP3 and JP4) are in UVLO position,
the resistor divider at the EN/UVLO will need to be changed. Alternately, move the CNTL jumpers to
CNTL_INPUT position and use the control signal to enable conversion or use the ON_OFF_CONFIG and
OPERATION commands to enable conversion.
5 EVM Configuration Using the Fusion GUI
The TPSM8D6C24 leaves the factory pre-configured. The factory default settings for the parameters can be
found in the data sheet. If configuring the EVM to settings other than the factory defaults, use the software
described in Section 4.1. It is necessary to have the input voltage applied to the EVM prior to launching the
software so that the TPSM8D6C24 can respond to the GUI and the GUI can recognize the device. The default
configuration for the EVM to stop converting is set by the EN/UVLO resistor divider to a nominal input voltage of
3.5 V, therefore, if it is necessary to avoid any converter activity during configuration, an input voltage less than
3.5 V should be applied. TI recommends an input voltage of 3.3 V.
5.1 Configuration Procedure
1. Adjust the input supply to provide 3.3 VDC, current limited to 1 A.
2. Apply the input voltage to the EVM. See Section 4.2 for connections and test setup.
3. Launch the Fusion GUI software. See the screen shots in Section 10 for more information.
4. Configure the EVM operating parameters as desired.
6 Test Procedure
6.1 Line and Load Regulation and Efficiency Measurement Procedure
1. Set up the EVM as Section 4.2 and Section 6.2 describe.
2. Set the electronic load to draw 0 ADC.
3. Increase VIN from 0 V to 12 V using voltage meter to measure input voltage.
4. Use the other voltage meter to measure output voltage VOUT.
5. Vary the load from 0 to 70 ADC. VOUT should remain in regulation as defined in Table 2-1.
6. Vary VIN from 5 V to 16 V. VOUT should remain in regulation as defined in Table 2-1.
7. Decrease the load to 0 A.
8. Decrease VIN to 0 V.
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6.2 Efficiency Measurement Test Points
To evaluate the efficiency of the power train (device and inductor), it is important to measure the voltages at
the correct location. This is necessary because otherwise the measurements will include losses that are not
related to the power train itself. Losses incurred by the voltage drop in the copper traces and in the input and
output connectors are not related to the efficiency of the power train, which should not be included in efficiency
measurements.
Input current can be measured at any point in the input wires, and output current can be measured anywhere in
the output wires of the output being measured.
Table 6-1 shows the measurement points for input voltage and output voltage. VIN and VOUT are measured
to calculate the efficiency. Using these measurement points will result in efficiency measurements that excluded
losses due to the wires and connectors.
Table 6-1. Test Points for Efficiency Measurements
Test Point Node Name Description Comment
TP1 PVIN Input voltage measurement point
for VIN+ The pair of test points are connected to the PVIN/PGND pins of U1. The voltage drop between
input terminal to the device pins is included for efficiency measurement.
TP3 PGND Input voltage measurement point
for VIN– (GND)
TP6 VOUT Output voltage measurement
point for VOUT+ The pair of test points are connected near the output terminals. The voltage drop from the
output point of the inductor to the output terminals is included for efficiency measurement.
TP10 PGND Output voltage measurement
point for VOUT– (GND)
6.3 Control Loop Gain and Phase Measurement Procedure
The TPSM8D6C24EVM-2PH includes a 49.9-Ω series resistor in the feedback loop for VOUT. The resistor is
accessible at the test points TP7 and TP8 for loop response analysis. These test points should be used during
loop response measurements as the perturbation injecting points for the loop. See the description in Table 6-2.
Table 6-2. List of Test Points for Loop Response Measurements
Test Point Node Name Description Comment
TP7 CHA_Vout Input to feedback divider of VOUT The amplitude of the perturbation at this node should be limited to less than 30 mV
TP8 CHB_Vout Resulting output of VOUT Bode can be measured by a network analyzer with a CH_B/CH_A configuration
Measure the loop response with the following procedure:
1. Set up the EVM as described in Section 4.2.
2. Connect the isolation transformer of the network analyzer from TP7 to TP8.
3. Connect the input signal measurement probe to TP7. Connect the output signal measurement probe to TP8.
4. Connect the ground leads of both probe channels to TP3.
5. On the network analyzer, measure the Bode as TP8/TP7 (Out/In).
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7 Performance Data and Typical Characteristic Curves
Figure 7-1 through Figure 7-10 present typical performance curves for the TPSM8D6C24EVM-2PH. The input
voltage is 12 V and the oscilloscope measurements use 200MHz bandwidth limiting, unless otherwise noted.
7.1 Efficiency
Output Current (A)
Efficiency (%)
0 5 10 15 20 25 30 35 40 45 50 55 60 65 70
0
10
20
30
40
50
60
70
80
90
100
PVIN = 5 V
PVIN = 12 V
PVIN = 16 V
Figure 7-1. Efficiency
7.2 Load Regulation
Output Current (A)
Output Voltage (V)
0 5 10 15 20 25 30 35 40 45 50 55 60 65 70
0.792
0.794
0.796
0.798
0.8
0.802
0.804
0.806
0.808
PVIN = 5 V
PVIN = 12 V
PVIN = 16 V
Figure 7-2. Load Regulation
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7.3 Line Regulation
Input Voltage (V)
Output Voltage (V)
5 6 7 8 9 10 11 12 13 14 15 16
0.799
0.7995
0.8
0.8005
0.801
0.8015
0.802
0.8025
0.803
0.8035
0.804
0.8045
0.805
IOUT = 0 A
IOUT = 35 A
IOUT = 70 A
Figure 7-3. Line Regulation
7.4 Transient Response
Figure 7-4 shows the transient response waveform with a 15-A to 30-A transient at 1 A/µs
Figure 7-4. Transient Response
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7.5 Control Loop Bode Plot
Frequency (Hz)
Gain (dB)
Phase ()
1000 2000 5000 10000 100000 1000000
-60 -180
-40 -120
-20 -60
0 0
20 60
40 120
60 180
Gain (dB)
Phase ()
Figure 7-5. Bode Plot, 70-A Load
7.6 Output Ripple
Figure 7-6 and Figure 7-7 show the output ripple waveforms at 0-A and 70-A load.
Figure 7-6. Output Ripple, No Load
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Figure 7-7. Output Ripple, 70-A Load
7.7 Control On
Figure 7-8 illustrates the start-up from control on waveforms at 70-A outputs.
Figure 7-8. Start-Up From Control, 70-A CC Load
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7.8 Control Off
Figure 7-9 illustrates the control off waveforms at 70-A outputs.
Figure 7-9. Shutdown From Control, 70-A CC Load
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7.9 Thermal Image
Figure 7-10 shows the TPSM8D6C24EVM-2PH thermal image.
VIN = 12 V, IOUT = 70 A, Airflow = 200 LFM, 10 minute soak
Figure 7-10. Thermal Image
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8 EVM Assembly Drawing and PCB Layout
through show the design of the TPSM8D6C24EVM-2PH printed circuit board.
Figure 8-1. TPSM8D6C24EVM-2PH Top Side
Component View (Top View)
Figure 8-2. TPSM8D6C24EVM-2PH Bottom Side
Component View (Bottom View)
Figure 8-3. TPSM8D6C24EVM-2PH Top Copper
(Top View)
Figure 8-4. TPSM8D6C24EVM-2PH Internal Layer 1
(Top View)
EVM Assembly Drawing and PCB Layout www.ti.com
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Figure 8-5. TPSM8D6C24EVM-2PH Internal Layer 2
(Top View)
Figure 8-6. TPSM8D6C24EVM-2PH Internal Layer 3
(Top View)
Figure 8-7. TPSM8D6C24EVM-2PH Internal Layer 4
(Top View)
Figure 8-8. TPSM8D6C24EVM-2PH Internal Layer 5
(Top View)
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Figure 8-9. TPSM8D6C24EVM-2PH Internal Layer 6
(Top View)
Figure 8-10. TPSM8D6C24EVM-2PH Internal
Bottom Layer (Top View)
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9 Bill of Materials
Table 9-1 lists the BOM for the TPSM8D6C24EVM-2PH.
Table 9-1. TPSM8D624EVM-2PH Bill of Materials
Designator Quantity Value Description PackageReference PartNumber Manufacturer Alternate
PartNumber
Alternate
Manufacturer
!PCB1 1 Printed Circuit Board BSR193 Any
C1, C7, C8, C9 4 100 μF CAP, AL, 100 μF, 35 V, ±20%,
0.15 Ω, SMD
SMT Radial G EEE-FC1V101P Panasonic
C2, C3, C4, C5,
C10, C11, C12,
C13
8 22 μF CAP, CERM, 22 μF, 25 V,
Ω10%, X6S, 1210
1210 GRM32EC81E226KE15L MuRata
C6, C14 2 6800 pF CAP, CERM, 6800 pF, 50 V,
±10%, X7R, 0402
402 GRM155R71H682KA88D MuRata
C15, C16, C20,
C21, C26, C27,
C28, C29, C30,
C34, C35, C37,
C38, C48, C49,
C50, C51, C52,
C56, C57, C59,
C60, C64, C65,
C69, C70
26 47 μF CAP, CERM, 47 μF, 10 V,
±10%, X7R, 1210
1210 GRM32ER71A476KE15L MuRata
C23 1 100 pF CAP, CERM, 100 pF, 50 V,
±10%, X7R, 0402
402 8.85012E+11 Wurth Elektronik
C24, C25, C46,
C47
4 10 μF CAP, CERM, 10 μF, 10 V,
±20%, X7R, 0603
603 GRM188Z71A106MA73D MuRata
C39, C40, C61,
C62
4 470 μF CAP, Tantalum Polymer, 470
μF, 6.3 V, ±20%, 0.01 Ω,
7343-40 SMD
7343-40 6TPF470MAH Panasonic
C41, C43 2 0.1 μF CAP, CERM, 0.1 μF, 50 V,
±10%, X7R, 0603
603 C0603C104K5RACTU Kemet
D1, D2 2 30 V Diode, Schottky, 30 V, 2 A,
AEC-Q101, SOD-123FL
SOD-123FL MBR230LSFT1G ON Semiconductor
H3, H4, H5, H6 4 Bumpon, Hemisphere, 0.44 ×
0.20, Clear
Transparent Bumpon SJ-5303 (CLEAR) 3M
J1 1 Connector, Receptacle, Micro-
USB Type B, R/A, Bottom
Mount SMT
MICRO USB CONN, R/A 1981568-1 TE Connectivity
J2 1 Header (shrouded), 100 mil, 5
× 2, Gold, TH
5 × 2 Shrouded header 5103308-1 TE Connectivity
JP1, JP2 2 Header, 100mil, 3 × 1, Gold,
TH
PBC03SAAN PBC03SAAN Sullins Connector
Solutions
JP3, JP4 2 Header, 100 mil, 3 × 2, Gold,
TH
Sullins 100 mil, 2 × 3, 230 mil
above insulator
PBC03DAAN Sullins Connector
Solutions
JP5, JP6 2 Header, 2.54 mm, 2 × 1, Gold,
TH
Header, 2.54 mm, 2 × 1, TH 61300211121 Wurth Elektronik
JP7, JP8 2 Header, 100 mil, 2 × 1, Tin, TH Header, 2 × 1, 100 mil, TH 5-146278-2 TE Connectivity
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Table 9-1. TPSM8D624EVM-2PH Bill of Materials (continued)
Designator Quantity Value Description PackageReference PartNumber Manufacturer Alternate
PartNumber
Alternate
Manufacturer
LBL1 1 Thermal Transfer Printable
Labels, 0.650" W × 0.200" H -
10,000 per roll
PCB Label 0.650 × 0.200 inch THT-14-423-10 Brady
LED1 1 Green LED, Green, SMD LED_0603 150060GS75000 Wurth Elektronik
R1, R3 2 10 RES, 10, 5%, 0.1 W, AEC-
Q200 Grade 0, 0603
603 CRCW060310R0JNEA Vishay-Dale
R2, R6 2 30.1 k RES, 30.1 k, 1%, 0.1 W, 0603 603 RC0603FR-0730K1L Yageo
R4, R8 2 11.0 k RES, 11.0 k, 1%, 0.1 W, 0603 603 RC0603FR-0711KL Yageo
R7, R14 2 10 RES, 10.0, 1%, 0.063 W, 0402 402 CRCW040210R0FKED Vishay-Dale
R9, R10, R12,
R13
4 49.9 RES, 49.9, 1%, 0.1 W, AEC-
Q200 Grade 0, 0402
402 ERJ-2RKF49R9X Panasonic
R11 1 10.0 k RES, 10.0 k, 1%, 0.1 W, 0402 402 ERJ-2RKF1002X Panasonic
R19, R20, R26,
R32
4 0 RES, 0, 5%, 0.1 W, AEC-Q200
Grade 0, 0603
603 ERJ-3GEY0R00V Panasonic
R22 1 14.7 k RES, 14.7 k, 1%, 0.1 W, AEC-
Q200 Grade 0, 0603
603 ERJ-3EKF1472V Panasonic
R23 1 10.0 k RES, 10.0 k, 1%, 0.1 W, 0603 603 RCG060310K0FKEA Vishay Draloric
R24 1 14.7 k RES, 14.7 k, 1%, 0.1 W, 0603 603 RC0603FR-0714K7L Yageo
R25 1 10.0 k RES, 10.0 k, 1%, 0.1 W, 0603 603 RC0603FR-0710KL Yageo
R42 1 1.00 k RES, 1.00 k, 1%, 0.1 W, AEC-
Q200 Grade 0, 0603
603 CRCW06031K00FKEA Vishay-Dale
SH-JP1, SH-
JP2, SH-JP3,
SH-JP4
4 1 × 2 Shunt, 100 mil, Gold plated,
Black
Shunt SNT-100-BK-G Samtec 969102-0000-DA 3M
SMB1 1 Connector, Receptacle, 50 Ω,
TH
SMB Connector SMBR004D00 JAE Electronics
T1, T2, T3, T5,
T6, T7, T8
7 Therminal Block, 5 mm, 2-pole,
Tin, TH
TH, 2-Leads, Body 10 × 10 mm,
Pitch 5 mm
282856-2 TE Connectivity
T4 1 Terminal Block, 3.5-mm Pitch,
2 × 1, TH
7.0 × 8.2 × 6.5 mm ED555/2DS On-Shore Technology
TP1, TP6, TP18 3 Test Point, Multipurpose, Red,
TH
Red Multipurpose Testpoint 5010 Keystone
TP2, TP3, TP4,
TP10, TP16,
TP22, TP27
7 Test Point, Multipurpose,
Black, TH
Black Multipurpose Testpoint 5011 Keystone
TP5, TP7, TP8,
TP9, TP11,
TP12, TP13,
TP15, TP23,
TP24, TP25,
TP26
12 Test Point, Multipurpose,
White, TH
White Multipurpose Testpoint 5012 Keystone
U1 1 TPSM8D6x24MOW59 MODULE_MOW0059A TPSM8D6x24MOW59 Texas Instruments Texas Instruments
Bill of Materials www.ti.com
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