Texas Instruments ADS8383EVM User manual

ADS8383EVM
December 2003 Data Acquistion
User’s Guide
SLAU119

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Copyright 2003, Texas Instruments Incorporated

EVM IMPORTANT NOTICE
Texas Instruments (TI) provides the enclosed product(s) under the following conditions:
This evaluation kit being sold by TI is intended for use for ENGINEERING DEVELOPMENT OR EVALUATION
PURPOSES ONLY and is not considered by TI to be fit for commercial use. As such, the goods being provided
may not be complete in terms of required design-, marketing-, and/or manufacturing-related protective
considerations, including product safety measures typically found in the end product incorporating the goods.
As a prototype, this product does not fall within the scope of the European Union directive on electromagnetic
compatibility and therefore may not meet the technical requirements of the directive.
Should this evaluation kit not meet the specifications indicated in the EVM User’s Guide, the kit may be returned
within 30 days from the date of delivery for a full refund. THE FOREGOING WARRANTY IS THE EXCLUSIVE
WARRANTY MADE BY SELLER TO BUYER AND IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED,
IMPLIED, OR STATUTORY, INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY
PARTICULAR PURPOSE.
The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user
indemnifies TI from all claims arising from the handling or use of the goods. Please be aware that the products
received may not be regulatory compliant or agency certified (FCC, UL, CE, etc.). Due to the open construction
of the product, it is the user’s responsibility to take any and all appropriate precautions with regard to electrostatic
discharge.
EXCEPT TO THE EXTENT OF THE INDEMNITY SET FORTH ABOVE, NEITHER PARTY SHALL BE LIABLE
TO THE OTHER FOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES.
TI currently deals with a variety of customers for products, and therefore our arrangement with the user is not
exclusive.
TI assumes no liability for applications assistance, customer product design, software performance, or
infringement of patents or services described herein.
Please read the EVM User’s Guide and, specifically, the EVM Warnings and Restrictions notice in the EVM
User’s Guide prior to handling the product. This notice contains important safety information about temperatures
and voltages. For further safety concerns, please contact the TI application engineer.
Persons handling the product must have electronics training and observe good laboratory practice standards.
No license is granted under any patent right or other intellectual property right of TI covering or relating to any
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Mailing Address:
Texas Instruments
Post Office Box 655303
Dallas, Texas 75265
Copyright 2003, Texas Instruments Incorporated

EVM WARNINGS AND RESTRICTIONS
It is important to operate this EVM within the input voltage range of ±6 V and the output voltage
range of 0 V and 5.5 V.
Exceeding the specified input range may cause unexpected operation and/or irreversible
damage to the EVM. If there are questions concerning the input range, please contact a TI
field representative prior to connecting the input power.
Applying loads outside of the specified output range may result in unintended operation and/or
possible permanent damage to the EVM. Please consult the EVM User’s Guide prior to
connecting any load to the EVM output. If there is uncertainty as to the load specification,
please contact a TI field representative.
During normal operation, some circuit components may have case temperatures greater than
60°C. The EVM is designed to operate properly with certain components above 60°C as long
as the input and output ranges are maintained. These components include but are not limited
to linear regulators, switching transistors, pass transistors, and current sense resistors. These
types of devices can be identified using the EVM schematic located in the EVM User’s Guide.
When placing measurement probes near these devices during operation, please be aware
that these devices may be very warm to the touch.
Mailing Address:
Texas Instruments
Post Office Box 655303
Dallas, Texas 75265
Copyright 2003, Texas Instruments Incorporated

Related Documentation From Texas Instruments
iii
Preface

About This Manual
This users guide describes the characteristics, operation, and use of the
ADS8383 18-bit, 500 kHz parallel interface analog to digital converter
evaluation board. A complete circuit description as well as schematic diagram
and bill of materials is included.
How to Use This Manual
This document contains the following chapters:
-Chapter 1 – EVM Overview
-Chapter 2 – Analog Interface
-Chapter 3 – Digital Interface
-Chapter 4 – Power Supply Requirements
-Chapter 5 – Using the EVM
-Chapter 6 − ADS8383EVM BOM, Layout and Schematic
Related Documentation From Texas Instruments
To obtain a copy of any of the following TI documents, call the Texas
Instruments Literature Response Center at (800) 477−8924 or the Product
Information Center (PIC) at (972) 644−5580. When ordering, identify this
booklet by its title and literature number. Updated documents can also be
obtained through our website at www.ti.com
Data Sheets: Literature Number:
ADS8383 SLAS005
REF3040 SBVS032
REF3020 SBVS032
SN74AHC138 SCLS258
SN74AHC245 SCLS230
SN74AHC1G04 SCLS318
THS4031 SLOS224

Contents
iv
FCC Warning
This equipment is intended for use in a laboratory test environment only. It gen-
erates, uses, and can radiate radio frequency energy and has not been tested
for compliance with the limits of computing devices pursuant to subpart J of
part 15 of FCC rules, which are designed to provide reasonable protection
against radio frequency interference. Operation of this equipment in other en-
vironments may cause interference with radio communications, in which case
the user at his own expense will be required to take whatever measures may
be required to correct this interference.

Contents
v

1 EVM Overview 1-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1 Features 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 Analog Interface 2-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1 Signal Conditioning 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2 Reference 2-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 Digital Interface 3-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4 Power Supply Requirements 4-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5 Using the EVM 5-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1 As a Reference Board 5-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2 As a Prototype Board 5-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3 As a Software Test Platform 5-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6 ADS8383EVM BOM, Layout, and Schematic 6-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.1 ADS8383EVM Bill of Materials 6-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.2 ADS8383EVM Layout 6-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3 ADS8383EVM Schematic 6-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Contents
vi

2−1 Input Buffer Circuit 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−1 Top Layer—Layer 1 6-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−2 Ground Plane—Layer 2 6-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−3 Power Plane— Layer 3 6-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−4 Bottom Layer—Layer 4 6-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−1 Analog Input Connector 2-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−2 Sholder Short Jumper Setting 2-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−1 Pinout for Parallel Control Connector P2 3-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−2 Jumper Settings 3-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−3 Data Bus Connector P3 3-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−4 Pinout for Converter Control Connector J4 3-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−1 Power Supply Test Points 4-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−2 Power Connector, J1, Pin Out 4-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−1 ADS8383EVM Bill Of Materials 6-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-1
EVM Overview
 
This chapter contains the features of the ADS8383EVM.
Topic Page
1.1 Features 1-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 1

Features
1-2
1.1 Features
-Full-featured evaluation board for the high-speed ADS8383 18-bit, single
channel, parallel interface SAR type analog to digital converters.
-Onboard signal conditioning
-Onboard reference
-Input and output digital buffer
-Onboard decoding for stacking multiple EVMs

2-1
Analog Interface
 
The ADS8383 analog-to-digital converter has both a positive and negative
analog input pin. The EVM provides ground for the negative input close the de-
vice via SJP3, or allows a user-furnished ground wire. The negative input pin
has a range of –200 mV up to 200 mV, and is shorted on the EVM via SJP3.
A signal for the positive input pin can be applied at connector P1, pin 2 (shown
in Table 2−1 ), or applied to the center pin of SMA connector J2.
Table 2−1.Analog Input Connector
Description Signal Name Connector.Pin# Signal Name Description
Pin tied to Ground AGND P1.1 P1.2 + Noninverting Input Channel
Reserved N/A P1.3 P1.4 N/A Reserved
Reserved N/A P1.5 P1.6 N/A Reserved
Reserved N/A P1.7 P1.8 N/A Reserved
Pin tied to Ground AGND P1.9 P.10 N/A Reserved
Pin tied to Ground AGND P1.11 P1.12 N/A Reserved
Reserved N/A P1.13 P1.14 N/A Reserved
Pin tied to Ground AGND P1.15 P1.16 N/A Reserved
Pin tied to Ground AGND P1.17 P1.18 N/A Reserved
Reserved N/A P1.19 P1.20 REF+ External Reference Input
Topic Page
2.1 Signal Conditioning 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2 Reference 2-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 2

Signal Conditioning
2-2
2.1 Signal Conditioning
The factory recommends the analog input to any SAR type converter be
buffered and low-pass filtered. It is important to note that the input buffer circuit
of the ADS8383EVM, shown in Figure 2−1, utilizes the THS4031 configured
as an inverting gain of one. The amplifier is not stable in a conventional a
gain-of-one configuration. The THS4031 was selected for it’s low noise, high
slew rate and fast settling time. The low pass filter resistor and capacitor values
were selected such that ADS8383EVM would meet the 100 kHz AC
performance specifications listed in the data sheet. The series resistor works
in conjunction with the capacitor to filter the input signal, but also isolates the
amplifier from the 6800 pF capacitive load. The capacitor to ground at the input
of the A/D works in conjunction with the series resistor to filter the input signal,
and acts like a charge reservoir. This external filter capacitor works with the
amplifier to charge the internal sampling capacitor during sampling mode.
The EVM has a provision to offset the input voltage by adjusting R23, a 10-kΩ
potentiometer.
Figure 2−1.Input Buffer Circuit
1 kΩ
1 kΩ
−VCC
VI0.1 µF
1 µF
10 Ω(+) IN
(−) IN
6800 pF
1 µF
0.1 µF
0.22 µF
500 Ω
4.096 V
10 kΩ
+VCC
THS4031
−
+

Reference
2-3
Analog Interface
2.2 Reference
The ADS8383EVM provide an onboard 4.096-V reference circuit. The EVM
also has the provision for users to supply a reference voltage via connecter P1
pin 20. This reference voltage may be filtered by installing amplifier U1. The
converter itself has onboard reference buffer, therefore it is not necessary to
buffer externally. The reference buffer circuit on the EVM is not populated with
an amplifier. The EVM allows users to select from two reference sources. Set
SJP1 and SJP2 to select onboard reference voltage (REF3040) or a
user-supplied reference voltage via P1 pin 20. See Table 2−2 for jumper
settings. See Chapter 6 for the full schematic.
Table 2−2.Solder Short Jumper Setting
Reference
Description
Jumper Setting
Reference
Designator
Description
1−2 2−3
SJP1 Select REF3040 output for reference voltage Installed†Not installed
Select buffered reference voltage Not installed Installed
SJP2 Select U3, REF3040, as 4.096V reference Installed†
Buffer User supplied reference voltage Not Installed Installed
SJP3 Short (−)IN pin to ground Installed†N/A
SJP4 Apply offset voltage to A/D buffer Not Installed N/A
SJP5 Set amplifier U1 negative supply to ground Installed
SJP5
Set amplifier U1 negative supply to −VCC Not Installed Installed†
SJP6 Set amplifier U2 negative supply to ground Installed Not Installed
SJP6
Set amplifier U2 negative supply to −VCC Not Installed Installed†
†Factory set condition

2-4

3-1
Digital Interface
 
The ADS8383EVM is designed for easy interfacing to multiple platforms.
Samtec part numbers SSW−110−22−F−D−VS−K and TSM−110−01−T−DV−P
provide a convenient dual row header/socket combination at P2 and P3.
Consult Samtec at www.samtec.com or 1−800−SAMTEC−9 for a variety of
mating connector options.
Table 3−1.Pinout for Parallel Control Connector P2
Connector.Pin Signal Description
P2.1 DC_CS Daughter card Board Select pin
P2.3
P2.5
P2.7 A0 Address line from processor
P2.9 A1 Address line from processor
P2.11 A2 Address line from processor
P2.13
P2.15
P2.17
P2.19 INTc Set jumper W3 to select BUSY or inverted signal
to be applied to this pin.
Note: All even numbered pins of P2 are tied to DGND.
Read (RD) and conversion start (CONVST) signals to the converter can be
assigned to two different addresses in memory via jumper settings. This allows
for the stacking of up to two ADS8383EVMs into processor memory. See
Table 3−2 for jumper settings. Note, the evaluation module does not allow chip
select (CS) line of the converter to be assigned to different memory locations.
It is therefore suggested the CS line be grounded or wired to an appropriate
signal of the processor.
Chapter 3

3-2
Table 3−2.Jumper Settings
Reference Designator
Description
Jumper Settings
Reference Designator
Description
1−2 2−3
W1
Set A[2..0] = 0x1 to generate RD pulse Installed†Not installed
W1
Set A[2..0] = 0x2 to generate RD pulse Not installed Installed
W2
Set A[2..0] = 0x3 to generate CONVST pulse Installed†Not installed
W2
Set A[2..0] = 0x4 to generate CONVST pulse Not installed Installed
W3
Apply BUSY to P3 pin 19 Not installed Installed†
W3
Apply inverted BUSY to P3 pin 19 Installed†Not installed
†Factory set condition The data bus is available at connector P3, see Table 3−3 for pin out
information.
Table 3−3.Data Bus Connector P3
Connector.Pin Signal Description
P3.1 D0 Buffered Data Bit 0 (LSB)
P3.3 D1 Buffered Data Bit 1
P3.5 D2 Buffered Data Bit 2
P3.7 D3 Buffered Data Bit 3
P3.9 D4 Buffered Data Bit 4
P3.11 D5 Buffered Data Bit 5
P3.13 D6 Buffered Data Bit 6
P3.15 D7 Buffered Data Bit 7
P3.17 D8 Buffered Data Bit 8
P3.19 D9 Buffered Data Bit 9
P3.21 D10 Buffered Data Bit 10
P3.23 D11 Buffered Data Bit 11
P3.25 D12 Buffered Data Bit 12
P3.27 D13 Buffered Data Bit 13
P3.29 D14 Buffered Data Bit 14
P3.31 D15 Buffered Data Bit 15
P3.33 D16 Buffered Data Bit 16
P3.35 D17 Buffered Data Bit 17 (MSB)
Note: All even numbered pins of P3 are tied to DGND.
This evaluation module provides direct access to all the analog-to-digital
converter control signals via connector J4, see Table 3−4.
Table 3−4.Pinout for Converter Control Connector J4
Connector.Pin Signal Description
J4.1 CS Chip Select pin. Active low
J4.3 RD Read pin. Active low
J4.5 CONVST Convert start pin. Active low
J4.7 BYTE Byte select input. Used for 8-bit bus reading.
J4.9 BUS 18/16 Bus size select input. Used for selecting 18-bit or 16-bit wide bus transfer.
J4.11 BUSY Converter Status Output. High when a conversion is in progress.
Note: All even numbered pins of P4 are tied to DGND.

4-1
Power Supply Requirements
 !""# $%
The EVM accepts four power supplies.
-A dual ±Vs DC supply for the dual supply op−amps. Recommend ±6VDC
supply.
-A single +5.0 V DC supply for analog section of the board (A/D + Refer-
ence).
-A single +5.0 V or +3.3 VDC supply for digital section of the board (A/D +
address decoder + buffers).
There are two ways to provide these voltages.
1) Wire in the voltages at test points on the EVM. See Table 4−1.
Table 4−1.Power Supply Test Points
Test Point Signal Description
TP16 +BVDD Apply +3.3 V or +5.0 V. See ADC datasheet for full range.
TP20 +AVCC Apply +5.0 V.
TP14 +VA Apply +6.0 V. Positive supply for amplifier.
TP18 −VA Apply –6.0 V. Negative supply for amplifier.
2) Use the power connector J1, and derive the voltages elsewhere. The
pinout for this connector is shown below. If using this connector, set W4
jumper to connect +3.3 V or +5 V from connector to +BVDD. Short
between pins 1−2 to select +5 VD, or short between pins 2−3 to select
+3.3 VD as the source for the digital buffer voltage supply (+BVDD).
Table 4−2.Power Connector, J1, Pin Out
Signal Power Connector − J1 Signal
+VA(+6V) 1 2 –VA (–6V)
+5VA 3 4 N/C
DGND 5 6 AGND
N/C 7 8 N/C
+3.3VD 9 10 +5VD
Chapter 4

4-2

5-1
Using the EVM
&  
The ADS8383EVM serves three functions
1) As a reference design
2) As a prototype board and
3) As software test platform
Topic Page
5.1 As a Reference Board 5-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2 As a Prototype Board 5-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3 As a Software Test Platform 5-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 5

As a Reference Board
5-2
5.1 As a Reference Board
As a reference design, the ADS8383EVM contains the essential circuitry to
showcase the analog-to-digital converter. This essential circuitry includes the
input amplifier, reference circuit, and buffers. The EVM analog input circuit is
optimized for 100 kHz sine wave, therefore users may need to adjust the
resistor and capacitor values of the A/D input RC circuit. In AC type
applications where signal distortion is a concern, polypropylene capacitors
should be used in the signal path.
5.2 As a Prototype Board
As a prototype board, the buffer circuit consists of footprint is a standard 8-pin
SOIC and resistor pads for inverting and noninverting configurations. The
ADS8383EVM can be used to evaluate both dual and single supply amplifiers.
The EVM comes installed with a dual supply amplifier as it allows the user to
take advantage of the full input voltage range of the converter. For applications
that require signal supply operation and smaller input voltage range, the
THS4031 can be replaced with the single supply amplifier like OPA300. Pad
jumper SJP6 should be shorted between pads 1 and 2, as it shorts the minus
supply pin of the amplifier to ground. Positive supply voltage can be applied
via test point TP14 or connector J1 pin 1.
5.3 As a Software Test Platform
As a software test platform, connectors P1, P2, P3 plug into the parallel
interface connectors of the 5−6K interface card. The 5−6K interface card sits
on the C5000 and C6000 Digital Signal Processor starter kit (DSK). The
ADS8383EVM is then mapped into the processor’s memory space. This card
also provides an area for signal conditioning. This area can be used to install
application circuit(s) for digitization by the ADS8383 analog-to-digital
converter. Refer to the 5−6K interface card user’s guide (SLAU104) for more
information.
For the software engineer the ADS8383EVM provides a simple platform for
interfacing to the converter. The EVM provides standard 0.1” headers and
sockets to wire into prototype boards. The user need only provide in 3 address
lines (A2, A1, A0) and address valid line(DC_CS) to connector P2. To choose
which address combinations will generate RD and CONVST set jumpers as
shown in Table 3−2. Recall chip select (CS) signal is not memory mapped or
tied to P2, therefore it must be controlled via general purpose pin or shorted
to ground at J3 pin 1. If address decoding is not required, the EVM provides
direct access to converter data bus via P3 and control via J3.