Texas Instruments ADS8686SEVM-PDK User manual

1
SBAU319–November 2019
Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated
ADS8686SEVM-PDK Evaluation Module
User's Guide
SBAU319–November 2019
ADS8686SEVM-PDK Evaluation Module
This user's guide describes the characteristics, operation, and use of the ADS8686S evaluation module
(EVM) performance demonstration kit (PDK). The ADS8686S is a 16-channel, integrated front-end data
acquisition (DAQ) system based on a dual, simultaneous-sampling, 16-bit successive approximation
(SAR) analog-to-digital converter (ADC). Each input channel on the device supports true bipolar input
ranges of ±10 V, ±5 V, or ±2.5 V with single-supply operation. The device includes an analog front-end
offering a 1-MΩ, constant resistive input impedance. The ADS8686SEVM supports all the mentioned
features and provides provisions for an external reference, user-selectable oversampling ratio, and
features 16 input channels. The EVM-PDK eases the evaluation of the ADS8686S device and any devices
derived from the ADS8686X family with hardware, software, and computer connectivity through the
universal serial bus (USB) interface. This user's guide includes complete circuit descriptions, schematic
diagrams, and a bill of materials using the ADS8686S device as an example throughout the document.
Throughout this document, the terms EVM-PDK and ADS8686SEVM are synonymous with the
ADS8686SEVM-PDK.
The following related documents are available through the Texas Instruments web site at www.ti.com.
Related Documentation
Device Literature Number
ADS8686S SBAS905
REF5025 SBOS410
TPS7A4700 SBVS204
OPA192 SBOS620
INA149 SBOS579

www.ti.com
2SBAU319–November 2019
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
ADS8686SEVM-PDK Evaluation Module
Contents
1 Overview...................................................................................................................... 4
1.1 ADS8686SEVM-PDK Features ................................................................................... 4
1.2 ADS8686SEVM Features.......................................................................................... 4
2 EVM Analog Interface....................................................................................................... 5
2.1 ADS8686S Internal Reference and EVM Onboard Reference ............................................... 7
3 Digital Interfaces ............................................................................................................. 7
3.1 ADS8686S Digital Interface ....................................................................................... 7
4 Power Supplies .............................................................................................................. 8
4.1 Device Power Supplies ............................................................................................ 8
4.2 High-Voltage Power Supplies..................................................................................... 9
5 Initial Setup.................................................................................................................. 10
5.1 Default Jumper Settings.......................................................................................... 10
5.2 EVM Graphical User Interface (GUI) Software Installation .................................................. 11
6 Operation.................................................................................................................... 14
6.1 EVM GUI Global Settings for ADC Control .................................................................... 16
6.2 Register Map Configurations .................................................................................... 17
6.3 Device Configuration ............................................................................................. 17
6.4 Time Domain Display Tool....................................................................................... 20
6.5 Spectral Analysis Tool............................................................................................ 21
6.6 Histogram Analysis Tool.......................................................................................... 22
6.7 Linearity Analysis Tool............................................................................................ 23
7 Bill of Materials, PCB Layout, and Schematics......................................................................... 24
7.1 Bill of Materials .................................................................................................... 24
7.2 PCB Layout ........................................................................................................ 27
7.3 Schematics......................................................................................................... 29
List of Figures
1 ADS8686SEVM Analog Input Connections for Channels.............................................................. 5
2 REF5025 2.5-V External Reference Source ............................................................................. 7
3 High-Voltage Power Supply for Amplifiers ............................................................................... 9
4 ADS8686SEVM Default Jumper Settings .............................................................................. 10
5 Software Installation Prompts ............................................................................................ 11
6 ADS8686S Device Driver Installation Wizard Prompts................................................................ 12
7 LabVIEW Run-Time Engine Installation................................................................................. 12
8 Software Installation Complete Prompts ................................................................................ 13
9 ADS8686S EVM Folder Post-Installation ............................................................................... 13
10 ADS8686SEVM-PDK Hardware Setup and LED Indicators.......................................................... 14
11 Launch the ADS8686SEVM GUI Software ............................................................................. 15
12 EVM GUI Global Input Parameters ...................................................................................... 16
13 Register Map Configuration Display..................................................................................... 17
14 Device Configuration in Software Mode................................................................................. 18
15 Device Configuration Display in Hardware Mode...................................................................... 19
16 Time Domain Display...................................................................................................... 20
17 Spectral Analysis Tool..................................................................................................... 21
18 Histogram Analysis Tool .................................................................................................. 22
19 Linearity Analysis Tool..................................................................................................... 23
20 ADS8686S EVM PCB: Top Overlay..................................................................................... 27
21 ADS8686S EVM PCB Layer 1: Top Layer.............................................................................. 27
22 ADS8686S EVM PCB Layer 2: GND Plane ............................................................................ 27
23 ADS8686S EVM PCB Layer 3: Power Planes ......................................................................... 27

www.ti.com
3
SBAU319–November 2019
Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated
ADS8686SEVM-PDK Evaluation Module
24 ADS8686S EVM PCB Layer 4: Bottom Layer.......................................................................... 27
25 ADS8686S EVM PCB: Bottom Overlay................................................................................. 27
26 ADS8686SEVM-PDK Schematic......................................................................................... 29
27 ADS8686SEVM-PDK Schematic......................................................................................... 30
28 ADS8686SEVM-PDK Schematic......................................................................................... 31
29 ADS8686SEVM-PDK Schematic......................................................................................... 32
30 ADS8686SEVM-PDK Schematic......................................................................................... 33
31 ADS8686SEVM-PDK Schematic......................................................................................... 34
List of Tables
1 Terminal Block Analog Interface Connections........................................................................... 6
2 SMA Analog Interface ADC-A Connections.............................................................................. 6
3 SMA Analog Interface ADC-B Connections.............................................................................. 6
4 Digital I/O Connections for Connector J17 ............................................................................... 7
5 Default Jumper Configuration ............................................................................................ 10
6 External Source Requirements for Evaluation of the ADS8686S.................................................... 21
7 External Source Requirements for ADS8686S Evaluation ........................................................... 23
8 ADS8686S EVM Bill of Materials ........................................................................................ 24
Trademarks
Windows 7, Windows 8, Windows 10 are registered trademarks of Microsoft Corporation.
LabVIEW is a trademark of National Instruments.
Phoenix Contact is a trademark of Samtec, Inc.
All other trademarks are the property of their respective owners.

Overview www.ti.com
4SBAU319–November 2019
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
ADS8686SEVM-PDK Evaluation Module
1 Overview
The ADS8686SEVM-PDK is a platform for evaluating the performance of the ADS8686X family. The EVM-
PDK comes with the ADS8686S SAR ADC, a 16-channel, 16-bit, ±10-V, ±5-V, or ±2.5-V input range,
simultaneous-sampling ADC device. The evaluation kit includes the ADS8686SEVM board and the
precision host interface (PHI) controller board that enables the accompanying computer software to
communicate with the ADC over the USB for data capture and analysis.
The ADS8686SEVM board includes the ADS8686S SAR ADC and all peripheral analog circuits and
components required to extract optimum performance from the ADC.
The PHI board primarily serves three functions:
• Provides a communication interface from the EVM to the computer through a USB port
• Provides the digital input and output signals necessary to communicate with the ADS8686SEVM
• Supplies power to the digital circuitry on the ADS8686SEVM board
Along with the ADS8686SEVM and PHI controller board, this evaluation kit includes an A-to-micro-B USB
cable to connect to a computer.
1.1 ADS8686SEVM-PDK Features
The ADS8686SEVM-PDK includes the following features:
• Hardware and software required for diagnostic testing as well as accurate performance evaluation of
the ADS8686X family of SAR ADC devices
• USB digital power to enable digital communication
• The PHI controller that provides a convenient communication interface to the ADS8686S ADC over a
USB 2.0 (or higher) for digital input and output
• Easy-to-use evaluation software for Windows 7®,Windows 8®, and Windows 10®64-bit operating
systems
• The software suite includes graphical tools for data capture, histogram analysis, spectral analysis, and
linearity analysis. This suite also has a provision for exporting data to a text file for post-processing.
1.2 ADS8686SEVM Features
The ADS8686SEVM includes the following features:
• Onboard SMB and terminal block connectors and RC input filters
• Jumper-selectable onboard precision 2.5-V voltage reference or the ADS8686X family devices internal
reference
• Jumper-selectable ±10-V, ±5-V, or ±2.5-V range
• Jumper-selectable channel sequence selection
• Onboard, ultralow noise, low-dropout (LDO) regulator for excellent 5.0-V, single-supply regulation of
the ADC and onboard voltage reference

ADS8686S
AIN_0A_GND
AIN_0A_P
AIN_0B_GND
AIN_0B_P
SMA Connector
J-1
T2
Terminal Block
(8x1)
1 kŸ
1 kŸ
0 Ÿ
1000 pF
0 Ÿ
Not
Installed
`
SMA Connector
J-9
0 ŸNot
Installed
1
2
3
T4
Terminal Block
(8x1)
1 kŸ
1 kŸ
0 Ÿ
1000 pF
0 Ÿ
Not
Installed
`
0 ŸNot
Installed
1
2
3
www.ti.com EVM Analog Interface
5
SBAU319–November 2019
Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated
ADS8686SEVM-PDK Evaluation Module
2 EVM Analog Interface
The ADS8686SEVM is designed for easy interfacing to analog sources. The four Phoenix Contact™ 8-
terminal headers paired with a respective screw connection tension sleeve, T2 thru T5, provides
convenient and interchangeable access points to all input channels (AIN_0A to AIN_7A and AIN_0B to
AIN_7B) of the device. In addition, the 16 SMB connectors footprints, J-1 to J-16, provide high-quality
connections to channels AIN_0A to AIN_7A and AIN_0B to AIN_7B. Figure 1 shows the ADS8686SEVM
analog input connections and input RC filters for channels AIN_0A to AIN_7A. Table 1 lists the analog
interface connections for header JP1 and Table 2 lists the analog interface connections for the SMB
connectors.
Figure 1. ADS8686SEVM Analog Input Connections for Channels

EVM Analog Interface www.ti.com
6SBAU319–November 2019
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
ADS8686SEVM-PDK Evaluation Module
Table 1. Terminal Block Analog Interface Connections
Terminal # - Pin
Number Signal Description
T2/3 - 1 AIN_0/7A_P Positive analog input for channel AIN0A OR positive analog input for channel AIN7A
T2/3 - 2 AIN_0/7A_GND Negative analog input for channel AIN0A OR negative analog input for channel AIN7A
T2/3 - 3 AIN_1/6A_P Positive analog input for channel AIN1A OR positive analog input for channel AIN6A
T2/3 - 4 AIN_1/6A_GND Negative analog input for channel AIN1A OR negative analog input for channel AIN6A
T2/3 - 5 AIN_2/5A_P Positive analog input for channel AIN2A OR positive analog input for channel AIN5A
T2/3 - 6 AIN_2/5A_GND Negative analog input for channel AIN2A OR negative analog input for channel AIN5A
T2/3 -7 AIN_3/4A_P Positive analog input for channel AIN3A OR positive analog input for channel AIN4A
T2/3 -8 AIN_3/4A_GND Negative analog input for channel AIN3A OR negative analog input for channel AIN4A
T4/5 - 1 AIN_0/7B_P Positive analog input for channel AIN0B OR positive analog input for channel AIN7B
T4/5 - 2 AIN_0/7B_GND Negative analog input for channel AIN0B OR negative analog input for channel AIN7B
T4/5 - 3 AIN_1/6B_P Positive analog input for channel AIN1B OR positive analog input for channel AIN6B
T4/5 - 4 AIN_1/6B_GND Negative analog input for channel AIN1B OR negative analog input for channel AIN6B
T4/5 - 5 AIN_2/5B_P Positive analog input for channel AIN2B OR positive analog input for channel AIN5B
T4/5 - 6 AIN_2/5B_GND Negative analog input for channel AIN2B OR negative analog input for channel AIN5B
T4/5 -7 AIN_3/4B_P Positive analog input for channel AIN3B OR positive analog input for channel AIN4B
T4/5 -8 AIN_3/4B_GND Negative analog input for channel AIN3B OR negative analog input for channel AIN4B
Table 2. SMA Analog Interface ADC-A Connections
SMA Connector Signal Description
J-1 AIN_0A Analog input for channel AIN_0A
J-2 AIN_1A Analog input for channel AIN_1A
J-3 AIN_2A Analog input for channel AIN_2A
J-4 AIN_3A Analog input for channel AIN_3A
J-5 AIN_4A Analog input for channel AIN_4A
J-6 AIN_5A Analog input for channel AIN_5A
J-7 AIN_6A Analog input for channel AIN_6A
J-8 AIN_7A Analog input for channel AIN_7A
Table 3. SMA Analog Interface ADC-B Connections
SMA Connector Signal Description
J-9 AIN_0B Analog input for channel AIN_0B
J-10 AIN_1B Analog input for channel AIN_1B
J-11 AIN_2B Analog input for channel AIN_2B
J-12 AIN_3B Analog input for channel AIN_3B
J-13 AIN_4B Analog input for channel AIN_4B
J-14 AIN_5B Analog input for channel AIN_5B
J-15 AIN_6B Analog input for channel AIN_6B
J-16 AIN_7B Analog input for channel AIN_7B

U4
REF5025 0.22
10µF
1µF
TRIM/NR
VOUT
10k
0.1µF
JP8
10 
ADS8686S
REFINOUT
(Pin 33)
www.ti.com EVM Analog Interface
7
SBAU319–November 2019
Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated
ADS8686SEVM-PDK Evaluation Module
2.1 ADS8686S Internal Reference and EVM Onboard Reference
The ADS8686S device incorporates an internal 2.5-V reference. Alternatively, the user can select the
onboard 2.5-V reference, REF5025 (U4). The reference voltage source is determined by setting REFSEL
(pin 35) of the ADS8686S device. By default, the evaluation module is set up with the ADS8686S internal
reference source, with a shunt jumper installed on JP6 (REFSEL). If the onboard REF5025 2.5-V
reference is desired, the shunt jumper must be removed from JP6 and placed on JP8 (REFIN/OUT). For
more information, see Section 5.1. The output of the REF5025 is filtered through a passive RC filter and
connected to the REFINOUT pin (pin 33) of the ADS8686S using jumper JP8 (REFIN/OUT). Figure 2
shows a schematic for the reference circuit.
Figure 2. REF5025 2.5-V External Reference Source
3 Digital Interfaces
As noted in Section 1, the EVM interfaces with the PHI that, in turn, communicates with the computer over
the USB. There are two devices on the EVM with which the PHI communicates: the ADS8686S ADC (over
a single or dual SDO serial interface or parallel interface) and the EEPROM (over I2C). The EEPROM
comes preprogrammed with the information required to configure and initialize the ADS8686SEVM-PDK
platform. The EEPROM is initially programmed to communicate with the ADS8686S, but can be
reprogrammed for any of the supported devices in the ADS8686X device family through their respective
GUI software. See Section 5.2 for more information and instructions. After the hardware is initialized, the
EEPROM is no longer used.
3.1 ADS8686S Digital Interface
The ADS8686SEVM-PDK supports parallel, parallel byte, and serial digital interface as detailed in the
ADS8686S data sheet. The PHI controller is configured to operate at a 3.3-V logic level and is directly
connected to the digital I/O lines of the ADC. The digital interface configuration can be easily selected by
navigating within the ADS8686SEVM GUI to Device Configuration tab. For more information, see
Section 6.1.
Socket strip connector J17 provides the digital I/O connections between the ADS8686SEVM board and
the PHI controller. Table 4 summarizes the pin outs for connector J17.
Table 4. Digital I/O Connections for Connector J17
Pin Number Signal Description
J17.6, J17.8, J17.10 DB15/OS2, DB14/OS1, DB13/OS0 Parallel data output connections OR oversampling mode control
pins
J17.12, J17.14, DB12/SDOA, DB11/SDOB Parallel data output connections OR serial data output
connections
J17.16, DB10/SDI Parallel data output connections OR serial data input connections
J17.18 DB9/BYTESEL Parallel data output connections OR enable parallel byte
interface
J17.20 DB8/FLTEN Parallel data output connections
J17.22,J17.24 DB7, DB6 Parallel data output connections
J17.26 DB5/CRCEN Parallel data output connections OR enable CRC word
J17.28 DB4/SER1W Parallel data output connections OR serial data output wire select

Power Supplies www.ti.com
8SBAU319–November 2019
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
ADS8686SEVM-PDK Evaluation Module
Table 4. Digital I/O Connections for Connector J17 (continued)
Pin Number Signal Description
J17.30 DB3 Parallel data output connections
J17.32, J17.34 CSn CS select, active low
J17.36 SCLK/RD Clock input pin in serial interface mode OR active-low ready input
pin in parallel and parallel byte interface
J17.38, J17.40, J17.42 DB2, DB1, DB0 Parallel data output connections
J17.44 CONVST Active high logic input to control start of conversion
J17.46, J17.48 HW_RNGSEL1,0 Pins used to select input range of device (±10 V, ±5 V, or ±2.5 V)
J17.50 DVDD 3.3-V digital supply from the PHI controller board
J17.56, J17.58 I2C Bus I2C bus; used only to read the EEPROM (U5) in the EVM board
J17.3, J17.60 GND Ground connections
J1721 WR/BURST Write register configuration in parallel and parallel byte modes
OR enable burst mode
J17.23 BUSY Active high digital output indicating ongoing conversion
J17.31 SEQEN Active high digital input enabling channel sequencer
J17.33 RESET Active low logic input to reset the device
J17.39 SER/BYTE/PAR Logic input pin to select between serial, parallel byte, or parallel
interface mode
J17.41, J17.43, J17.45 CHSEL0,1,2 Logic input pin to select channel for hardware mode sequencer
J17.59 ID_POWER Power supply used only to power the EEPROM (U3) in the EVM
board
4 Power Supplies
4.1 Device Power Supplies
The ADS8686S ADC analog supply (AVDD) is provided by a low-noise linear regulator (TPS7A4700). The
regulator uses a 5.5-V external supply provided through terminal block T1 (PWR) connected in position 3
(5.5V), and position 4 (GND). This (TBD this what?) is connected to JP7 set to position EXT (pins 2 and
3). The switching regulator (U2) is not populated, and the EVM does not support setting JP7 in position
INT (pins 1 and 2). The 3.3-V supply to the digital supply of the ADS8686S is provided directly by an LDO
on the PHI controller. The power supply for each active component on the EVM is bypassed with a
ceramic capacitor placed close to that component. Additionally, the EVM layout uses thick traces or large
copper filled areas where possible between bypass capacitors and their loads to minimize inductance
along the load current path.
CAUTION
When using the ADS8686SEVM in conjunction with the PHI controller, install a
shunt between JP7 pins 2-3 as shown in Figure 4 The PHI controller supplies
the DVDD power supply. Do not use the JP7 internal setting or the device can
be damaged.
CAUTION
When using the ADS8686SEVM as a stand-alone board, install a shunt
between JP7 (pins 2 and 3) and connect the analog supply (AVDD) on the
terminal block T1 (position 3 or 4). For the digital supply (DVDD), remove R28
and supply DVDD on the terminal block T1 (position 1 or 2). Make sure that the
AVDD voltage is in the range between 5.5 V to 6 V, and that DVDD is in the
range of 2.3 V < DVDD < AVDD for proper device operation. Do not exceed the
absolute maximum ratings for the ADS8686S device, or damage may occur.

R132
10k
-
+
+
OPA192
R129
100k
+15V
-15V
BIN1J+BIN1J+ BIN1+
T6
GND
1
2
3
+15V
-15V
-
+
+
INA149
+15V
-15V
BIN2J+ BIN2+
GND
GND
www.ti.com Power Supplies
9
SBAU319–November 2019
Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated
ADS8686SEVM-PDK Evaluation Module
4.2 High-Voltage Power Supplies
As shown in Figure 3, the ADS8686SEVM is equipped with two input driving amplifiers for two ADS8686S
analog inputs. The device input AIN_0B can be driven by U6, the OPA192 (a precision rail-to-rail
operational amplifier) in a buffer configuration. Input AIN_B1 can be driven by a difference amplifier, U7
(INA149). Each of these amplifiers require positive and negative power rails over the expected maximum
and minimum input levels, and the recommended supply is ±15 V. Connect an external power supply to
terminal block T6 (HV PWR) to provide the high-voltage power supplies. See the respective device data
sheet for more information.
By default, each of the amplifiers are bypassed. To include the OPA192 in the input driving circuit to
channel AIN_0B, remove the 0-Ωresister, R127, and populate R129 and R128 with 0-Ωresisters. The
input can be connected through either terminal block T4 (position 3 or4) or by the BNC connector J10. To
include the INA149 in the input driving circuit to channel AIN_1B, remove the 0-Ωresistors, R130 and
R133, and populate R134, R135, and R131. Inputs can be connected through either terminal block T4
(position 5 or 6) or by the BNC connector J11. To use a different value other than ground for input
AIN_1BGND, use terminal block T4, position 6.
Figure 3. High-Voltage Power Supply for Amplifiers
NOTE: The high-voltage power supplies connected to terminal block T6 only provide power to U6
and U7, the input driving amplifiers. The high-voltage power supplies are not connected to
any other device on the board.
CAUTION
Terminal T6 (HV PWR) on the ADS8686SEVM is intended for high-voltage
supplies and does not have a protection scheme or regulation circuitry onboard.
When connecting an external power supply to T6 use a clean and precise
supply, otherwise damage can occur to the driving amplifiers U6 and U7.

Initial Setup www.ti.com
10 SBAU319–November 2019
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
ADS8686SEVM-PDK Evaluation Module
5 Initial Setup
This section explains the initial hardware and software setup procedure that must be completed for the
proper operation of the ADS8686SEVM-PDK.
5.1 Default Jumper Settings
Install a shunt at JP6 to select the internal reference. Install a shunt between JP7 (pins 2 and 3) as shown
in Figure 4 to connect the onboard regulated AVDD 5.0-V supply. Figure 4 details the default jumper
settings. Table 5 explains the configuration for these jumpers. When the EVM is paired with the PHI
board, the jumper selections on JP1 thru JP5 have no effect in either hardware or software mode. The
GUI provides user-selectable options to control these settings and overrides the jumper selection. When
the EVM is used standalone, the jumper settings take effect in the device settings.
Figure 4. ADS8686SEVM Default Jumper Settings
Table 5. Default Jumper Configuration
Jumper Function Default Position Description
JP1, JP3, JP5 CHSEL0, CHSEL1,
CHSEL2 Open 1-2 logic high, 2-3 logic low. Programs the channel sequencer.
JP2, JP4 HW_RNGSEL0,
HW_RNGSEL1 Open 1-2 logic high, 2-3 logic low. Selects the analog input range.
JP6 REFSEL Closed Open selects the external reference; closed selects the internal reference
JP7 AVDD Ext Closed between
pins 2 and 3 2-3 external source regulated with the onboard LDO to the AVDD 5.0-V supply

www.ti.com Initial Setup
11
SBAU319–November 2019
Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated
ADS8686SEVM-PDK Evaluation Module
Table 5. Default Jumper Configuration (continued)
Jumper Function Default Position Description
JP8 REFIN/OUT Open Open when using the internal reference; closed connects the external onboard
reference
5.2 EVM Graphical User Interface (GUI) Software Installation
NOTE: Manually disable any antivirus software running on the computer before downloading the
EVM GUI installer onto the local hard disk. Otherwise, depending on the antivirus settings,
an error message may appear or the installer.exe file may be deleted.
The following steps list the directions to install the software using the ADS8686S as an example.
Download and install the ADS8686SEVM software GUI from he ADS8686SEVM-PDK product folder.
Administrator privileges are required on the PC to install the EVM software.
Accept the license agreements and follow the on-screen instructions to complete the installation, as shown
in Figure 5, after downloading and starting the GUI installer.
Figure 5. Software Installation Prompts

Initial Setup www.ti.com
12 SBAU319–November 2019
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
ADS8686SEVM-PDK Evaluation Module
A prompt with a Device Driver Installation appears on the screen, as shown in Figure 6, as part of the
ADS8686S EVM GUI installation. Click Next to proceed.
Figure 6. ADS8686S Device Driver Installation Wizard Prompts
NOTE: A notice may appear on the screen stating that Widows cannot verify the publisher of this
driver software. Select Install this driver software anyway.
TheADS8686SEVM-PDK requires the LabVIEW™ Run-Time Engine. A prompt appears for the installation
of this software, as shown in Figure 7, if not already installed.
Figure 7. LabVIEW Run-Time Engine Installation

www.ti.com Initial Setup
13
SBAU319–November 2019
Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated
ADS8686SEVM-PDK Evaluation Module
The installation is now complete. The prompts shown in Figure 8 confirm that the software is installed.
Figure 8. Software Installation Complete Prompts
Verify that the contents of C:\Program Files (x86)\Texas Instruments\ADS8686 EVM is as shown in
Figure 9 after installation.
Figure 9. ADS8686S EVM Folder Post-Installation

Operation www.ti.com
14 SBAU319–November 2019
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
ADS8686SEVM-PDK Evaluation Module
6 Operation
The following instructions are a step-by-step guide to connecting the ADS8686S to the computer and
evaluating the performance of the ADS8686S:
1. Connect the ADS8686SEVM to the PHI. Install the two screws as indicated in Figure 10.
2. Use the USB cable provided to connect the PHI to the computer.
a. LED D5 on the PHI lights up, indicating that the PHI is powered up.
b. LEDs D1 and D2 on the PHI starts blinking to indicate that the PHI is booted up and
communicating with the PC. Figure 10 shows the resulting LED indicators.
Figure 10. ADS8686SEVM-PDK Hardware Setup and LED Indicators

www.ti.com Operation
15
SBAU319–November 2019
Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated
ADS8686SEVM-PDK Evaluation Module
3. As shown in Figure 11, double click the ADS8686EVM.exe file to launch the EVM GUI.
Figure 11. Launch the ADS8686SEVM GUI Software

Operation www.ti.com
16 SBAU319–November 2019
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
ADS8686SEVM-PDK Evaluation Module
6.1 EVM GUI Global Settings for ADC Control
Although the EVM GUI does not allow direct access to the voltage levels and timing configuration of the
ADC digital interface, the EVM GUI provides high-level control over the ADS8686S interface modes and
RD/SCLK clock frequency. In addition, the EVM GUI provides control to device configuration settings such
as sampling rate and number of samples to be captured, as well as register mapping such as input range
selection, oversampling setting, and channel sequence selection.
Figure 12 shows the Interface Configuration pane at the left, through which timing functions of the
ADS8686S are exercised. These are global settings and persist across the different GUI Pages listed in
the top left pane. TheSCLK Frequency (Hz) and Sampling Rate (sps) can be selected on this pane,
depending on the selected interface and OSR settings. Enter the targeted values for these two
parameters, and the GUI considers the timing constraints of the selected interface and computes the best
values that can be achieved. Enter a Target value in the SCLK Frequency (Hz) field, and the GUI matches
this frequency as closely as possible by changing the PHI PLL settings, and then displaying the
Achievable frequency that may differ from the entered Target value. Similarly, adjust the ADC Sampling
Rate (sps) by entering a Target value (Hz = sps). The Achievable ADC sampling rate can differ from the
Target value, depending on the applied RD/SCLK frequency and selected Interface. The closest
achievable match is then displayed. Therefore, this pane allows the various settings available on the
ADS8686S to be tested in an iterative fashion until the best settings for the corresponding test scenario
are achieved.
Displayed above this (TBD this what?) are the Full Reset and Partial Reset buttons. Each of these buttons
initiates its respective reset type through software. A hardware reset can be initiated by pressing S1 RST
on the EVM. When a master reset, either through software or hardware occurs the device resets to the
default register settings. The GUI automatically generates a reset pulse when required to execute device
configurations; there is no need to press the Full Reset button. At the bottom left, the Current Device
Mode pane displays the operational mode the device is currently in, which also persists across the GUI
tools and pages.
Figure 12. EVM GUI Global Input Parameters

www.ti.com Operation
17
SBAU319–November 2019
Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated
ADS8686SEVM-PDK Evaluation Module
6.2 Register Map Configurations
The Register Map Config page (Figure 13) provides access to the device register mapping. Within the
page, the user registers listed can be easily changed through a drop down provided under the Field View
on the right. When a register is selected, the options available are listed, when an option is selected, that
option is reflected in the Value column. When a register configuration is made, that configuration persists
through all GUI pages. See the device data sheet for more information on device registers.
Figure 13. Register Map Configuration Display
6.3 Device Configuration
The device configuration page provides a user-friendly interface to the most common configuration
options. When a setting is changed, that setting persists through all GUI pages and is also reflected in the
Current Device Mode box if listed. When making a change that requires a reset pulse to the device, the
GUI provides the pulse when the setting is changed; there is no need to press the Full Reset button.
At the top of the page are drop-down menu options for the Interface Mode,Device Mode, and Serial
Output Mode. The Interface Mode field allows the choice of three interface options: serial, parallel, or
parallel byte. Serial interface communication occurs through either single or dual serial output:
DB12/SDOA and DB11/SDOB that can be selected in the Serial Output Mode field. Parallel interface
communication occurs through the DB[15:0] parallel bus, parallel byte through the DB[7:0] parallel bus.

Operation www.ti.com
18 SBAU319–November 2019
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
ADS8686SEVM-PDK Evaluation Module
6.3.1 Software Mode
The page displays the setting options as shown in Figure 14 when in software mode. The setting are
displayed in three sections, Configuration,Individual Range Selections, and Sequencer Configuration.
In the left-most section, Configuration, channel selection options for each ADC is provided. In software
mode the device allows the ADC channels sampled not to correspond with each other (for example,
channel AIN_0A can be sampled with channel AIN_2B). The device also supports sequencer mode that
can be enabled in this section. When this mode is disabled, the Burst Mode option is grayed out because
burst mode is only available with the Sequencer Mode option enabled. To use burst mode, first enable
Sequencer Mode, then enable Burst Mode. The ADS8686S supports an oversampling mode of operation
using an on-chip averaging digital filter, as explained in the device data sheet. The oversampling ratio
(OSR) settings drop-down menu in this section provides selectable oversampling ratios of 2x, 4x, 8x, 16x,
32x, 64x, and 128x. The Filter Settings drop down provides a drop-down field to select the cutoff
frequency of the internal second-order, low-pass filter: 15 kHz, 39 kHz, or 300 kHz.
The middle section, Individual Range Selection, is used to select the input range of each input channel of
the device: ±10 V, ±5 V, or ±2.5 V. Each channel can also support an input range increase of 20% of the
selected input range by checking the Over Range option. More information on the overrange setting is
available in the device data sheet.
The right most section, Sequencer Configuration, provides a user-friendly interface to set the channel
stack setting in sequencer mode. The device supports up to 32 stack options, navigating through the
Jump to Page buttons displays these options. The stack length is selected by checking the Last Layer box
of the final stack desired. Each stack can support non-corresponding input channels between ADC A and
ADC B.
Figure 14. Device Configuration in Software Mode

www.ti.com Operation
19
SBAU319–November 2019
Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated
ADS8686SEVM-PDK Evaluation Module
6.3.2 Hardware Mode
When in hardware mode, Figure 15 shows the setting options for the Device Configuration page. The
device has limited configuration options in hardware mode, whcih are disabled in the GUI. The Register
Map Config page is also not accessible in hardware mode.
In hardware mode, simultaneous sampling is restricted to the corresponding ADC A and ADC B channel,
that is, channel AIN_0A is always sampled with channel AIN_0B. The diagnostic channels can not be
sampled in the hardware mode of operation. All input channels are configured to the same input range in
hardware more. Sequencer mode is supported in hardware mode. When sequencer mode is disabled, the
Burst Mode option is grayed out because burst mode is only available with sequencer mode enabled. The
oversampling setting is also available in hardware mode, and can be selected using the drop-down field.
The Float Detection option is displayed as a drop-down field in the Device Configurations page because
the Register Map Config page is inaccessible in hardware mode.
Figure 15. Device Configuration Display in Hardware Mode

Operation www.ti.com
20 SBAU319–November 2019
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
ADS8686SEVM-PDK Evaluation Module
6.4 Time Domain Display Tool
The Time Domain Display tool (Figure 16) allows visualization of the time domain conversion results given
a set of analog input signals.
The GUI Time Domain Display shows two time domain voltage plots: the top time domain plot shows the
conversion results ADC A and the bottom display shows conversion results for ADC B. The sample
indices are on the x-axis and there are two y-axes showing the corresponding converted analog voltages.
Any combination of desired channels can be selected using the Analog CH AINx selection buttons at the
top-right side of the display.
When the Capture button is pressed, the software captures a contingent number of samples that are
selected in the Samples field. In addition, the bottom-right side of the GUI provides information about the
converted signals, such as the selected channel maximum and minimum code, maximum and minimum
voltage, and the calculated RMS voltage value for the captured signal on each channel.
Figure 16. Time Domain Display