Texas Instruments BoosterPack BOOSTXL-IOLINKM-8 EVM User manual

User's Guide
BOOSTXL-IOLINKM-8 EVM User's Guide
ABSTRACT
This BoosterPack™ was designed to operate with the LP-AM243 TI LaunchPad™ kit with Sitara™ AM243x MCU.
Together this design implements an eight port IO-Link Master with fast and deterministic timing and independent
cycle and bit rate configuration. This design can be used to build a remote IO gateway to connect to OPC UA,
Profinet, EtherCAT, or Ethernet IP. The Programmable Real-Time Unit (PRU) for Sitara ™ Processors based
frame handler provides a flexible way of controlling timing and synchronization.
Table of Contents
Get Started..................................................................................................................................................................................2
Features......................................................................................................................................................................................2
Applications............................................................................................................................................................................... 2
1 Evaluation Module Overview................................................................................................................................................. 3
1.1 Introduction........................................................................................................................................................................ 3
1.2 Kit Contents........................................................................................................................................................................3
1.3 Specification.......................................................................................................................................................................3
1.4 Device Information............................................................................................................................................................. 4
2 Hardware............................................................................................................................................................................... 12
2.1 Power Requirements........................................................................................................................................................12
2.2 Power Configuration Headers.......................................................................................................................................... 13
2.3 BoosterPack Pinout Headers........................................................................................................................................... 14
2.4 Push Buttons....................................................................................................................................................................15
2.5 Test Points and Status LEDs............................................................................................................................................16
2.6 M12 Connector Mechanical Stiffener Plate......................................................................................................................22
2.7 Assembly Instructions...................................................................................................................................................... 23
2.8 What to Do and What Not to Do.......................................................................................................................................23
3 Software.................................................................................................................................................................................24
3.1 Software Description........................................................................................................................................................ 24
3.2 Software Installation.........................................................................................................................................................24
3.3 GUI Installation.................................................................................................................................................................24
3.4 Software Development.....................................................................................................................................................24
4 Implementation Results....................................................................................................................................................... 25
4.1 Test Setup........................................................................................................................................................................ 25
4.2 Test Results......................................................................................................................................................................25
5 Hardware Design Files......................................................................................................................................................... 32
5.1 Schematics.......................................................................................................................................................................32
5.2 PCB Layouts.................................................................................................................................................................... 41
5.3 Bill of Materials (BOM)..................................................................................................................................................... 47
Trademarks
BoosterPack™, LaunchPad™, Sitara™, and HotRod™ are trademarks of Texas Instruments.
IO-Link® is a registered trademark of Profibus User Organization.
All trademarks are the property of their respective owners.
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Get Started
1. Order the BOOSTXL-IOLINKM-8 BoosterPack™ and the LP-AM243 LaunchPad™
2. Download and read the comprehensive reference design files and User's Manuals
3. Download the latest firmware libraries and follow the LaunchPad™programming instructions
4. Assemble the BoosterPack™ and LaunchPad™
Features
• Eight IO-Link ports
• Supports IO-Link transmission rates COM1, COM2, and COM3
• Supports 400-µs cycle time
• Can provide 500-mA of current per port
• Overcurrent protection and limiting on all ports
• PRU frame handler enables flexible timing
Applications
•Stand-Alone Remote IO
•Communication Module
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1 Evaluation Module Overview
1.1 Introduction
This BoosterPack contains all of the analog circuitry needed to create an eight-port IO-Link Master when
combined with the LP-AM243 LaunchPad containing the processor and framehandler. Each identical port
contains a M12 connector with an IO-Link communication line (CQ), a 24-V power supply (L+) with a power
supply return or ground (L-), and a digital input line (DI).
Each port uses an IO-Link TIOL112 transceiver configured for master-mode, which implements the physical
layer interface for an IO-Link Master interface, including the required integrated current sink on the CQ line.
The TIOL112 offers a current limit of 700mA during the wake-up pulse, which exceeds the minimum 500-mA
requirement, but not enough to overload the cables or power supplies and generate fault conditions. The
TIOL112 also limits the slew rate of the CQ line to minimize overshoots, reduce emissions and improve
communication while still achieving COM3 performance with 230 kbps data rates.
The eight 24-V power supply channels are implemented with two TPS274160 quad-channel high side switches
offering individual current monitoring and a configurable current limit to protect against overloaded outputs and
fault conditions.
An eight-channel, 24-V, SN65HVS883 digital input serializer is used to monitor the Digital Input (DI) pins of each
port when read by the processor as well as drive blue Status LEDs to reflect the line values.
General port status is provided by the processor through red and green status LEDs on each port controlled by a
TCA6424A I2C-to-GPIO Expander.
The BoosterPack is protected from over-voltage, under-voltage, over-current, reverse polarity and other fault
conditions on the primary 24-V power supply through the TPS26631 eFuse. The supply current is also monitored
for diagnostic use by the processor.
A 3.3-V digital voltage rail is created from the 24-V supply with an LMR36503 DC/DC buck converter allowing
the entire BoosterPack board to be powered from the single 24-V power supply. However, the 3.3-V supply from
the LaunchPad could be used instead with a simple jumper configuration.
1.2 Kit Contents
• EVM Board (Qty 1)
• M12 Connector Stiffener Plate (Qty 1)
• M2.5x0.45 Pan Head Machine Screw (Qty 5)
1.3 Specification
1. Texas Instruments, IO-Link Master Demo
2. Texas Instruments, TIOL112 and TIOL112x IO-Link Device Transceivers with Low Residual Voltage
andIntegrated Surge Protection in Small Packages data sheet
3. Texas Instruments, AM243x Sitara™ Microcontrollers data sheet
4. IO-Link Interface and System Specification V1.1.3
5. IO-Link Test Specification V1.1.3
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1.4 Device Information
1.4.1 TIOL112
The TIOL112(x) family of transceivers implements the IO-Link interface for industrial bidirectional, point-to-point
communication. When the device is connected to an IO-Link master through a three-wire interface, the master
initiates communication and exchange data with the remote node while the TIOL112(x) acts as a complete
physical layer for the communication. These devices are capable of withstanding up to 1.2 kV (500 Ω) of
IEC 61000-4-5 surge and feature integrated reverse polarity protection. A simple pin programmable interface
allows easy interfacing with the controller circuits. The output current limit can be configured using an external
resistor. TIOL112(x) can be configured to generate wake-up pulse and be used in IO-link master applications.
Fault reporting and internal protection functions are provided for undervoltage, overcurrent and overtemperature
conditions.
DIAGNOSTICS
& CONTROL
CONTRO
L LOGIC
ILIM_ADJ
CUR_OK
EN
TX
PWR_OK
L+
CQ
L-
TMP_OK
WAKE
RX
NFAULT
Rev.
Polarity
Protection
Rev. Polarity
Protection
ESD and
Surge
Protection
ESD and
Surge
Protection
VCC_IN
Figure 1-1. TIOL112 Functional Block Diagram
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1.4.2 TPS26631
The TPS2663x devices are easy to use, positive 60 V and 6-A eFuse with a 31-mΩ integrated FET. It features
a B-FET driver to control an external N-channel FET in the system designs that require protection from
input reverse polarity faults and reverse current blocking. The device incorporates robust protection features
that simplify system designs requiring protection during system tests like IEC61000-4-5 industrial surge tests.
The device features an adjustable output power limiting (PLIM) functionality that simplifies the system design
requiring compliance in accordance to the standards like IEC61010-1 and UL1310. Additional protection features
include adjustable overcurrent protection, fast short circuit protection, output slew rate control, overvoltage
protection and undervoltage lockout. For system status monitoring and downstream load control, the device
provides fault and a precise current monitor output. PGOOD can be used for enable and disable control of
the downstream DCDC converters. The MODE pin allows flexibility to configure the device between the two
current-limiting fault responses (latch off and auto-retry).
IMON
OUT
UVLO
+
Current
Sense
4.3 V
4.2 V
+
OVP
2 µA
PORb
UVLOb
SWEN
25x
14 Ÿ
65 Ÿ
X27.9 µ
xx
ILIM
1.2 V
1.12 V
Ramp Control
Q
Q
SET
CLR
S
R
SHDNb
Current Limit Amp
PORb
Gate Control Logic
FLT
Charge
Pump (12 V)
GND
TSD
PORb
UVLOb
SHDNb
Thermal
Shutdown
SHDN
4.17V
Fault Latch
Open/ Short
detect
2.7V
+
0.8 V
TSD
OLR
SWEN
* Only for Latch Mode
IN_SYS
IN_SYS
CP
MODE
OLR
162 msec
timer
I(OUT) = I(OL)
Timeout
31 PŸ
5 V
Overload fault response
(Auto-Retry/Latch-off)
select detection
3V
Q
Q
SET
CLR
S
R
PGOOD
65 Ÿ
1 0HJŸ
Fast-Trip Comp
(Threshold= 45A)
IN
dVdT
+
+
±
-15mV
+57mV
IN_SYS
1.3msec
+
PGTH
1.2V
1.12V 2 µs
Fast_Charge
_EN
SHDNb
Gate Enhanced (HS_FET)
1.2 0HJŸ
B_GATE
Power Limit Amp
25.5 msec
timer
I(OUT) > I(CB)
Timeout
*TPS26631
Only
REVERSE
20 µA
P(OUT) = P(LIM)
SHDNb
Fast_Charge
_EN
DRV
TPS26630 & TPS26631
+OVP
1.2 V
I(OUT) = I(OL)
VSEL_UVLO +
±
VSEL_OVP +
±
1.12 V
Figure 1-2. TPS26631 Functional Block Diagram
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1.4.3 LMR36503
The LMR36503 is the industry smallest 65 V, 0.3 A synchronous step-down DC/DC converter in 2- mm × 2-mm
HotRod™ package. This easy-to-use converter can handle input voltage transients up to 70 V, provide excellent
EMI performance and support fixed 5 V and other adjustable output voltages. The transient tolerance reduces
the necessary design effort to protect against input overvoltage and meets the surge immunity requirements of
IEC 61000-4-5. The LMR36503 uses the peak current mode control architecture with internal compensation to
maintain stable operation with minimal output capacitance. The LMR36503 with the right resistor selection from
the RT pin to ground can be externally programmed to any desired switching frequency of operation over a wide
range from 200 kHz to 2.2 MHz. The precision EN/UVLO feature allows precise control of the device during the
start-up and shutdown. The power-good flag, with built-in glitch filter and delayed release, offers a true indication
of the system status, eliminating the requirement for an external supervisor. The compact size and feature set of
LMR36503 simplifies implementation for a wide range of industrial applications.
PGOOD
PGOOD
LOGIC
FB
OSCILLATOR
EN
CONTROL
LOGIC &
DRIVER
ENABLE
GND
SW
VIN
LDO
+
±
MAX. &
MIN.
LIMITS
ERROR
AMPLFIER
+
±
+
HS
CURRENT
SENSE
SLOPE
COMPENSATION
VREF
VCC
+
±
±
+
HS
CURRENT
LMIT
CLOCK
FSW FOLDBACK
MIN.
LS CURRENT
LIMIT
+
±
THERMAL
SHUTDOWN
CLOCK
COMP
SOFT-
START
&
BANDGAP
SYS ENABLE
VCC UVLO
VCC UVLO
GND
VIN
FPWM or AUTO
RT
VOUT/
BIAS
LS
CURRENT
LMIT
SYS ENABLE
TSD
TSD
TSD
LS
CURRENT
SENSE
VOUT UV/OV
VOUT UV/OV
ADJ. OUTPUT
VOLTAGE
VARIANTS ONLY
FIXED OUTPUT
VOLTAGE
VARIANTS
ONLY
FIXED OUTPUT
VOLTAGE
VARIANTS
ONLY
ADJ. OUTPUT
VOLTAGE
VARIANTS ONLY
FIXED
OUTPUT
VOLTAGE
VARIANTS
ONLY
VOUT/
BIAS
FB
VOUT/
BIAS
SYS ENABLE
BOOT
Figure 1-3. LMR36503 Functional Block Diagram
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1.4.4 TLV9001
The TLV900x family includes single (TLV9001), dual (TLV9002), and quad-channel (TLV9004) low-voltage (1.8
V to 5.5 V) operational amplifiers (op amps) with rail-to-rail input and output swing capabilities. These op
amps provide a cost-effective solution for space-constrained applications such as smoke detectors, wearable
electronics, and small appliances where low-voltage operation and high capacitive-load drive are required. The
capacitive-load drive of the TLV900x family is 500 pF, and the resistive open-loop output impedance makes
stabilization easier with much higher capacitive loads. These op amps are designed specifically for low-voltage
operation (1.8 V to 5.5 V) with performance specifications similar to the TLV600x devices. The robust design of
the TLV900x family simplifies circuit design. The op amps feature unity-gain stability, an integrated RFI and EMI
rejection filter, and no-phase reversal in overdrive conditions.
The TLV900x devices include a shutdown mode (TLV9001S, TLV9002S, and TLV9004S) that allow the
amplifiers to switch off into standby mode with typical current consumption less than 1 µA. Micro-size packages,
such as SOT-553 and WSON, are offered for all channel variants (single, dual, and quad), along with industry-
standard packages such as SOIC, MSOP, SOT-23, and TSSOP packages.
Reference
Current
V+
VIN- VIN+
V
(Ground)
-
VBIAS2
VBIAS1 Class AB
Control
Circuitry
VO
Figure 1-4. TLV9001 Functional Block Diagram
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1.4.5 TCA6424A
This 24-bit I/O expander for the two-line bidirectional bus (I2C) is designed to provide general-purpose remote
I/O expansion for most microcontroller families via the I2C interface [serial clock (SCL) and serial data (SDA)].
The major benefit of this device is its wide VCC range. It can operate from 1.65 V to 5.5 V on the P-port side
and on the SDA/SCL side. This allows the TCA6424A to interface with next-generation microprocessors and
microcontrollers on the SDA/SCL side, where supply levels are dropping down to conserve power. In contrast to
the dropping power supplies of microprocessors and microcontrollers, some PCB components, such as LEDs,
remain at a 5-V power supply.
29
I/O Port
Shift
Register 24 Bits
Input
Filter
30
Power-On
Reset
Read Pulse
Write Pulse
26
27
25
GND
VCCP
SDA
SCL
ADDR
I C Bus
Control
2
RESET 28
INT Interrupt
Logic
LP Filter
32
VCCI
31
P27
P17–P10
P07–P00
–P20
Figure 1-5. TCA6424A Functional Block Diagram
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Data From
Shift Register
Write Configuration
Pulse
Write Pulse
Read Pulse
Write Polarity Pulse
Polarity
Inversion
Register
Input
Port
Register
Output
Port
Register
Configuration
Register VCCP
GND
Input Port
Register Data
Polarity
Register Data
ESD Protection Diode
P00 to P27
Output Port
Register Data
To INT
Q1
Q2
D
FF
CK
Q
Q
D
FF
CK
Q
Q
D
FF
CK
Q
Q
D
FF
CK
Q
Q
Data From
Shift Register
Data From
Shift Register
Figure 1-6. TCA6424A Simplified Schematic of P00 to P27
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1.4.6 TPS274160
The TPS274160 device is a smart high-side switch with four integrated 160-mΩ NMOS power FETs and a
charge pump to drive the gates. The device offers robust protection and diagnostic features to drive various
loads (inductive, capacitive, and resistive) such as low wattage bulbs, LEDs, relays, solenoids, heaters, and
sub-modules. The part enables flexible, multi-channel output configurations through paralleling channels and
is in a very small WQFN package to enable usage in space constrained applications. The device is protected
against short circuit events and over-temperature events, safely shutting off the output during fault events. The
device also implements an external adjustable current limiting feature. This feature improves the reliability of
the system by reducing inrush current when driving large capacitive loads and minimizing overload current
thereby eliminating system supply brown out condition. The device also integrates diagnostic features like output
current monitoring (version B) and open load detection to enable improved intelligence in modules and to enable
predictive maintenance functionality.
Output
Clamp
Temperature Sensor
Gate Driver
and
Charge Pump
Protection
and
Diagnostics
Current-Sense
Mux
Current Limit
Current Sense
ESD
Protection
Current Limit
Reference
Oscillator
Internal LDO
Internal Reference
Auxiliary Charge Pump
Diagnosis
4Temperature
Sensor OTP
2
OUT1
OUT2
OUT3
OUT4
VS
GND
ENx
THER
CS
SEH
SEL
CL
FAULT
DIAG_EN
STx
Figure 1-7. TPS274160 Functional Block Diagram
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1.4.7 SN65HVS883
The SN65HVS883 is a 24-V, eight-channel, digital input serializer for high-channel density digital input modules
of PC and PLC-based systems in industrial automation. In combination with galvanic isolators, the device
completes the interface between the 24-V sensor outputs of the field-side and the low-voltage controller inputs
at the control-side. Input signals provided by EN60947-5-2 compliant 2-wire and 3-wire proximity switches are
current-limited and then validated by internal debounce filters. The input switching characteristic is in accordance
with IEC61131-2 for Type 1, 2, and 3 sensor switches.
Upon the application of load and clock signals, input data is latched in parallel into the shift register and
afterwards clocked out serially via a subsequent isolator into a serial PLC input.
Cascading of multiple SN65HVS883 is possible by connecting the serial output of the leading device with the
serial input of the following device, enabling the design of high-channel count input modules. Input status is
indicated via 3-mA constant current LED outputs. An external precision resistor is required to set the internal
reference current. The integrated voltage regulator provides a 5-V output to supply low power isolators. An
internal supply voltage monitor provides a chip-okay (CHOK) indication.
The SN65HVS883 comes in a 28-pin PWP PowerPAD™ package allowing for efficient heat dissipation. The
device is specified for operation at temperatures from –40°C to 85°C.
Voltage
Regulator
Supply
Monitor
Adj. Current
Thresholds
Debounce
Select
Current
Sense
Voltage
Sense
Debounce
Filter
SERIALZER
&
Channel 0
Channel 7
V24
FGND
RLIM
RE0
IP0
RE7
IP7
5V
CHOK
SIP
SOP
CLK
LD
CE
DB0
DB1
5VOP
Copyright © 2016, Texas Instruments Incorporated
Figure 1-8. SN65HVS883 Functional Block Diagram
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2 Hardware
2.1 Power Requirements
The IO-Link Master BoosterPack™ is powered from an 24-V supply connected to either the DC Power Jack (2.0
mm I.D x 6.5 mm O.D max) J6, or the 2-pin screw terminal block J7.
PARAMETER SPECIFICATION
Input voltage External 24-V power supply
Input current Dependent on connected load (5 A recommended)
Output voltage 24 V
Output current per port 500 mA
Number of IO-Link master ports 8
Total output current 4 A
To avoid damaging the inputs of the LaunchPad, the BOOSTXL-IOLINKM-8 board should not be powered prior
to the LaunchPad. The Shutdown (SHDN) pin of the TPS26631 eFuse device can be used disconnect the 24-V
supply to the board when the LaunchPad board is not powered by using the LaunchPad 3V3 supply voltage to
control the shutdown (SHDN) pin.
The BOOSTXL-IOLINKM-8 board can be used when disconnected from the LaunchPad board such as when
doing certain physical layer testing with test equipment. In this configuration the Shutdown (SHDN) pin of the
TP26631 eFuse should be connected to the external 24-V supply so that the board is powered when the 24-V
supply is active.
The Digital IO voltage level of 3.3 V is used for the signals between the LaunchPad and BOOSTXL-IOLINKM-8
boards. The LMR36503 DC-DC stepdown buck converter can be used to create the 3V3 supply rail from the 24V
rail controlled by the eFuse. However, it is possible to disable the LMR36503 and directly use the 3.3-V supply
rail from the LaunchPad with a jumper configuration.
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2.2 Power Configuration Headers
The board has three headers used in the power supply configuration shown in Figure 2-1, and the shunt jumpers
should be applied before power is applied to the board.
23
1
Figure 2-1. Power Configuration Headers
1. Header J8 is used to configure the TP26631 eFuse Shutdown (SHDN) pin configuration. Placing the
shunt jumper between the pins labeled “3V3_LP” and “24V_SHDN” disables the 24 V supply rail when
there is no voltage coming from the 3V3_LP (LaunchPad) supply rail. This is the default configuration and
protects the LaunchPad MCU by disabling the BOOSTXL-IOLINKM-8 when the LaunchPad is not properly
powered. Placing the shunt jumper between the pins labeled “24V_SHDN” and “24V_SHDN_PU” connects
the TPS26631 Shutdown (SHDN) pin to the external 24-V supply voltage through a 100 kΩ pullup resistor. In
this configuration, the BOOSTXL-IOLINKM-8 is powered whenever the external 24-V supply is active.
2. Header J9 is connected to the enable pin of the LMR36503 DC-DC stepdown buck converter. Placing a
shunt jumper on this header disables the converter when the 3V3 rail is powered from the LaunchPad
through the 3V3_LP rail or from an external 3.3-V supply.
3. Header J10 is used to configure which 3.3V source is used to supply the 3V3 rail. Placing a shunt jumper
between the pins labeled “3V3_BUCK” and “3V3” connects the output of the LM36503 DC-DC step down
buck converter to the board’s 3V3 supply rail. This is the default configuration. Placing a shunt jumper
between the pins labeled “3V3” and 3V3_LP” connects the 3V3_LP supply rail coming from the LaunchPad
to the board 3V3 supply rail.
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2.3 BoosterPack Pinout Headers
The BOOSTXL-IOLINKM-8 BoosterPack requires both sets of BoosterPack XL connectors (J1/J3, J2/J4) and
(J5/J7, J6/J8), and uses most of the signals available from the LaunchPad for the application. The eight
standard IO-LINK Port 5-pin M12 connectors must be mounted in a manner that eliminates the ability to stack
another BoosterPack board on top of the BOOSTXL-IOLINKM-8 board. As a result, the standard BoosterPack
XL connectors, with both a socket portion on the bottom of the board and a pin portion on top of the board,
have been replaced with a surface mount socket header type that allows the BoosterPack to mate with the
LaunchPad, but removes the top side pins that conflict with the M12 connectors. The majority of these signals
have also been brought out to test points located on the perimeter of the Boosterpack to maintain access to
these signals during testing. Figure 2-2 shows the header pinout as viewed from the bottom side of the board.
J4J2
4020
3919
3818
3717
3616
3515
3414
33
13
3212
3111
J3 J1
21 1
22 2
23 3
24 4
25 5
26 6
27 7
28 8
29 9
30 10
J6J8
8060
7959
7858
7757
7656
7555
7454
7353
7252
7151
J7 J5
61 41
62 42
63 43
64 44
65 45
66 46
67 47
68 48
69 49
70 50
+3V3
24V_CS_BUF
H_SEH
H_SEL
TX2
H_CS_BUF
TX6
TX8
GPIO_SDA
GPIO_SCL
L_CS_BUF
GND
+5V
TX1
RX8
EN_L+1
+3V3
DI_SCK
RX7
EN8
EN7
EN6
GND
+5V
EN_L+3
EN_L+4
EN_L+5
EN_L+6
FAULT3
FAULT4
FAULT5
FAULT7
FAULT8
EN_L+7
EN_L+8
FAULT6
FAULT1
FAULT2
EN3
EN4
DI_nLD
DI_SOP
EN5
EN2
EN1
GND
DI_nCE
TX4
RX6
TX5
EN_L+2
TX3
RX1
RX2
RX3
RX4
TX7
RX5
GND L_SEH
L_SEL
H_FAULT
L_FAULT
Bottom view
Figure 2-2. LaunchPad-BoosterPack Pinout
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2.4 Push Buttons
The board has one push button shown in Figure 2-3. Due to the limited GPIO pins available between the
LaunchPad and BOOSTXL-IOLINKM-8 boards through the board-to-board mating headers, additional GPIO pins
were created using a TCA6424A I2C-to-GPIO Expander. The MCU firmware should configure these GPIO pins
to the proper direction (Input or Output) as well as the High or Low state through communication on the I2C bus.
Pressing this push button switch S1 labeled “GPIO_RST” reset the TCA6424A registers to their default values. It
is not expected that the user needs to use this push button during normal operation.
Figure 2-3. GPIO Reset Push Button
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2.5 Test Points and Status LEDs
Most of the signals are brought out to test points or status LEDs located on the perimeter of the board. Care
must be taken when working with the test points to avoid shorting two test points together when connecting test
leads, scope probes, and so on. The recommendation is to make the test equipment connections to the test
points before turning on the 24-V power supply.
The test points and status LEDs associated with the 24-V supply voltage are shown in Figure 2-4.
Reference Designator Label Description
TP13 24_VIN External 24-V supply test point
TP16, TP17, TP14 GND Ground test point
TP14 24 V TP26631 eFuse protected 24-V supply for
the 24 V supply rail
TP15 24V_CS_BUF TP26631 eFuse current sense output voltage
D6 24V_PGOOD TP26631 eFuse Power Good LED indicator
for the 24 V supply rail
D8 24V_FAULT TP26631 eFuse Fault LED Indicator for the
24 V supply rail
Figure 2-4. 24-V Test Points and LEDs
The test points and status LEDs associated with the 3.3-V and 5V_LP supply voltages are shown in Figure 2-5.
Reference Designator Label Description
TP12 3V3 Test point for the 3V3 supply rail
TP28, TP32 GND Ground test point
TP20 3V3_PG 3V3_BUCK Power Good LED indicator for
the 3V3 supply rail
D9 3V3 LED indicator for the 3V3 supply rail
TP31 5V_LP Test point for the 5V_LP supply rail (not used
on the board)
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Figure 2-5. 3V3 and 5V_LP Test Points and LEDs
The M12 connector, test points and status LEDs associated with the IO-Link Ports are shown in Figure 2-6. Each
port is identically routed and a detailed view for port 1 is shown in Figure 2-7. The reference designators for the
components associated with the port have the same base reference designator followed by the port number. For
example the reference designators for the eight M12 connectors are J1_[1:8].
Reference Designator Label Description
TP1_[1:8] DI_[1:8] Digital Input test point (24-V signal level)
TP2_[1:8] CQ_[1:8] TIOL112 CQ pin test point (24-V signal level)
TP3_[1:8] EN[1:8] TIOL112 Enable (EN) pin test point (3.3-V
signal level)
TP4_[1:8] TX_[1:8] TIOL112 TX pin test point (3.3-V signal level)
TP5_[1:8] RX_[1:8] TIOL112 RX pin test point (3.3-V signal level)
D1_[1:8] N/A (Green LED) Port status Good LED Indicator
D2_[1:8] N/A (Red LED) Port status Fault LED Indicator
D3_[1:8] N/A (Blue LED) Digital Input LED Indicator
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1 2
3 4
5 6
7 8
Figure 2-6. IO-Link Port M12 Connectors, Test Points, and LEDs
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Figure 2-7. IO-Link Port 1 M12 Connector, Test Points, and LEDs
The test points and status LEDs associated with the TCA6424A I2C-to_GPIO Expander are shown in Figure 2-8.
Reference Designator Label Description
TP8 GPIO_SCL TCA6424A I2C SCL signal test point (3.3-V
signal level)
TP9 GPIO_SDA TCA6424A I2C SDA signal test point (3.3-V
signal level)
TP10 GPIO_RST TCA6424A Reset pin test point (3.3-V signal
level)
TP11 GPIO_INT TCA6424A Interrupt pin test point (3.3-V
signal level)
D5 GPIO_INT TCA6424A Interrupt pin LED Indicator
TP37, TP39 GND Ground test point
Figure 2-8. GPIO Test Points and Interrupt LED
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The test points and status LEDs associated with the SN65HVS883 digital input serializer are shown in Figure
2-9.
Reference Designator Label Description
TP21 DI_SOP SN65HVS883 serial data output (SOP) pin
test point (3.3-V signal level)
TP24 DI_SIP SN65HVS883 serial data input (SIP) pin test
point (3.3-V signal level)
TP25 DI_SCK SN65HVS883 serial clock input (CLK) pin
test point (3.3-V signal level)
TP27 DI_nCE SN65HVS883 clock enable input (nCE) pin
test point (3.3-V signal level)
TP24 DI_nLD SN65HVS883 load pulse input (nLD) pin test
point (3.3-V signal level)
TP23 DI_CHOK SN65HVS883 chip okay output (CHOK) pin
test point (3.3-V signal level)
TP22 5V_OP SN65HVS883 5 V output (5VOP) pin test
point (5-V signal level)
TP38, TP40 GND Ground test point
D10 DI_CHOK (Red LED) SN65HVS883 chip okay output status Fault
LED Indicator
D11 DI_CHOK (Green LED) SN65HVS883 chip okay output status Good
LED Indicator
Figure 2-9. Digital Input Test Points and Status LEDs
The test points associated with the TP26631 eFuse and TPS274160 High Side Switches current sense outputs
digital input serializer are shown in Figure 2-10.
Reference Designator Label Description
TP15 24V_CS_BUF TP26631 eFuse current sense output voltage
(3.3-V max signal level)
TP7 H_CS_BUF TPS274160 High Side Switch current sense
output voltage for L+[5:8] (3.3-V max signal
level)
TP6 L_CS_BUF TPS274160 High Side Switch current sense
output voltage for L+[1:4] (3.3-V max signal
level)
TP16, TP18, TP19 Ground test point
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