Texas Instruments AM64 GP EVM Series User manual

User’s Guide
AM64x GP EVM User's Guide
Table of Contents
1 Introduction.............................................................................................................................................................................3
2 Important Usage Notes...........................................................................................................................................................4
2.1 Power-On Usage Note....................................................................................................................................................... 4
3 System Description................................................................................................................................................................ 4
3.1 Key Features......................................................................................................................................................................5
3.2 Functional Block Diagram.................................................................................................................................................. 7
3.3 Power-On/Off Procedures..................................................................................................................................................8
3.3.1 Power-On Procedure...................................................................................................................................................8
3.3.2 Power-Off Procedure...................................................................................................................................................9
3.4 Peripheral and Major Component Description................................................................................................................. 10
3.4.1 Clocking.....................................................................................................................................................................10
3.4.1.1 Ethernet PHY Clock............................................................................................................................................ 10
3.4.1.2 AM64x SoC Clock...............................................................................................................................................10
3.4.1.3 PCIe Clock.......................................................................................................................................................... 10
3.4.2 Reset..........................................................................................................................................................................11
3.4.3 Power........................................................................................................................................................................ 12
3.4.3.1 Power Input.........................................................................................................................................................12
3.4.3.2 Reverse Polarity Protection................................................................................................................................ 12
3.4.3.3 Current Monitoring.............................................................................................................................................. 12
3.4.3.4 Power Supply......................................................................................................................................................13
3.4.3.5 Power Sequencing..............................................................................................................................................15
3.4.3.6 SoC Power..........................................................................................................................................................16
3.4.4 Configuration............................................................................................................................................................. 17
3.4.4.1 Boot Modes.........................................................................................................................................................17
3.4.5 JTAG..........................................................................................................................................................................21
3.4.6 Test Automation.........................................................................................................................................................23
3.4.7 UART Interface..........................................................................................................................................................26
3.4.8 Memory Interfaces.....................................................................................................................................................27
3.4.8.1 DDR4 Interface................................................................................................................................................... 27
3.4.8.2 MMC Interface.................................................................................................................................................... 28
3.4.8.3 OSPI Interface.................................................................................................................................................... 29
3.4.8.4 SPI EEPROM Interface.......................................................................................................................................30
3.4.8.5 Board ID EEPROM Interface.............................................................................................................................. 30
3.4.9 Ethernet Interface...................................................................................................................................................... 31
3.4.9.1 DP83867 PHY Default Configuration..................................................................................................................33
3.4.9.2 DP83869 PHY Default Configuration..................................................................................................................33
3.4.9.3 Ethernet LEDs.....................................................................................................................................................39
3.4.10 Display Interface......................................................................................................................................................40
3.4.11 USB 2.0 Interface.....................................................................................................................................................41
3.4.12 PCIe Interface..........................................................................................................................................................41
3.4.13 High Speed Expansion Interface............................................................................................................................. 43
3.4.14 CAN Interface.......................................................................................................................................................... 47
3.4.15 Interrupt................................................................................................................................................................... 48
3.4.16 ADC Interface.......................................................................................................................................................... 48
3.4.17 Safety Connector.....................................................................................................................................................49
3.4.18 SPI Interface............................................................................................................................................................49
3.4.19 I2C Interface............................................................................................................................................................ 49
3.4.20 FSI Interface............................................................................................................................................................ 52
4 Known Issues and Modifications........................................................................................................................................ 53
4.1 Issue 1 - Embedded XDS110 Connection to AM64x Target in CCS................................................................................ 53
4.2 Issue 2 - MDIO Ethernet PHY Communications.............................................................................................................. 55
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5 References............................................................................................................................................................................ 55
6 Revision History................................................................................................................................................................... 55
List of Figures
Figure 3-1. Top View of General Processor Board...................................................................................................................... 4
Figure 3-2. Bottom View of General Processor Board.................................................................................................................5
Figure 3-3. General Processor Board Functional Block Diagram................................................................................................7
Figure 3-4. AM64x GP EVM Clock Tree....................................................................................................................................10
Figure 3-5. Overall Reset Architecture of the AM64x EVM........................................................................................................11
Figure 3-6. Power Good LEDs...................................................................................................................................................14
Figure 3-7. Power ON and OFF Sequencing.............................................................................................................................15
Figure 3-8. Core Supply and Array Core Supply Options..........................................................................................................16
Figure 3-9. AM64x GP EVM Schematic Excerpt, Boot Mode Selection Switches (SW2, SW3)................................................18
Figure 3-10. AM64x GP EVP PCB, Boot Mode Selection Switches (SW2, SW3).....................................................................18
Figure 3-11. JTAG Interface.......................................................................................................................................................22
Figure 3-12. Test Automation Header........................................................................................................................................24
Figure 3-13. UART Interface......................................................................................................................................................26
Figure 3-14. DDR4 Interface......................................................................................................................................................27
Figure 3-15. Micro SD Interface.................................................................................................................................................28
Figure 3-16. eMMC Interface.....................................................................................................................................................29
Figure 3-17. OSPI Interface.......................................................................................................................................................30
Figure 3-18. Ethernet Interface - CPSW Domain...................................................................................................................... 31
Figure 3-19. Ethernet Interface - ICSSG Domain...................................................................................................................... 32
Figure 3-20. Ethernet Interface - CPSW Ethernet Strap Settings..............................................................................................36
Figure 3-21. Ethernet Interface - ICSSG1 Ethernet Strap Settings........................................................................................... 37
Figure 3-22. Ethernet Interface - ICSSG2 Ethernet Strap Settings........................................................................................... 38
Figure 3-23. GP Board Ethernet Interface - LEDs..................................................................................................................... 39
Figure 3-24. USB 2.0 Host Interface..........................................................................................................................................41
Figure 3-25. PCIe Interface....................................................................................................................................................... 42
Figure 3-26. High Speed Expansion Connector........................................................................................................................ 45
Figure 3-27. High Speed Expansion Connector Part 1..............................................................................................................46
Figure 3-28. High Speed Expansion Connector Part 2..............................................................................................................47
Figure 3-29. CAN Interface........................................................................................................................................................48
Figure 3-30. I2C Interfaces and Address Assignment to its Peripherals................................................................................... 51
Figure 3-31. FSI Interface..........................................................................................................................................................52
Figure 4-1. AM64x GP EVM Modification Label Location..........................................................................................................53
Figure 4-2. XDS110 CCS Connection Error Dialog................................................................................................................... 54
Figure 4-3. : XDS110 debug reset utility command-line function...............................................................................................54
List of Tables
Table 3-1. Source Clock Selection for the Clock Buffer............................................................................................................. 10
Table 3-2. VMAIN LED...............................................................................................................................................................12
Table 3-3. INA Devices I2C Slave Address............................................................................................................................... 12
Table 3-4. Power Test Points..................................................................................................................................................... 13
Table 3-5. Power LEDs.............................................................................................................................................................. 14
Table 3-6. SoC Power Supply....................................................................................................................................................16
Table 3-7. BOOTMODE Bits...................................................................................................................................................... 19
Table 3-8. PLL Reference Clock Selection BOOTMODE[2:0]................................................................................................... 19
Table 3-9. Boot Device Selection BOOTMODE[6:3]..................................................................................................................19
Table 3-10. Primary Boot Media Configuration BOOTMODE[9:7]............................................................................................. 20
Table 3-11. Backup Boot Mode Selection BOOTMODE[12:10]................................................................................................. 20
Table 3-12. Backup Boot Media Configuration BOOTMODE[13].............................................................................................. 20
Table 3-13. Selection of HSE Connector and JTAG TRACE Functionality................................................................................ 21
Table 3-14. TI20 Pin Connector (J25) Pin-Out...........................................................................................................................21
Table 3-15. TI 60-Pin Connector (J33) Pin-Out......................................................................................................................... 22
Table 3-16. List of Signals Routed to Test Automation Header................................................................................................. 23
Table 3-17. Test Automation Header (J38) Pin-out....................................................................................................................25
Table 3-18. Board ID Memory Header Information.................................................................................................................... 30
Table 3-19. Default Strap Setting of CPSW Ethernet PHY........................................................................................................ 34
Table 3-20. Default Strap Setting of ICSSG Ethernet PHYs......................................................................................................34
Table 3-21. Display Connector (J36) Pin-Out............................................................................................................................ 40
Table 3-22. PCIe Jumper Options to Enable Root Complex and Endpoint Mode..................................................................... 42
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Table 3-23. PCIe Connector (J27) Pin-out.................................................................................................................................42
Table 3-24. Selection of PRG0 Signals on Application Connector............................................................................................ 43
Table 3-25. CAN (J31 and J32) Pin-out..................................................................................................................................... 47
Table 3-26. ADC Connector (J3) Pin-out................................................................................................................................... 48
Table 3-27. Safety Connector Pinouts....................................................................................................................................... 49
Table 3-28. I2C Test Header (J5) Pin-out.................................................................................................................................. 49
Table 3-29. I2C Test Header (J4) Pin-out.................................................................................................................................. 50
Table 3-30. FSI (J5) Connector Pin-out..................................................................................................................................... 52
Table 4-1. AM64x GP EVM Known Issues and Modifications................................................................................................... 53
Trademarks
Sitara™ and Code Composer Studio™ are trademarks of Texas Instruments.
ARM® and Cortex® are registered trademarks of Arm Limited.
All trademarks are the property of their respective owners.
1 Introduction
The AM64x GP EVM is a standalone test, development, and evaluation module (EVM) that lets developers
evaluate AM64x's functionality and develop prototypes for a variety of applications. The EVM is equipped with
a Sitara™ AM6442 processor along with additional components to allow the user to make use of the various
device interfaces including Industrial Ethernet, standard Ethernet, PCIe, Fast Serial Interface (FSI) and others
to easily create prototypes. An on-board display makes use of AM64x's serial peripheral interface (SPI) ports to
provide the ability for local visual outputs in addition to the LEDs. On-board current measurement capabilities are
available to monitor power consumption for power-conscious applications. The supplied USB cable paired with
embedded emulation logic allows for emulation and debugging using standard development tools such as Code
Composer Studio™, from TI.
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2 Important Usage Notes
2.1 Power-On Usage Note
CAUTION
To avoid high inrush currents and prevent possible damage to the AM64x GP EVM components, the
proper EVM power on and power off procedures are required. For more details, see Section 3.3.
3 System Description
The following sections describe the AM64x GP EVM design. Top-down and bottom-up views of the PCB are
provided in Figure 3-1 and Figure 3-2 for reference to major IC and connector component locations.
Figure 3-1. Top View of General Processor Board
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Figure 3-2. Bottom View of General Processor Board
3.1 Key Features
AM64x System-on-Chip (SoC):
• AM64x combines two instances of Sitara’s gigabit TSN-enabled PRU-ICSSG with up to two ARM® Cortex®-
A53 cores, up to four Cortex-R5F MCUs, and a Cortex-M4F MCU
Memory
• 2GB DDR4 supporting data rate up to 1600MT/s
• 16GB eMMC Flash which can support HS400 speed of operation
• Micro Secure Digital (SD) Card with UHS-1 support
• 1 Kbit Serial Peripheral Interface (SPI) EEPROM
• 512 Mbit OSPI EEPROM
• 1 Mbit Inter-Integrated Circuit (I2C) Boot EEPROM
I/O Interface:
• One CPSW Gigabit Ethernet port and two Industrial Ethernet ports based on the Gigabit Industrial
Communication Subsystem (PRU-ICSS-Gb) paired with Texas Instruments Gigabit Ethernet PHY
• One USB2.0 interface with Micro AB connector
Expansion Bus:
• 10051922-1410ELF - 14-Pin FPC connector to interface with the OSD9616P0992-10 display
• High Speed Expansion (HSE) connector to connect application cards
• 2x5 header - 67997-410HLF FSI connector to connect with the C2000 EVM
• x4 PCIe connector to support 1 lane PCIe Card
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Debug:
• XDS110 On-Board Emulator
• Supports 20-pin JTAG connection from external emulator
• Automatic selection between on-board and external emulator (higher priority)
• Quad port Universal Asynchronous Receiver/Transmitter (UART) to USB circuit over microB USB connector
• Two I2C ports SoC_I2C0 & SoC_I2C1 connected to test headers for slave testing of the AM64x device
• Three Push buttons to generate Interrupts. One for testing MCU and SoC GPIO
Power Supply:
• DC Input: 12V
– The GP EVM implements a center positive 5.5mm x 2.1mm x 9.5mm Barrel Jack.
– Recommended mating connector - CUI In. PP3-002AH. (“tuning fork” style plug recommended to avoid
the possibility of intermittent connections)
– Recommended Power Supply - CUI In. SDI65-12-UD-P5 (adapter cords sold separately).
– Example Adapter Cords:
• CUI In. AC-C7 NA
• Phihong USA AC15WNA
• CUI In. AC-C7 UK
• Status Output: LEDs to indicate power status
• INA devices for current monitoring
Compliance:
• RoHS Compliant
• REACH Compliant
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3.2 Functional Block Diagram
Figure 3-3 shows the functional block diagram of the AM64x GP EVM.
Figure 3-3. General Processor Board Functional Block Diagram
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3.3 Power-On/Off Procedures
Power to the EVM is provided through an external AC/DC converter providing 12 Volt, 5A (max) DC voltage to
the J6 power jack.
TI recommends using the CUI Model Number SD165-12-UD or equivalent AC/DC power converter.
CAUTION
To avoid high inrush currents, and prevent possible damage to the AM64x GP EVM components, the
following EVM power on and power off procedures should be utilized.
3.3.1 Power-On Procedure
1. Place EVM power (SW1) switch in OFF position as shown in the figure
below.
2. Place AM64x boot switch selectors (SW2, SW3) into selected boot mode. For more details, see the
bootmode section.
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3. Attach 12 V AC/DC regulator plug to EVM power jack (J6), but do not power converter from AC power.
4. Apply AC power to AC/DC converter. 12 V power LED (LD6 and LD12) should illuminate.
5. Place EVM power (SW1) switch in ON position as shown below.
6. Visually inspect LED against reference photo above. The following LED should be illuminated:
• LD1, LD2, LD3, LD4, LD6, LD7, LD8, LD9, LD10, LD15, LD24, LD25
3.3.2 Power-Off Procedure
1. Switch EVM power switch (SW1) to OFF position.
2. Disconnect AC power from AC/DC converter.
3. Remove DC power plug from EVM power jack (J6).
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3.4 Peripheral and Major Component Description
The following sections provide an overview of the different interfaces and circuits on the AM64x GP EVM.
3.4.1 Clocking
3.4.1.1 Ethernet PHY Clock
A clock generator of part number CDCLVC1310 is used to drive 25 MHz clock to the Ethernet PHYs.
CDCLVC1310 is a 1:10 LVCMOS clock buffer, which takes 25 MHz crystal/LVCMOS reference input and
provides ten 25 MHz LVCMOS clock outputs. The source for the clock buffer is either the CLKOUT0 pin from
the SoC or a 25 MHz oscillator (ASFLMB-25.000MHZ-LY-T), the selection is made using a set of resistors. This
selection can be made through the select lines of the clock buffer.
1. IN_SEL0, IN_SEL1 = [00] for selecting CLKOUT0.
2. IN_SEL0, IN_SEL1 = [01] for selecting oscillator input which is made as default condition in AM64x EVM.
The resistor termination for single ended Crystal input is provided as per device-specific data sheet.
Table 3-1. Source Clock Selection for the Clock Buffer
IN_SEL1 IN_SEL0 Clock Chosen Mount Unmount
0 0 EXT_REFCLK from SoC R40, R45 R248, R253
1 0 Oscillator input R253, R40 R45, R248
Figure 3-4. AM64x GP EVM Clock Tree
Note
Resistors that are marked with red color box are DNI.
3.4.1.2 AM64x SoC Clock
Crystal of 25 MHz (ABM10W-25.0000MHZ-8-K1Z-T3) is provided on EVM as reference clock for the SoC. An
optional output from the buffer driving the SoC is provided. Selection of clock for SoC is done using resistors. By
default, an output from clock buffer SoC_CLKIN is provided to SoC.
3.4.1.3 PCIe Clock
The PCIe reference clock to the SoC will be provided by the PCIe slot connector when processor is configured
as downstream port and PCIe reference clock from the SoC (SERDES0_REFCLK0) will be provided to the PCIe
slot connector during root complex mode of operation.
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3.4.2 Reset
The SoC has the following resets:
• RESET_REQz is the warm reset input for Main domain.
• RESETSTATz is the warm reset status output for Main domain.
• PORz_OUT is the power ON reset status output from Main and MCU domain.
• MCU_PORz is the power ON / Cold Reset input for MCU and Main domain.
• MCU_RESETz is the Warm Reset input for MCU domain.
• MCU_RESETSTATz is the Warm Reset status output for MCU domain.
The PORz signal is provided by ANDing the two supervisor output and reset from JTAG. This is further
ANDed with CONN_MCU_PORz from safety connector and PCIe_MCU_PORz from PCIe connector to provide
MCU_PORz.
Three push button switches are available to provide reset for MCU_PORz, MCU_RESETz and RESET_REQz.
Warm reset can also be applied through Test automation header or manual reset switches SW4(SoC) and
SW6(MCU).
MCU_PORz input can be applied though switch SW7.
The CONN_MCU_RESETz and CONN_MCU_PORz from the safety connector are routed to MCU_RESETz and
MCU_PORz respectively thereby providing option for safety connector to create a warm reset and a cold reset
as shown in the Figure 3-5.
Most peripheral resets are “ANDED” with the RESETSTATz output from the SoC along with a GPIO control as
shown in Figure 3-5. This ensures that the peripheral reset is asserted until the SoC is out of reset and allows
the AM64x to manually assert reset to the peripheral.
Figure 3-5. Overall Reset Architecture of the AM64x EVM
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3.4.3 Power
3.4.3.1 Power Input
The following sections describe the power distribution network topology that supplies the GP EVM board,
supporting components and reference voltages.
The AM64x GP EVM board includes a power solution based on discrete power supply components. The initial
stage of the power supply will be 12 V from a barrel jack connector with part reference J6. J6 supports 8A
current rating and necessary diodes for reverse polarity protection and voltage surge protection. The 12 V input
(VMAIN) of the EVM that is used to generate all necessary voltages required by the EVM.
A ON/OFF switch with part reference SW1 is provided to turn ON/OFF the EVM by connecting this switch to
Enable pin of LM5140, thereby, allowing the switch to turn on or off the board based on the switch position. The
board is in off condition when switch is grounded position 1-2 and in on condition when the switch is in position
2-3. Additionally GPIO from the test automation header is also connected to the switch to control ON/OFF of the
EVM via the test automation board. A fault indication LED LD5 will be in ON status in case of reverse polarity.
LD6 will be in ON status to indicate VMAIN power good.
Note
The Switch SW1 does not turn of VMAIN. It only disables the VCC_5V0 output of LM5140 from which
all other power supplies are derived.
3.4.3.2 Reverse Polarity Protection
A Schottky barrier rectifier with reference D3 is kept for reverse polarity protection, which has average forward
current: IF(AV) ≤ 15 A, reverse voltage: VR ≤ 45 V. LD6 status will give power polarity.
Table 3-2. VMAIN LED
LED ON Status OFF Status
LD5 Power polarity reversed Power polarity good
LD6 Board Power on Board Power off
3.4.3.3 Current Monitoring
INA226 power monitor devices are used to monitor current and voltage of various power rails of AM65x
processor. The device reports current, voltage and power to AM64x processor through I2C interface. Four
terminal, high precision shunt resistors are provided, and the values are calculated based on load current.
Table 3-3. INA Devices I2C Slave Address
Power Source Supply Net
Slave Address
(IN HEX)
Value of the Shunt Connected
to the Supply Rail
VCC_CORE VDD_CORE 40 2mΩ ±1%
VDD_0V85 VDDAR_CORE 41 10mΩ ± 0.5%
VCC_3V3_SYS SoC_DVDD3V3 4C 10mΩ ± 0.5%
VCC1V8 SoC_DVDD1V8 4B 10mΩ ± 0.5%
VDDA1V8 VDDA_1V8 4E 10mΩ ± 0.5%
VCC1V2_DDR VDD_DDR4 46 10mΩ ± 0.5%
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3.4.3.4 Power Supply
The GP EVM utilizes an array of DC-DC converters to supply the various memories, clocks, SoC and other
components on the card with the necessary voltage and the power required. Table 3-5 gives power-good LEDs
provided on EVM board to give users positive confirmation of the status of output of each supply.
Test points for each power outputs are provided on the EVM Board and are mentioned in the below Table 3-4.
Table 3-4. Power Test Points
Sl.No Power Supply Test Point Voltage
Top Side
1 VMAIN TP81 12 V
2 VCC_5V0 TP18 5 V
3 VCC3V3_PREREG TP12 3.3 V
4 VCC_3V3_SYS TP44 3.3 V
5 VDD_2V5 TP6 2.5 V
6 VDD_1V1 TP28 1.1 V
7 VDDA1V8 TP29 1.8 V
8 VDD_CORE TP14 0.75 V
9 VCC_CORE TP23 0.75 V
10 VDD_0V85 TP8 0.85 V
11 VDDAR_CORE TP10 0.85 V
12 VCC1V2_DDR TP4 1.2 V
13 VDD_2V8 TP99 2.8 V
14 VCC3V3_TA TP96 3.3 V
15 VDD_1V0 TP56 1 V
16 VPP_DDR_2V5 TP47 2.5 V
17 VDDR_VTT TP48 0.6 V
18 VCC1V8 TP51 1.8 V
19 VPP_1V8 TP52 1.8 V
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Table 3-5. Power LEDs
Sl.No Power Supply LED REF
Before SW1 TURN ON
1 VMAIN LD6
2 VCC3V3_TA LD24
After SW1 TURN ON
3 VCC_5V0 LD15
4 VCC3V3_PREREG LD4
5 VCC_3V3_SYS LD9
6 VDD_2V5 LD1
7 VDD_1V1 LD10
8 VDDA1V8 LD8
9 VDD_CORE LD2
10 VCC_CORE LD7
11 VDD_2V8 LD25
12 VCC1V2_DDR LD3
Figure 3-6. Power Good LEDs
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3.4.3.5 Power Sequencing
Figure 3-7 shows the Power Up and Power Down sequence of all the Power supplies present on the EVM
Board.
Figure 3-7. Power ON and OFF Sequencing
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3.4.3.6 SoC Power
The Core voltage of the AM64x SoC can be powered by 0.75 V or 0.8 V or 0.85 V based on
the power optimization requirement. It is recommended to use a single voltage source when the SoC
Core voltage (VDD_CORE) and SoC Array Core Voltage (VDDR_CORE) and other array core voltages
(VDDA_0P85_SERDES0_C, VDDA_0P85_SERDES0, VDDA_0P85_USB0, VDD_DLL_MMC0, VDD_MMC0) is
0.85 V. In cases where the SoC Core voltage is required to be 0.75 V or 0.8 V and SoC Array Core Voltage and
other Array Core voltages is required to be 0.85 V then there needs to be separate voltage supply for the SoC
Core voltage and an separate supply for the SoC Array Core voltages.
This EVM has a provision for providing single voltage supply or different voltage supply to the SoC Core
and SoC Array Core and other Array Core Voltages and based requirement. This can be configured by the
placement of resistors as mentioned in Figure 3-8.
Figure 3-8. Core Supply and Array Core Supply Options
The SoC has different IO groups. Each IO group is powered by specific power supplies as shown in Table 3-6.
Table 3-6. SoC Power Supply
SI.No. Power Supply SoC Supply Rails IO Power Group Power
1 VDDA_CORE VDDA_0P85_SERDES
0
SERDES0 0.85
VDDA_0P85_SERDES
0_C
0.85
VDDA_0P85_USB0 USB0 0.85
VDD_MMC0 MMC0 0.85
2 SoC_DVDD3V3 VDDS_MCU MCU 3.3
VDDA_3P3_USB0 USB0 3.3
VDDSHV0 General 3.3
VDDSHV1 PRG0 3.3
VDDSHV2 PRG1 3.3
VDDSHV3 GPMC 3.3
3 VDDA_1V8_MCU VDDA_MCU MCU 1.8
4 VDDA_MCU_ADC VDDA_ADC ADC0 1.8
5 VDDA_1V8_SERDES VDDA_1P8_SERDES0 SERDES0 1.8
6 VDDA_1V8_USB0 VDDA_1P8_USB0 USB0 1.8
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Table 3-6. SoC Power Supply (continued)
SI.No. Power Supply SoC Supply Rails IO Power Group Power
7 VDDA_1V8 VDDS_OSC OSC0 1.8
VDDA_TEMP_0/1 1.8
VDDA_PLL_0/1/2 1.8
8 VDD_DDR4 VDDS_DDR DDR0 1.2
VDDS_DDR_C 1.2
9 SOC_DVDD1V8 VDDSHV4 FLASH 1.8
VDDS_MMC0 MMC0 1.8
10 VDDSHV_SD_IO VDDSHV5 MMC1 1.8
3.4.4 Configuration
3.4.4.1 Boot Modes
The boot mode for the AM64x EVM is defined by either a bank of switches SW2 and SW3 or by the I2C buffer
(U96) connected to the test automation connector (J38). All the boot mode pins have a weak pull-down resistor
and a switch capable of connecting to a strong pull up resistor. Switch set to “ON” corresponds to logic “HIGH”
while “OFF” corresponds to logic “LOW”.
For a full description of all AM64x SoC supported bootmodes, see the AM64x Sitara™ Processors Data Manual
and AM64x Processors Silicon Revision 1.0 Texas Instruments Families of Products Technical Reference
Manual.
The following boot modes are supported by EVM:
1. OSPI
2. MMC1 - SD Card
3. MMC0 - eMMC installed
4. USB - boot using host mode with bulk storage. USB 2.0 mass storage using FAT16/32 (i.e. thumb drive)
5. USB - device boot DFU
6. UART
7. No-Boot
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AM64x GP EVM User's Guide 17
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Figure 3-9. AM64x GP EVM Schematic Excerpt, Boot Mode Selection Switches (SW2, SW3)
Figure 3-10. AM64x GP EVP PCB, Boot Mode Selection Switches (SW2, SW3)
The BOOTMODE pins provide means to select the boot mode before the device is powered up. They are divided
into the following categories:
Note
The following bitpattern is reversed in the table from the switch order
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Table 3-7. BOOTMODE Bits
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reserv
ed
Reserv
ed
Backup
Boot
Mode
Config
Backup Boot Mode Primary Boot Mode
Config
Primary Boot Mode PLL Config
BOOTMODE[2:0] - Denote system clock frequency for PLL configuration. By default, these bits are set for 25
MHz.
Table 3-8. PLL Reference Clock Selection BOOTMODE[2:0]
SW2.3 SW2.2 SW2.1 PLL REF CLK (MHz)
off off off 19.2
off off on 20
off on off 24
off on on 25
on off off 26
on off on 27
on on off Reserved
on on on No PLL Configuration Done
(slow speed backup)
BOOTMODE[6:3] - This provides primary boot mode configuration to select the requested boot mode after POR,
that is, the peripheral/memory to boot from.
Table 3-9. Boot Device Selection BOOTMODE[6:3]
SW2.7 SW2.6 SW2.5 SW2.4
Primary Boot Device
Selected
off off off off Reserved
off off on on OSPI
off off on off QSPI
off off on on SPI
off on off off Reserved
off on off on Reserved
off on on off I2C
off on on on UART
on off off off MMC/SD Card
on off off on eMMC
on off on off USB
on off on on GPMC NAND
on on off off GPMC NOR
on on off on PCIe
on on on off xSPI
on on on on No-boot / Dev-boot
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AM64x GP EVM User's Guide 19
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BOOTMODE[9:7] - These pins provide optional settings and are used in conjunction with the primary boot
device selected. For more details, see the device-specific TRM.
Table 3-10. Primary Boot Media Configuration BOOTMODE[9:7]
SW3.2 SW3.1 SW2.8 Primary Boot Device
Rsvd Reserved
Rsvd Iclk Csel OSPI
Rsvd Iclk Csel QSPI
Rsvd Mode Csel SPI
Rsvd Rsvd Rsvd Reserved
Rsvd Rsvd Rsvd Reserved
Bus Reset Don't Care Addr I2C
Rsvd Rsvd UART
Port Rsvd Fs/raw MMC / SD Card
Rsvd Rsvd eMMC
Core Volt Mode Lane Swap USB
Rsvd GPMC NAND
Rsvd GPMC NOR
Rsvd Rsvd PCIe
SFDP Read Cmd Mode xSPI
Rsvd Rsvd No-boot / Dev-boot
BOOTMODE[12:10] - Select the backup boot mode, that is, the peripheral/memory to boot from, if primary boot
device failed.
Table 3-11. Backup Boot Mode Selection BOOTMODE[12:10]
SW3.2 SW3.1 SW2.8 Backup Boot Device Selected
off off off None (No backup mode)
off off on USB
off on off Reserved
off on on UART
on off off Reserved
on off on MMC/SD
on on off SPI
on on on I2C
BOOTMODE[13] - These pins provide optional settings and are used in conjunction with the backup boot device
devices. For more details on bit details, see the device-specific TRM. When on, switches SW3.6 sets 1 and,
when off, sets 0.
Table 3-12. Backup Boot Media Configuration BOOTMODE[13]
SW3.6 Boot Device
Rsvd None
Mode USB
Rsvd Reserved
Rsvd UART
Rsvd Reserved
Port MMC/SD
Rsvd SPI
Rsvd I2C
BOOTMODE[14:15] - Reserved
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