Texas Instruments AN-2150 LM3450A User manual

User's Guide
SNVA485B–June 2011–Revised May 2013
AN-2150 LM3450A Evaluation Board
1 Introduction
The LM3450A evaluation board is designed to provide an AC to LED solution for a 30W LED load.
Specifically, it takes an AC mains input and converts it to a constant current output of 700mA for a series
string of 1 to 13 LEDs (maximum LED stack voltage of 45V). There are two assembly versions designed
to operate from two different nominal AC input voltages, 120VAC or 230VAC. .
The board employs a two stage design with an LM3450A flyback primary stage and an LM3409HV
secondary stage. The LM3450A provides an isolated 50V regulated output voltage and a power factor
corrected input current. The LM3409HV uses the 50V flyback output as its input and provides a constant
current of 700mA to the LED load. This two stage design provides excellent line and load regulation as
well as isolation. The board is comprised of two copper layers with components on both sides and an FR4
dielelctric.
The two-stage design has several key advantages over a single stage design including:
• No 120Hz LED current ripple
• Better dimming performance at low dimming levels.
• Better line disturbance rejection
• Better efficiency using small LED stack voltages
2 Specifications
120VAC 30W Version
• Input Voltage Range: VIN = 90VAC – 135VAC
• Regulated Flyback Output Voltage: VOUT = 50V
• Maximum LED Stack Voltage: VLED < 45V
• Regulated LED Current: ILED = 700mA
230VAC 30W Version
• Input Voltage Range: VIN = 180VAC – 265VAC
• Regulated Flyback Output Voltage: VOUT = 50V
• Maximum LED Stack Voltage: VLED < 45V
• Regulated LED Current: ILED = 700mA
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ZCD
GATE
LM3450A
GND
COMP
FB
HOLD
CS
DIM
FLT2
FLT1
PWM
BIAS
RETURN
OPTICAL
ISOLATION
RETURN
EMI FILTER
PWM
AC
INPUT
LED
LOAD
VCC
VAC
ISEN
VREF
VADJ
HOLD
LM3409HV
LED Driver
Specifications www.ti.com
Figure 1. Schematic
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POUT (W)
PF
1.00
0.98
0.96
0.94
0.92
16 20 24 28 32
100 VAC
120 VAC
POUT (W)
PF
1.00
0.98
0.96
0.94
0.92
16 20 24 28 32
200 VAC
230 VAC
POUT (W)
EFFICIENCY (%)
84
82
80
78
76
16 20 24 28 32
100 VAC
120 VAC
POUT (W)
EFFICIENCY (%)
84
82
80
78
76
16 20 24 28 32
200 VAC
230 VAC
www.ti.com Typical Performance
3 Typical Performance
Figure 2. 120V, 30W Version Figure 3. 230V, 30W Version
Efficiency vs. Output Power Efficiency vs. Output Power
Figure 4. 120V, 30W Version Figure 5. 230V, 30W Version
Power Factor vs. Output Power Power Factor vs. Output Power
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0
20
40
60
80
100
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39
AMPLITUDE (mA)
HARMONIC NUMBER
Limits
Measured
0
10
20
30
40
50
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39
AMPLITUDE (mA)
HARMONIC NUMBER
Limits
Measured
AMPLITUDE in dbuV
FREQUENCY
AMPLITUDE in dbuV
FREQUENCY
Conducted EMI Performance www.ti.com
4 Conducted EMI Performance
Figure 6. 120V, 30W Conducted EMI Peak Scan Figure 7. 230V, 30W Conducted EMI Peak Scan
Line and Neutral - CISPR/FCC Class B Quasi Peak and Line and Neutral - CISPR/FCC Class B Quasi Peak and
Average Limits Average Limits
5 THD / Harmonic Performance
Figure 8. 120V, 30W THD Measurements Figure 9. 230V, 30W THD Measurements
EN 61000-3 Class C Limits EN 61000-3 Class C Limits
THD = 6.27% ; Fundamental = 316mA THD = 8.96% ; Fundamental = 167mA
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VCC
VREF
ZCDFLT2
DIM GATE
VAC CS
COMP GND
FB ISEN
HOLDVADJ
FLT1
BIAS
9
10
11
12
13
14
15
16
8
7
6
5
4
3
2
1
www.ti.com LM3450A Pin Descriptions
6 LM3450A Pin Descriptions
Pin Name Description Application Information
Reference Output: Connect directly to VADJ or to resistor
1 VREF 3V Reference divider feeding VADJ and to necessary external circuits.
Analog Dim and Phase Dimming Range Input: Connect
directly to VREF to force standard 70% phase dimming
2 VADJ Analog Adjust range. Connect to resistor divider from VREF to extend
usable range of some phase dimmers or for analog
dimming. Connect to GND for low power mode.
Ramp Comparator Input: Connect a series resistor from
3 FLT2 Filter 2 FLT1 capacitor and a capacitor to GND to establish
second filter pole.
Angle Decoder Output: Connect a series resistor to a
4 FLT1 Filter 1 capacitor to ground to establish first filter pole.
Open Drain PWM Dim Output: Connect to dimming input
5 DIM 500 Hz PWM Output of output stage LED driver (directly or with isolation) to
provide decoded dimming command.
Multiplier and Angle Decoder Input: Connect to resistor
6 VAC Sampled Rectified Line divider from rectified AC line.
Error Amplifier Output and PWM Comparator Input:
7 COMP Compensation Connect a capacitor to GND to set the compensation.
Error Amplifier Inverting Input: Connect to output voltage
via resistor divider to control PFC voltage loop for non-
8 FB Feedback isolated designs. Connect to a 5.11kΩresistor to GND
for isolated designs (bypasses error amplifier). Also
includes over-voltage protection and shutdown modes.
Input Current Sense Non-Inverting Input: Connect to
diode bridge return and resistor to GND to sense input
9 ISEN Input Current Sense current for dynamic hold. Connect a 0.1µF capacitor and
Schottky diode to GND, and a 0.22µF capacitor to
HOLD.
10 GND Power Ground System Ground
MosFET Current Sense Input: Connect to positive
11 CS Current Sense terminal of sense resistor in PFC MosFET source.
Gate Drive Output: Connect to gate of main power
12 GATE Gate Drive MosFET for PFC.Gate Drive Output: Connect to gate of
main power MosFET for PFC.
Power Supply Input: Connect to primary bias supply.
13 VCC Input Supply Connect a 0.1µF bypass capacitor to ground.
Demagnetization Sense Input: Connect a resistor to
14 ZCD Zero Crossing Detector transformer/inductor winding to detect when all energy
has been transferred.
Open Drain Dynamic Hold Input: Connect to holding
15 HOLD Dynamic Hold resistor which is connected to source of passFET.
5
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UVLO
1
CSP
2
VIN
3
4
8
COFF 7
EN
6
CSN
5
9
10
GND PGATE
DAP
VCC
IADJ
LM3409HV Pin Descriptions www.ti.com
Pin Name Description Application Information
Pre-regulator Gate Bias Output: Connect to gate of
16 BIAS Pre-regulator Gate Bias passFET and to resistor to rectified AC (drain of
passFET) to aid with startup.
7 LM3409HV Pin Descriptions
Pin Name Description Application Information
Connect to a resistor divider from VIN. UVLO threshold is
1 UVLO Input Under Voltage Lock-out 1.24V and hysteresis is provided by a 22µA current
source.
Apply a voltage between 0 - 1.24V, or connect a resistor
2 IADJ Analog LED Current Adjust from this pin to GND, to set the current sense threshold
voltage.
Apply a voltage >1.6V to enable device, a PWM signal
3 EN Logic Level Enable to dim, or a voltage <0.6V for low power shutdown.
Connect an external resistor from VOto this pin, and a
4 COFF Off-time programming capacitor from this pin to GND to set the off-time.
5 GND Power Ground Connect to the system ground.
6 PGATE Gate Drive Connect to the gate of the external PFET.
7 CSN Negative Current Sense Connect to the negative side of the sense resistor.
Connect to the positive side of the sense resistor (also
8 CSP Positive Current Sense connected to VIN).
Connect at least a 1 µF ceramic capacitor from this pin
9 VCC VIN-referenced Linear Regulator Output to CSN. The regulator provides power for P-FET drive.
10 VIN Input Voltage Connect to the input voltage.
Connect to pin 5 (GND). Place 4-6 vias from DAP to
DAP DAP Thermal PAD on bottom of IC bottom layer GND plane.
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ZCD
GATE
LM3450A
VCC
GND
COMP
FB
HOLD
VAC
VADJ
CS
DIM
FLT2
FLT1
ISEN
PWM
VREF BIAS
IADJ
EN
CSN
LM3409HV
UVLO
VCC
COFF
GND
CSP
PGATE
DAP
VIN
VOUT
PWM
VOP1 VOP2
RETURN
RETURN
VLED
LMV431
OPTO1
OPTO2
VOP2
VOP1
VPOP2
VOUT
EMI
FILTER
CONTROL
FEEDBACK
SECONDARY
LED DRIVER
DIMMING
VREF +
-
AC
MAINS
LED
LOAD
Q1
Q3
D10
D23
D8
D9 D4
C8
C9
C30
C7
C1
C2
C3
C66
C26
C11
C13
C4
C5
D5
D1
C42
C44 D16
C43
C17
C18
C24 C23
D17
C22
L1
L2
T1
R8
R9
R56
R2
R3
R47
D6
R5
R7
R17
R23
R24
R25
R26
R29
R32
R38
R30
R31
R34
R36
R70
R77 R72
R81
R16
R71
R84
R65
R66
R83
R58
R1
C35
C34
C38 C36
C39
C37
C47
D15
D13
D14
D22
D11D12
Q7 L3
Q6
Q2
R57
HOLD
VLED
R39
D7
D2
D3
U9
U8
U10
U1
U11
VPOP2
VCC
R18
Q8
D18
C21
C46
L4
VCC VADJ
COMPBIAS
D21
D24
R20
Q4
R21
SOFTSTART
C12
D20
THERMAL
PROTECT
R10
R12
R14
R15
AUX R6
AUX
R11
www.ti.com Simplified Evaluation Board Schematic
8 Simplified Evaluation Board Schematic
Figure 10. Simplified Evaluation Board Schematic
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VREF +
-
LM3450A FLYBACK
+
VREF +
-
EMI + BRIDGE LM3409HV BUCK
Design Information www.ti.com
9 Design Information
The following section explains how to design using the LM3450A power factor controller and phase
dimming decoder. Refer to AN-1953 LM3409HV Evaluation Board (SNVA390) for a detailed design
procedure of the LM3409HV secondary stage and to the LM3450/A LED Drivers with Active Power Factor
Correction & Phase Dimming Decoder (SNVAS681) data sheet for specific details regarding the function
of the LM3450A device. All reference designators refer to the Simplified Evaluation Board Schematic. Note
that parallel and series resistances are combined in one schematic symbol for simplification. To improve
readability of this design document, each subsection is followed by a list of Definitions for new terms used
in the calculations. Section 11, showing all components and connectors, is found at the end of this
document as well as a Bill of Materials for each assembly version.
Figure 11. Two-Stage PFC LED Driver
9.1 1ST Stage - CRM Flyback
The first stage of the evaluation board shown in Figure 11 is a critical conduction mode (CRM) flyback
converter controlled with the LM3450A. CRM converters operate at the boundary of continuous conduction
mode (CCM) and discontinuous conduction mode (DCM). CRM is implemented by turning on the main
switching FET (Q3) until the primary current rises to a peak threshold. Q3 is then turned off and the
current falls until a zero crossing is detected. At this point, Q3 is turned on and the cycle repeats.
In the CRM flyback PFC application, the rectified AC input is fed forward to the control loop, yielding a
sinusoidal peak current threshold. This peak threshold creates a sinusoidal primary peak current envelope
IP-pk as shown in Figure 12. The secondary peak current envelope IS-pk will simply be a scaled version of
the primary according to the turns ratio of the transformer. Assuming good attenuation of the switching
ripple via the EMI filter, the average input current IIN(t), shown in red, can also be approximated as a
sinusoid. Since the input current has the same shape and phase as the input voltage, high power factor
(PF) can easily be achieved.
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IIN-PK
IP-PK
IS-PK
t
i
tON TSW
www.ti.com Design Information
Figure 12. CRM Flyback Current Waveforms
The input current shaping happens instantly in CRM due to the feed-forward mechanism; however, the
converter must also regulate the flyback output voltage with a traditional feedback loop. This is
accomplished with a narrow bandwidth error amplifier coupled with energy storage capacitance at the
output to limit the twice line frequency ripple. The output of the error amplifier is multiplied with the scaled
rectified AC voltage to achieve both input current shaping and output voltage regulation. Refer to the
datasheet for a more detailed explanation of the power factor controller.
The LM3450A also has a phase decoder that interprets the phase dimming angle and maps it to a 500Hz
PWM open-drain output at the DIM pin. This signal is directly connected to an opto-isolator to send across
the isolation boundary to the second stage LED driver. In addition, the LM3450A provides a dynamic hold
circuit to ensure that the holding current requirement is satisfied in forward phase dimmers. Refer to the
datasheet for a more detailed explanation of the phase dimmer decoder.
9.2 2ND Stage - Buck LED Driver
The second stage of the evaluation board is a buck LED driver controlled with the LM3409HV. The input
to this stage is the flyback output voltage and the output is a regulated constant current of 700mA to a
stack of <45V of LEDs. The LM3409HV is a hysteretic PFET controller using peak current detection and a
constant off-timer to provide regulated LED current with a constant switching frequency ripple. Coupled
with the flyback energy storage capacitance, the LM3409HV is able to remove all 120HZ ripple content
from the LED output. The 500Hz PWM signal from the first stage is used as the dimming input to the
LM3409HV. The output of the opto-isolator is connected directly to the EN pin of the LM3409HV to provide
a PWM dimmed LED current according to the detected phase angle at the primary.
The LM3409HV design is not included in this document. Refer to AN-1953 for a detialed design
procedure. The specifications for the second stage are:
• Nominal Input Voltage = 50V
• Regulated LED Current = 700mA
• Nominal LED Stack Voltage = 45V
• Switching Frequency at Nominal Input = 100kHz
• Inductor/LED Current Ripple = 115mA
9.3 CRM Flyback Converter
Operating Points
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Design Information www.ti.com
The AC mains voltage, at the line frequency fL, is assumed to be perfectly sinusoidal and the diode bridge
ideal. This yields a perfect rectified sinusoid at the input to the flyback. The input voltage Vin(t) is defined in
terms of the peak input voltage:
(1)
The controller and the transformer are also assumed to be ideal. These assumptions yield a sinusoidal
peak primary current envelope IP-pk(t) and peak secondary current envelope IS-pk(t) as shown in Figure 12.
Both are defined in terms of the peak primary current:
(2)
The output voltage reflected to the primary is defined:
(3)
CRM control yields a variable duty cycle over a single line cycle with a minimum occurring at the peak
input voltage:
(4)
The resulting sinusoidal average input current Iin(t), shown in Figure 12, is approximated as the average of
each triangular current pulse during a switching period. The peak input current occurs at the peak primary
current:
(5)
Turns Ratio
The first thing to decide with an isolated design is the desired transformer turns ratio. This should be
based on the specified output voltage and the maximum peak input voltage. Frequently the MosFET is
already chosen for a design, given its cost and availability. With a desired MosFET voltage, the maximum
reflected voltage at the primary is calculated:
(6)
Generally, an integer turns ratio is selected to achieve a reflected voltage at or below the defined
maximum:
(7)
Switching MosFET
The main switching MosFET (Q3) can be sized as desired; to block the maximum drain-to-source voltage,
operate at the maximum RMS current, and dissipate the maximum power:
(8)
The peak current limit should be at least 25% higher than the maximum peak input current:
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