Texas Instruments AN-2150 LM3450A User manual

User's Guide
SNVA485B–June 2011–Revised May 2013
AN-2150 LM3450A Evaluation Board
1 Introduction
The LM3450A evaluation board is designed to provide an AC to LED solution for a 30W LED load.
Specifically, it takes an AC mains input and converts it to a constant current output of 700mA for a series
string of 1 to 13 LEDs (maximum LED stack voltage of 45V). There are two assembly versions designed
to operate from two different nominal AC input voltages, 120VAC or 230VAC. .
The board employs a two stage design with an LM3450A flyback primary stage and an LM3409HV
secondary stage. The LM3450A provides an isolated 50V regulated output voltage and a power factor
corrected input current. The LM3409HV uses the 50V flyback output as its input and provides a constant
current of 700mA to the LED load. This two stage design provides excellent line and load regulation as
well as isolation. The board is comprised of two copper layers with components on both sides and an FR4
dielelctric.
The two-stage design has several key advantages over a single stage design including:
• No 120Hz LED current ripple
• Better dimming performance at low dimming levels.
• Better line disturbance rejection
• Better efficiency using small LED stack voltages
2 Specifications
120VAC 30W Version
• Input Voltage Range: VIN = 90VAC – 135VAC
• Regulated Flyback Output Voltage: VOUT = 50V
• Maximum LED Stack Voltage: VLED < 45V
• Regulated LED Current: ILED = 700mA
230VAC 30W Version
• Input Voltage Range: VIN = 180VAC – 265VAC
• Regulated Flyback Output Voltage: VOUT = 50V
• Maximum LED Stack Voltage: VLED < 45V
• Regulated LED Current: ILED = 700mA
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ZCD
GATE
LM3450A
GND
COMP
FB
HOLD
CS
DIM
FLT2
FLT1
PWM
BIAS
RETURN
OPTICAL
ISOLATION
RETURN
EMI FILTER
PWM
AC
INPUT
LED
LOAD
VCC
VAC
ISEN
VREF
VADJ
HOLD
LM3409HV
LED Driver
Specifications www.ti.com
Figure 1. Schematic
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POUT (W)
PF
1.00
0.98
0.96
0.94
0.92
16 20 24 28 32
100 VAC
120 VAC
POUT (W)
PF
1.00
0.98
0.96
0.94
0.92
16 20 24 28 32
200 VAC
230 VAC
POUT (W)
EFFICIENCY (%)
84
82
80
78
76
16 20 24 28 32
100 VAC
120 VAC
POUT (W)
EFFICIENCY (%)
84
82
80
78
76
16 20 24 28 32
200 VAC
230 VAC
www.ti.com Typical Performance
3 Typical Performance
Figure 2. 120V, 30W Version Figure 3. 230V, 30W Version
Efficiency vs. Output Power Efficiency vs. Output Power
Figure 4. 120V, 30W Version Figure 5. 230V, 30W Version
Power Factor vs. Output Power Power Factor vs. Output Power
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0
20
40
60
80
100
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39
AMPLITUDE (mA)
HARMONIC NUMBER
Limits
Measured
0
10
20
30
40
50
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39
AMPLITUDE (mA)
HARMONIC NUMBER
Limits
Measured
AMPLITUDE in dbuV
FREQUENCY
AMPLITUDE in dbuV
FREQUENCY
Conducted EMI Performance www.ti.com
4 Conducted EMI Performance
Figure 6. 120V, 30W Conducted EMI Peak Scan Figure 7. 230V, 30W Conducted EMI Peak Scan
Line and Neutral - CISPR/FCC Class B Quasi Peak and Line and Neutral - CISPR/FCC Class B Quasi Peak and
Average Limits Average Limits
5 THD / Harmonic Performance
Figure 8. 120V, 30W THD Measurements Figure 9. 230V, 30W THD Measurements
EN 61000-3 Class C Limits EN 61000-3 Class C Limits
THD = 6.27% ; Fundamental = 316mA THD = 8.96% ; Fundamental = 167mA
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VCC
VREF
ZCDFLT2
DIM GATE
VAC CS
COMP GND
FB ISEN
HOLDVADJ
FLT1
BIAS
9
10
11
12
13
14
15
16
8
7
6
5
4
3
2
1
www.ti.com LM3450A Pin Descriptions
6 LM3450A Pin Descriptions
Pin Name Description Application Information
Reference Output: Connect directly to VADJ or to resistor
1 VREF 3V Reference divider feeding VADJ and to necessary external circuits.
Analog Dim and Phase Dimming Range Input: Connect
directly to VREF to force standard 70% phase dimming
2 VADJ Analog Adjust range. Connect to resistor divider from VREF to extend
usable range of some phase dimmers or for analog
dimming. Connect to GND for low power mode.
Ramp Comparator Input: Connect a series resistor from
3 FLT2 Filter 2 FLT1 capacitor and a capacitor to GND to establish
second filter pole.
Angle Decoder Output: Connect a series resistor to a
4 FLT1 Filter 1 capacitor to ground to establish first filter pole.
Open Drain PWM Dim Output: Connect to dimming input
5 DIM 500 Hz PWM Output of output stage LED driver (directly or with isolation) to
provide decoded dimming command.
Multiplier and Angle Decoder Input: Connect to resistor
6 VAC Sampled Rectified Line divider from rectified AC line.
Error Amplifier Output and PWM Comparator Input:
7 COMP Compensation Connect a capacitor to GND to set the compensation.
Error Amplifier Inverting Input: Connect to output voltage
via resistor divider to control PFC voltage loop for non-
8 FB Feedback isolated designs. Connect to a 5.11kΩresistor to GND
for isolated designs (bypasses error amplifier). Also
includes over-voltage protection and shutdown modes.
Input Current Sense Non-Inverting Input: Connect to
diode bridge return and resistor to GND to sense input
9 ISEN Input Current Sense current for dynamic hold. Connect a 0.1µF capacitor and
Schottky diode to GND, and a 0.22µF capacitor to
HOLD.
10 GND Power Ground System Ground
MosFET Current Sense Input: Connect to positive
11 CS Current Sense terminal of sense resistor in PFC MosFET source.
Gate Drive Output: Connect to gate of main power
12 GATE Gate Drive MosFET for PFC.Gate Drive Output: Connect to gate of
main power MosFET for PFC.
Power Supply Input: Connect to primary bias supply.
13 VCC Input Supply Connect a 0.1µF bypass capacitor to ground.
Demagnetization Sense Input: Connect a resistor to
14 ZCD Zero Crossing Detector transformer/inductor winding to detect when all energy
has been transferred.
Open Drain Dynamic Hold Input: Connect to holding
15 HOLD Dynamic Hold resistor which is connected to source of passFET.
5
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UVLO
1
CSP
2
VIN
3
4
8
COFF 7
EN
6
CSN
5
9
10
GND PGATE
DAP
VCC
IADJ
LM3409HV Pin Descriptions www.ti.com
Pin Name Description Application Information
Pre-regulator Gate Bias Output: Connect to gate of
16 BIAS Pre-regulator Gate Bias passFET and to resistor to rectified AC (drain of
passFET) to aid with startup.
7 LM3409HV Pin Descriptions
Pin Name Description Application Information
Connect to a resistor divider from VIN. UVLO threshold is
1 UVLO Input Under Voltage Lock-out 1.24V and hysteresis is provided by a 22µA current
source.
Apply a voltage between 0 - 1.24V, or connect a resistor
2 IADJ Analog LED Current Adjust from this pin to GND, to set the current sense threshold
voltage.
Apply a voltage >1.6V to enable device, a PWM signal
3 EN Logic Level Enable to dim, or a voltage <0.6V for low power shutdown.
Connect an external resistor from VOto this pin, and a
4 COFF Off-time programming capacitor from this pin to GND to set the off-time.
5 GND Power Ground Connect to the system ground.
6 PGATE Gate Drive Connect to the gate of the external PFET.
7 CSN Negative Current Sense Connect to the negative side of the sense resistor.
Connect to the positive side of the sense resistor (also
8 CSP Positive Current Sense connected to VIN).
Connect at least a 1 µF ceramic capacitor from this pin
9 VCC VIN-referenced Linear Regulator Output to CSN. The regulator provides power for P-FET drive.
10 VIN Input Voltage Connect to the input voltage.
Connect to pin 5 (GND). Place 4-6 vias from DAP to
DAP DAP Thermal PAD on bottom of IC bottom layer GND plane.
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ZCD
GATE
LM3450A
VCC
GND
COMP
FB
HOLD
VAC
VADJ
CS
DIM
FLT2
FLT1
ISEN
PWM
VREF BIAS
IADJ
EN
CSN
LM3409HV
UVLO
VCC
COFF
GND
CSP
PGATE
DAP
VIN
VOUT
PWM
VOP1 VOP2
RETURN
RETURN
VLED
LMV431
OPTO1
OPTO2
VOP2
VOP1
VPOP2
VOUT
EMI
FILTER
CONTROL
FEEDBACK
SECONDARY
LED DRIVER
DIMMING
VREF +
-
AC
MAINS
LED
LOAD
Q1
Q3
D10
D23
D8
D9 D4
C8
C9
C30
C7
C1
C2
C3
C66
C26
C11
C13
C4
C5
D5
D1
C42
C44 D16
C43
C17
C18
C24 C23
D17
C22
L1
L2
T1
R8
R9
R56
R2
R3
R47
D6
R5
R7
R17
R23
R24
R25
R26
R29
R32
R38
R30
R31
R34
R36
R70
R77 R72
R81
R16
R71
R84
R65
R66
R83
R58
R1
C35
C34
C38 C36
C39
C37
C47
D15
D13
D14
D22
D11D12
Q7 L3
Q6
Q2
R57
HOLD
VLED
R39
D7
D2
D3
U9
U8
U10
U1
U11
VPOP2
VCC
R18
Q8
D18
C21
C46
L4
VCC VADJ
COMPBIAS
D21
D24
R20
Q4
R21
SOFTSTART
C12
D20
THERMAL
PROTECT
R10
R12
R14
R15
AUX R6
AUX
R11
www.ti.com Simplified Evaluation Board Schematic
8 Simplified Evaluation Board Schematic
Figure 10. Simplified Evaluation Board Schematic
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VREF +
-
LM3450A FLYBACK
+
VREF +
-
EMI + BRIDGE LM3409HV BUCK
Design Information www.ti.com
9 Design Information
The following section explains how to design using the LM3450A power factor controller and phase
dimming decoder. Refer to AN-1953 LM3409HV Evaluation Board (SNVA390) for a detailed design
procedure of the LM3409HV secondary stage and to the LM3450/A LED Drivers with Active Power Factor
Correction & Phase Dimming Decoder (SNVAS681) data sheet for specific details regarding the function
of the LM3450A device. All reference designators refer to the Simplified Evaluation Board Schematic. Note
that parallel and series resistances are combined in one schematic symbol for simplification. To improve
readability of this design document, each subsection is followed by a list of Definitions for new terms used
in the calculations. Section 11, showing all components and connectors, is found at the end of this
document as well as a Bill of Materials for each assembly version.
Figure 11. Two-Stage PFC LED Driver
9.1 1ST Stage - CRM Flyback
The first stage of the evaluation board shown in Figure 11 is a critical conduction mode (CRM) flyback
converter controlled with the LM3450A. CRM converters operate at the boundary of continuous conduction
mode (CCM) and discontinuous conduction mode (DCM). CRM is implemented by turning on the main
switching FET (Q3) until the primary current rises to a peak threshold. Q3 is then turned off and the
current falls until a zero crossing is detected. At this point, Q3 is turned on and the cycle repeats.
In the CRM flyback PFC application, the rectified AC input is fed forward to the control loop, yielding a
sinusoidal peak current threshold. This peak threshold creates a sinusoidal primary peak current envelope
IP-pk as shown in Figure 12. The secondary peak current envelope IS-pk will simply be a scaled version of
the primary according to the turns ratio of the transformer. Assuming good attenuation of the switching
ripple via the EMI filter, the average input current IIN(t), shown in red, can also be approximated as a
sinusoid. Since the input current has the same shape and phase as the input voltage, high power factor
(PF) can easily be achieved.
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IIN-PK
IP-PK
IS-PK
t
i
tON TSW
www.ti.com Design Information
Figure 12. CRM Flyback Current Waveforms
The input current shaping happens instantly in CRM due to the feed-forward mechanism; however, the
converter must also regulate the flyback output voltage with a traditional feedback loop. This is
accomplished with a narrow bandwidth error amplifier coupled with energy storage capacitance at the
output to limit the twice line frequency ripple. The output of the error amplifier is multiplied with the scaled
rectified AC voltage to achieve both input current shaping and output voltage regulation. Refer to the
datasheet for a more detailed explanation of the power factor controller.
The LM3450A also has a phase decoder that interprets the phase dimming angle and maps it to a 500Hz
PWM open-drain output at the DIM pin. This signal is directly connected to an opto-isolator to send across
the isolation boundary to the second stage LED driver. In addition, the LM3450A provides a dynamic hold
circuit to ensure that the holding current requirement is satisfied in forward phase dimmers. Refer to the
datasheet for a more detailed explanation of the phase dimmer decoder.
9.2 2ND Stage - Buck LED Driver
The second stage of the evaluation board is a buck LED driver controlled with the LM3409HV. The input
to this stage is the flyback output voltage and the output is a regulated constant current of 700mA to a
stack of <45V of LEDs. The LM3409HV is a hysteretic PFET controller using peak current detection and a
constant off-timer to provide regulated LED current with a constant switching frequency ripple. Coupled
with the flyback energy storage capacitance, the LM3409HV is able to remove all 120HZ ripple content
from the LED output. The 500Hz PWM signal from the first stage is used as the dimming input to the
LM3409HV. The output of the opto-isolator is connected directly to the EN pin of the LM3409HV to provide
a PWM dimmed LED current according to the detected phase angle at the primary.
The LM3409HV design is not included in this document. Refer to AN-1953 for a detialed design
procedure. The specifications for the second stage are:
• Nominal Input Voltage = 50V
• Regulated LED Current = 700mA
• Nominal LED Stack Voltage = 45V
• Switching Frequency at Nominal Input = 100kHz
• Inductor/LED Current Ripple = 115mA
9.3 CRM Flyback Converter
Operating Points
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Design Information www.ti.com
The AC mains voltage, at the line frequency fL, is assumed to be perfectly sinusoidal and the diode bridge
ideal. This yields a perfect rectified sinusoid at the input to the flyback. The input voltage Vin(t) is defined in
terms of the peak input voltage:
(1)
The controller and the transformer are also assumed to be ideal. These assumptions yield a sinusoidal
peak primary current envelope IP-pk(t) and peak secondary current envelope IS-pk(t) as shown in Figure 12.
Both are defined in terms of the peak primary current:
(2)
The output voltage reflected to the primary is defined:
(3)
CRM control yields a variable duty cycle over a single line cycle with a minimum occurring at the peak
input voltage:
(4)
The resulting sinusoidal average input current Iin(t), shown in Figure 12, is approximated as the average of
each triangular current pulse during a switching period. The peak input current occurs at the peak primary
current:
(5)
Turns Ratio
The first thing to decide with an isolated design is the desired transformer turns ratio. This should be
based on the specified output voltage and the maximum peak input voltage. Frequently the MosFET is
already chosen for a design, given its cost and availability. With a desired MosFET voltage, the maximum
reflected voltage at the primary is calculated:
(6)
Generally, an integer turns ratio is selected to achieve a reflected voltage at or below the defined
maximum:
(7)
Switching MosFET
The main switching MosFET (Q3) can be sized as desired; to block the maximum drain-to-source voltage,
operate at the maximum RMS current, and dissipate the maximum power:
(8)
The peak current limit should be at least 25% higher than the maximum peak input current:
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www.ti.com Design Information
(9)
The parallel sense resistor combination (R30||R31) has to dissipate the maximum power:
(10)
Switching Diode
The main switching diode (D10) should be sized to block the maximum reverse voltage , operate at the
maximum average current, and dissipate the maximum power:
(11)
Definitions
n – Primary to Secondary Turns Ratio
VOUT – Regulated Output Voltage
VIN – Nominal AC Input Voltage
VIN-PK – Peak Input Voltage
VIN-PK-MAX – Maximum Peak Input Voltage
IP-PK – Peak Primary Current
IS-PK – Peak Secondary Current
IIN-PK – Peak Input Current
ILIM – Peak Current Limit
DMIN – Minimum Duty Cycle over Line Cycle
VR– Output Voltage Reflected to Primary
VR-MAX – Maximum Tolerable Reflected Voltage
VT-DES-MAX – Maximum Tolerable MosFET Voltage
VT-MAX – Maximum MosFET Blocking Voltage
IT-RMS-MAX – Maximum MosFET RMS Current
IT-PK-MAX – Maximum MosFET Peak Current
PT-MAX – Maximum MosFET Power Dissipation
VRD-MAX – Maximum Diode Blocking Voltage
ID-MAX – Maximum Diode Average Current
ID-PK-MAX – Maximum Diode Peak Current
PD-MAX – Maximum Diode Power Dissipation
9.4 Transformer
Primary Inductance
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Design Information www.ti.com
The maximum peak input current, occuring at the minimum AC voltage peak, determines the necessary
flyback transformer energy storage. As a general rule of thumb, the desired duty cycle at this worst-case
operating point should be specified near 0.5 to limit large conduction losses associated with high voltage
diodes. The maximum input current can be approximated by the maximum output power, expected
converter efficiency, and minimum input voltage. Note that there is also a 0.85 multiplier to account for the
fact that maximum power with a triac dimmer in-line is demanded at approximately 85% of the full
sinusoidal voltage waveform. Given the desired duty cycle, the maximum peak input current and
corresponding maximum peak primary current can be approximated:
(12)
Using the calculated turns ratio and the desired minimum switching frequency, the minimum necessary
primary inductance is calculated:
(13)
Switching Frequency Range
Given a primary inductance that meets the above constraint, the variable switching frequency has the
following limits:
(14)
Transformer Geometries and Materials
The length of the gap necessary for energy storage in the flyback transformer can be determined
numerically; however, this can lead to non-standard designs. Instead, an appropriate ALcore value
(160nH/turns2 is a good standard value to start with) can be chosen that will imply the gap size. ALis an
industry standard used to define how much inductance, per turns squared, that a given core can provide.
With the initial chosen ALvalue, the number of turns on the primary and secondary are calculated:
(15)
Given the switching frequency range and the maximum output power, a core size can be chosen using the
vendor’s specifications and recommendations. This choice can then be validated by calculating the
maximum operating flux density given the core cross-sectional area of the chosen core.
(16)
With most common core materials, the maximum operating flux density should be set between 300mT and
3400mT. If the calculation is below this range, then ALshould be increased to the next standard value and
the turns and maximum flux density calculations iterated. If the calculation is above this range, then AL
should be decreased to the next standard value and the turns and maximum flux density calculations
iterated.
With the flux density appropriately set, the core material for the chosen core size can be determined using
the vendor’s specifications and recommendations. Note that there are core materials that can tolerate
higher flux densities; however, they are usually more expensive and not always practical for these
designs.
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VOUT
VOP1
VOP2
Rectified AC
BIAS
LM3450A
VCCUV
6V
14V
VCC
VCC UVLO
C42
C44
Q1
R5
R7
Q3
VPOP2
D16
D9
D8
Q8
R18
D18
Q2
D12
R1
Q6
D11R58
C4
C5
C11
C13
D10
D23
D4
T1
R10
R11 R6
C1
www.ti.com Design Information
The rest of the transformer design should be done with the aid of the manufacturer. There are calculated
trade-offs between the different loss mechanisms and safety constraints that determine how well a
transformer performs. This is an iterative process and can ultimately result in the choice of a new core or
switching frequency range. The previous steps should reduce the number of iterations significantly but a
good transformer manufacturer is invaluable for completion of the process.
Definitions
η– Expected converter efficiency
POUT-MAX – Maximum Output Power
VIN-MIN – Minimum RMS AC Line Voltage
VIN-PK-MIN – Minimum Peak Input Voltage
IIN-PK-MAX – Maximum Peak Input Current
IP-PK-MAX – Maximum Peak Primary Current
D@IIN-PK-MAX – Duty Cycle at Maximum Peak Input Current
LP-MIN – Minimum Necessary Primary Inductance
LP– Chosen Primary Inductance
fSW-MIN-DES– Desired Minimum Switching Frequency
fSW-MIN – Minimum Switching Frequency
fSW-MAX – Maximum Switching Frequency
NP– Number of Primary Turns
NS– Number of Secondary Turns
AE-MAX – Core Cross-Sectional Area
BMAX – Maximum Operating Flux Density
AL– Transformer Core Figure of Merit
Figure 13. Bias Circuitry
9.5 Bias Supplies and Capacitances
Bias Supplies
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Design Information www.ti.com
The primary bias supply shown in Figure 13 enables instant turn-on through Q1 while providing an
auxiliary winding for high efficiency steady state operation. The two bias paths are each connected to VCC
through a diode (D8, D9) to ensure the higher of the two is providing VCC current. The LM3450A BIAS pin
helps to ensure that the auxiliary winding is always providing VCC during normal operation.
Since there is optical isolation, a secondary bias supply is also desirable. This is accomplished with
another auxiliary winding, diode (D4), and capacitance (C4, C5) which creates another flyback output that
scales with the regulated output (similar to the auxiliary primary bias winding). To ensure secondary bias
regulation is closely coupled to the regulated flyback output, the output winding is tapped to provide the
secondary bias output.
It is also advantageous to linear regulate down to approximately 9V, from the 12V bias supplies, for every
opto-isolator supply rail (VPOP1, VOP1, VOP2) . This will stabilize the opto-isolator rail over the entire operating
range, preventing noise coupling into COMP and the dimming input of the LM3409.
The primary and secondary bias outputs for both versions of the board are set to 12.5V at the nominal
input voltage. The turns calculations (referred to the output) for the primary auxiliary winding and the tap
point for the secondary winding are:
(17)
The minimum primary bias supply capacitance is calculated, given a minimum VCC ripple specification, to
keep VCC above UVLO at the worst-case current:
(18)
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+
-
5 P$
40 k:
Rectified AC
BIAS
AC AC
LM3450A
C22
C23
R34
R36
R12
R14
R15
Q1
R5
R7
+
-
VSEN
ISEN
HOLD
R45
Q11
R61
D17
R44
NTC
GND
www.ti.com Design Information
Input Capacitance
The input capacitor of the flyback (C1), also called the PFC capacitor, has to be able to provide energy
during the worst-case switching period at the peak of the AC input. C1 should be a high frequency, high
stability capacitor (usually a metallized film capacitor, either polypropylene or polyester) with an AC rating
equal to the maximum input voltage. C1 should also have a DC voltage rating exceeding the maximum
peak input voltage + half of the peak to peak input voltage ripple specification. The minimum required
input capacitance is calculated given the same ripple specification:
(19)
Output Capacitance
Since the LM3450A is a power factor controller, C1 is minimized and the output capacitor (C11) serves as
the main energy storage device. C11 should be a high quality electrolytic capacitor that can tolerate the
large current pulses associated with CRM operation. The voltage rating should be at least 25% greater
than the regulated output voltage and, given the desired voltage ripple, the minimum output capacitance is
calculated:
(20)
Definitions
ΔvIN-PK – Peak Input Voltage Switching Ripple
ΔvOUT – Nominal Output Voltage Ripple
ΔvCC – Nominal Primary Bias Ripple
VCC – Primary Bias Capacitance
nAUX – Output to Auxiliary Turns Ratio
NA– Number of Auxiliary Turns
f2L – Twice Line Frequency
Figure 14. Dynamic Hold Circuit with Thermal Protection
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40 45 50 55 60 65 70
0
6
12
18
24
30
36
MIN OUTPUT POWER (W)
REGULATED MIN INPUT CURRENT (mA)
120VAC
230VAC
Design Information www.ti.com
9.6 Hold Current
Dynamic Hold
The LM3450A regulates the minimum input current with a dynamic hold circuit to ensure the triac holding
current requirement is satisfied. The regulated minimum current is set by choosing the sense resistor
(R34||R36):
(21)
The maximum possible holding current (usually occurs during transients when triac fires) is set by
choosing the hold resistor (R12||R14||R15) between the source of the Q1 and HOLD:
(22)
PassFET
The passFET (Q1) is used in its linear region to stand-off the line voltage from the LM3450A controller.
Both the VCC startup current and the triac holding current are conducted through the device. Since the
holding current is far larger than the startup current and is dynamically adjusted every cycle, it will
dominate the calculations. Given this, Q1 is chosen to block the maximum peak input voltage and conduct
the maximum holding current. The surge handling capability of Q1 is also important and is evaluated by
looking at the safe operating area (SOA) of the device.
Finally, Q1 needs to be able to dissipate the maximum power. Looking at an absolute worst-case
condition for the Q1 (during open load where the converter draws near-zero power), extremely large
power dissipation is required (many Watts). Designing for this case is unrealistic and costly. Instead,
Figure 15 can be used to find the maximum IIN-MIN-REG for the desired minimum output power level. The
minimum output power is defined as the output power that causes the dynamic hold to force
approximately 1W of power dissipation in Q1 (causing approximately 100°C rise in a DPAK). Below the
minimum output power level, Q1 can reach temperatures exceeding 125°C, depending on the conduction
angle, causing potential catastrophic failure. Figure 15 is only a general guideline based on experimental
testing of this evaluation board. Each application will have a different passFET thermal characteristic,
which suggests thermal protection of the passFET is usually necessary.
Figure 15. Output Power Restrictions
(without thermal protection)
16 AN-2150 LM3450A Evaluation Board SNVA485B–June 2011–Revised May 2013
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+
-DIM
VAC
500k
Transition
LM3450A
OPTO2
VPOP2
Rectified AC
ANGLE
DEMOD
SAMPLE/REMAP
DIN
DOUT
DIN DOUT R25 R24
C18 C17
R16
R71
R26
R29
R32
FLT2
FLT1
VADJ
VREF
3V
REF
R23
D22
500 Hz
U8
VOP2
LM3409HV
EN
www.ti.com Design Information
Thermal Protection
Using the previously mentioned design methodology, thermal protection is indeed necessary for the open
load condition and for power levels below the specified operating range shown in Figure 15. The thermal
protection circuit shown in Figure 14 will reduce the maximum holding current when the temperature rises
too high, thus preventing catastrophic failure of Q1. Keep in mind that the thermal foldback does not
prevent the circuit from operating, it simply reduces the amplitude of the dynamic hold. The only negative
effect of the thermal protection is a possible reduction in contrast ratio, meaning the minimum attainable
output current potentially increases as the dynamic hold level decreases.
The thermal protection is accomplished using a PNP transistor (Q11) and a resistor divider comprised of a
fixed resistor (R45) and an NTC thermistor (R44). As Q1 heats up, R44 decreases causing the collector
voltage of Q11 to decrease, effectively reducing the maximum attainable holding current. Placement of
R44 is critical to ensure the best possible thermal coupling to Q1. The drain of Q1 will have the highest
temperature rise but it is at a much higher voltage than the source where R44 is electrically connected.
Because of this, the best placement for R44 is on the other side of the PCB, directly under the drain of
Q1. The dielectric of the PCB provides adequate electrical insulation while yielding the best thermal
coupling. Obviously, R44 placement in potted solutions is much more forgiving. A 10kΩNTC is suggested
for R44 and Q11 can be a basic PNP (i.e. MMBT3906). R45 has to be sized experimentally since the
thermal coupling will vary with each PCB layout. A good starting point for R45 is 15kΩ.
Definitions
IIN-MIN-REG – Regulated Minimum Input Current
IHOLD-MAX – Maximum Hold Current
Figure 16. Dimming Decoder Circuit
9.7 Dimming Decoder
Angle Sense
VAC is a dual input for both the PFC multiplier and the angle decoder. The resistor divider (R26+R29, R32)
should be sized according to the desired angle detect voltage VDET. A general rule of thumb is to set VDET =
VIN-PK/x where x is a value between 4 and 7. R26+R29 should be chosen to be between 1MΩand 2MΩto
limit power dissipation.
(23)
17
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0.0 0.2 0.4 0.6 0.8 1.0
0.0
0.2
0.4
0.6
0.8
1.0
1.2
LM3409HV EN PIN DUTY CYCLE
LM3450A DEMODULATED VAC PIN DUTY CYCLE
1V
0.5V
2V
2.5V
1.5V
VADJ=3V
Design Information www.ti.com
Decoder Mapping
The mapping from the demodulated input (VAC pin of the LM3450A) to output (EN pin of the LM3409HV)
is shown in Figure 17. Varying VADJ will adjust the mapping as desired for the target dimmers. Keep in
mind that the demodulated input angle is a function of the resistor divider at the VAC pin. This means that
the input duty cycle can be shifted by changing VDET within the previously suggested range.
Filters
The filters (FLT1, FLT2) are chosen to provide the desired dimming transition response (how the light
changes during dimmer movement). The filter frequency should be set between 2Hz and 10Hz for best
operation (2Hz has a fade feeling, 10Hz is very snappy). The capacitors (C17, C18) can both be set to
1µF for all designs and given the filter frequencies, the resistors (R24, R25) are calculated:
(24)
Figure 17. Dimming Decoder Mapping
Opto-Isolator
A standard low cost opto-isolator (same type used for feedback of the output) is used to transfer the
dimming command from DIM to the secondary. It needs to be driven with at least 1-2mA of current to
obtain full 70:1 contrast ratio (more current creates faster edges). With VPOP2 = 9V and R16 = 6.04kΩ,
there is > 1mA of drive current. The output of the opto-isolator should be clamped to just above the
dimming input threshold of the secondary driver. This is accomplished with a 1.8V Zener clamp (D22) at
the EN pin of the LM3409HV on the evaluation boards. R71 needs to be large enough that the Zener
clamp is activated whenever the LM3409HV EN pin should be high.
Definitions
VDET – Rectified AC Angle Detect Voltage
fFLT1 – FLT1 frequency
fFLT2 – FLT2 frequency
18 AN-2150 LM3450A Evaluation Board SNVA485B–June 2011–Revised May 2013
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OPTO GAINS & EXTERNAL
ERROR AMPLIFIER FLYBACK POWER STAGE
FEEDBACK GAIN
+
-
LM3450A MULTIPLIER &
SENSING GAINS
VREF VOUT
VCOMP
VFB
ICONT
VE
+-
GCOMP G3450 GVC
HFB
www.ti.com Design Information
Figure 18. Control Loop Block Diagram
9.8 Voltage Control Loop
The CRM topology requires a narrow bandwidth voltage control loop to regulate the output voltage. This
loop needs to be compensated to maintain stability over the desired operating range. The flyback topology
is isolated, therefore the LM3450A internal error amplifier is bypassed and an external secondary side
error amplifier is used instead. The control loop shown in Figure 18 is comprised of the converter control-
to-output transfer function, the compensator transfer function, and all of the other gains in the loop.
The output voltage is sensed with a resistor divider (R81, R72) and regulated to 1.24V using an LMV431:
(25)
The converter control-to-output transfer function can be approximated as a single pole system:
(26)
The feedback gain (HFB) is unity due to the control implementation and the LM3450A device and external
gains are defined:
(27)
A standard PI compensator is used on the secondary to stabilize the system. The error amplifier is
implemented with an LMV431 and a series resistor (R77) and capacitor (C35) in the feedback path as
shown in Figure 19. The output of the LMV431 is tied to the cathode of the opto photo-diode. A resistor
(R70 = 2kΩ) from the anode of the photodiode to the bias rail provides the current path and ultimately the
output voltage swing of the secondary error amplifier. The primary side of the opto is connected directly to
COMP. With the 5kΩinternal pull-up resistor, the maximum current through the primary side of the opto
will be 1mA. A higher frequency roll-off pole is placed on the primary in the form of a capacitor (C24) from
COMP to GND. The resistor divided flyback output voltage is regulated to the 1.24V LMV431 internal
reference. Note the additional soft-start circuit using C34, D13, and D14.
19
SNVA485B–June 2011–Revised May 2013 AN-2150 LM3450A Evaluation Board
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VOUT
VOP1
LMV431
COMP
OPTO
5V
LM3450A
5k
R72
R81
R77
C35
R70
C24
SOFT
START
FB
R38
U10
U9 D13
D14
C34
Design Information www.ti.com
Figure 19. Secondary Error Amplifier Circuit
The compensator transfer function is defined:
(28)
Where the secondary compensator pole is defined:
(29)
And the compensator zero is defined:
(30)
And the primary roll-off pole is defined:
(31)
The resulting control loop gain is
(32)
The compensator design for this system can be complicated; however with some useful assumptions, it
can be simplified. Looking at the total DC gain (G3450xGC0xHFB), the following can be made relatively
constant over all designs:
• R70 = 2kΩ, the 5kΩinternal pull-up, and the 0.55 multiplier gain.
• The opto CTR, though variable over temperature, given a fixed supply rail and a fixed R70 value.
In several cases, the product of two DC gain terms can also be identified as relatively constant over all
designs if all of the previous LM3450A design methodology is observed:
• VINPK and KVare almost exactly inversely proportional (given x remains constant when solving VDET =
VIN/x).
• IP-PK and R30||R31 are closely inversely proportional (given current limit is a constant percentage above
IP-PK ).
Given these relationships and following the complete LM3450A design method, the DC gain should only
vary largely with change in output voltage (directly proportional).
The output pole of the converter on the other hand follows these basic relationships:
20 AN-2150 LM3450A Evaluation Board SNVA485B–June 2011–Revised May 2013
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