User’s Guide
TPS7H3302EVM (LP085)
ABSTRACT
This user’s guide describes operational use of the TPS7H3302EVM evaluation module (EVM) as a reference
design for engineering demonstration and evaluation of the TPS7H3302-SEP, a 3-A sink and source DDR
termination LDO regulator. This user's guide provides details about the EVM, the configuration, schematics, and
bill of materials (BOM).
Table of Contents
1 Introduction.............................................................................................................................................................................2
2 Description.............................................................................................................................................................................. 3
2.1 Related Information............................................................................................................................................................3
2.2 Typical Applications............................................................................................................................................................3
2.3 Features............................................................................................................................................................................. 3
2.4 Performance Specification Summary.................................................................................................................................4
3 Test Setup................................................................................................................................................................................4
3.1 Equipment.......................................................................................................................................................................... 4
3.2 EVM Connectors and Test Points...................................................................................................................................... 5
3.3 Testing Procedure.............................................................................................................................................................. 6
4 Board Layout.........................................................................................................................................................................12
5 Schematic..............................................................................................................................................................................16
6 Bill of Materials..................................................................................................................................................................... 17
7 Related Documentation........................................................................................................................................................18
8 Revision History................................................................................................................................................................... 18
List of Figures
Figure 1-1. TPS7H3302EVM Board (Top View)...........................................................................................................................2
Figure 3-1. DDR3 Bode Plot Iload = 500 mA...............................................................................................................................7
Figure 3-2. DDR3 Bode Plot Iload = 1 A......................................................................................................................................8
Figure 3-3. DDR3 Bode Plot Iload = 3 A......................................................................................................................................8
Figure 3-4. DDR3 Scope Plot Response With Both Sinking and Sourcing Enabled and VDDQSNS Isolated..........................10
Figure 3-5. DDR3 Scope Plot of Response with 1.875 A Sinking Only with Isolated VDDQSNS............................................. 10
Figure 3-6. DDR3 Scope Plot of Response with 1.875 A Sourcing Only with Isolated VDDQSNS........................................... 11
Figure 3-7. DDR3 Scope Plot of Response With 1.875 A Sinking and Sourcing With Non-Isolated VDDQSNS...................... 11
Figure 4-1. Top Overlay............................................................................................................................................................. 12
Figure 4-2. Top Solder............................................................................................................................................................... 12
Figure 4-3. Top Layer.................................................................................................................................................................13
Figure 4-4. Signal and Power Layer 1....................................................................................................................................... 13
Figure 4-5. Signal and Power Layer 2....................................................................................................................................... 14
Figure 4-6. Bottom Layer........................................................................................................................................................... 14
Figure 4-7. Bottom Solder..........................................................................................................................................................15
Figure 5-1. LP085B Schematic..................................................................................................................................................16
List of Tables
Table 2-1. Performance Specification Summary..........................................................................................................................4
Table 3-1. Connectors and Test Points........................................................................................................................................ 5
Table 3-2. I/O Voltage Measurement Test Points.........................................................................................................................6
Table 6-1. Bill of Materials..........................................................................................................................................................17
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SLVUCK2A – JANUARY 2023 – REVISED APRIL 2023
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