2.4.5 Helpful Tips
1. The leads and cables to the various power supplies, batteries and loads have resistance. The current meters
also have series resistance. The charger dynamically reduces charge current depending on the voltage
sensed at its VBUS pin (using the VINDPM feature), BAT pin (as part of normal termination), and TS pin
(through its battery temperature monitoring feature via battery thermistor). Therefore, voltmeters must be
used to measure the voltage as close to the IC pins as possible instead of relying on the digital readouts of
the power supply. If a battery thermistor is not available, that shunts JP11 and JP13 are in place.
2. When using a source meter that can source and sink current as your battery simulator, TI highly
recommends adding a large (>=1000+ μF) capacitor at the EVM BATTERY and GND connector in order
to prevent oscillations at the BAT pin due to mismatched impedances of the charger output and source
meter input within their respective regulation loop bandwidths. Configuring the source meter for 4-wire
sensing eliminates the need for a separate voltmeter to measure the voltage at the BAT pin. When using
4-wire sensing, always ensure that the sensing leads are properly connected in order to prevent accidental
overvoltage by the power leads.
3. For precise measurements of input and output current, especially near termination, the current meter in
series with the battery or battery simulator should not be set to auto-range and may need to be removed
entirely. An alternate method for measuring charge current is to either use an oscilloscope with hall effect
current probe or by a differential voltage measurement across the relevant sensing resistors populated on
the BQ2526xEVM.
3 PCB Layout Guideline
Minimize the switching node rise and fall times for minimum switching loss. Proper layout of the components
minimizing high-frequency current path loop is important to prevent electrical and magnetic field radiation and
high-frequency resonant problems. This PCB layout priority list must be followed in the order presented for
proper layout:
1. For lowest switching noise during forward/charge mode, place the decoupling PMID capacitor and then bulk
PMID capacitor positive terminals as close as possible to PMID pin. Place the capacitor ground terminal
close to the GND pin using the shortest copper trace connection or GND plane on the same layer as the IC.
2. For lowest switching noise during reverse/OTG mode, place the SYS output capacitors' positive terminals
near the SYS pin. The capacitors' ground terminals must be via'd down through multiple vias to an all ground
internal layer that returns to IC GND pin through multiple vias under the IC.
3. Since REGN powers the internal gate drivers, place the REGN capacitor positive terminal close to REGN pin
to minimize switching noise. The capacitor's ground terminal must be via'd down through multiple vias to an
all ground internal layer that returns to IC GND pin through multiple vias under the IC.
4. Place the VBUS and BAT capacitors' positive terminals as close to the VBUS and BAT pins as possible.
The capacitors' ground terminals must be via'd down through multiple vias to an all ground internal layer that
returns to IC GND pin through multiple vias under the IC.
5. Place the inductor input pin near the positive terminal of the SYS pin capacitors. Due to the PMID capacitor
placement requirements, the inductor's switching node terminal must be via'd down with multiple via's to
a second internal layer with a wide trace that returns to the SW pin with multiple vias. Using multiple
vias ensures that the via's additional resistance is negligible compared to the inductor's dc resistance and
therefore does not impact efficiency. The vias additional series inductance is negligible compared to the
inductor's inductance.
6. Place the BTST capacitor on the opposite side from the IC using vias to connect to the BTST pin and SW
node.
7. A separate analog GND plane for non-power related resistors and capacitors is not required if those
components are placed away from the power components traces and planes.
8. Ensure that the I2C SDA and SCL lines are routed away from the SW node.
Additionally, it is important that the PCB footprint and solder mask cover the entire length of each of the pins.
GND, SW, PMID, SYS and BAT pins extend further into the package than the other pins. Using the entire length
of these pins reduces parasitic resistance and increases thermal conductivity from the package into the board.
See the EVM design for the recommended component placement with trace and via locations.
www.ti.com Testing Procedures
SLUUCQ9 – JANUARY 2023
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BQ25628 and BQ25629 Evaluation Modules 9
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