Texas Instruments DP83TG721EVM-MC User manual

User’s Guide
DP83TG721EVM-MC User Guide
ABSTRACT
This User’s Guide discusses how to properly operate and configure the DP83TG721 Media Converter EVM. For
layout, schematic files, and Bill of Materials, see the DP83TG721 product page.
DP83TG721EVM-MC
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Note
TI is transitioning to use more inclusive terminology. Some language may be different than what you
would expect to see for certain technology areas.
Table of Contents
1 Introduction.............................................................................................................................................................................3
1.1 Key Features......................................................................................................................................................................3
1.2 Board Connections.............................................................................................................................................................4
2 Operation - Quick Start...........................................................................................................................................................6
3 Further Configuration.............................................................................................................................................................7
3.1 Power Supply..................................................................................................................................................................... 7
3.2 MSP Connection................................................................................................................................................................ 8
3.3 Master and Slave Mode Selection..................................................................................................................................... 8
3.4 Wake Selection.................................................................................................................................................................. 9
3.5 Autonomous/Managed Mode Selection........................................................................................................................... 10
3.6 LED Indication.................................................................................................................................................................. 11
3.7 Clock Configuration..........................................................................................................................................................12
3.8 MDI Connection............................................................................................................................................................... 13
4 Schematic, Board Layout, and Bill of Materials.................................................................................................................14
4.1 Schematic........................................................................................................................................................................ 15
Trademarks
All trademarks are the property of their respective owners.
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1 Introduction
The DP83TG721EVM-MC supports 1000 Mbps speed and is IEEE 802.3bp compliant. There is an on-board
MSP430F5529 for use with the USB2MDIO graphical user interface tool. The DP83867 is provided for copper
(1000BASE-T) support using the RGMII MAC Interface.
1.1 Key Features
• Media Converter: 1000BASE-T to 1000BASE-T1
• IEEE802.3bp Compliant
• RGMII Back-to-Back Configuration
• On-board MSP430F5529
– USB2MDIO Support
• Status LEDs
– Link
– Link + Activity
– Power-On
VBAT
5-20V
DC-DC 5V
DP83TG721
VDDIO VDDA VDD1P1 VSLEEP
DP83867
VDD1P0 VDDA2P5 VDDIO
3.3V LDO
RJ-45 w/
Integrated
Magnetics CMC Automotive
Connector
MSP430F5529 USB
MDIO
MDC
RGMII
3.3V LDO 3.3V LDO
1.1V LDO
3.3V LDO
VDDA1P8
2.5V LDO1.8V LDO1.0V LDO
USB 5V
60 pin
connector
bridges
two sides
Industrial side Automo  ve side
5V
MDIO
MDC
Figure 1-1. DP83TG721EVM-MC Block Diagram
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1.2 Board Connections
Figure 1-2. Board Connections
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Number Description
1MATEnet automotive Ethernet connector
2RJ45 Ethernet connector
35-20V input
4Micro-USB for power and data
560 pin media conversion connector
6Reset button
7 SMA MDI connection for DP83TG721
8External clock-in for DP83TG721
9DP83867 CLKOUT
10 DP83TG721 CLKOUT
11 Break-here line
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2 Operation - Quick Start
1. Break the PCB along the perforated line and connect the two halves through the 60 pin connectors as shown
in Figure 2-1.
Figure 2-1. DP83TG721EVM Media Conversion
2. Connect a micro USB cable from J1 to any windows laptop or PC.
3. Open USB-2-MDIO on the laptop or PC.
4. Read register 0x0003 on both on-board PHYs and ensure the values match Table 2-1.
Table 2-1. Default Register 0x3 Values
Register 0x3 Value
DP83TG721 (PHY_ID = 0) 0xA290
DP83867 (PHY_ID = 9) 0xA231
5. Load initialization script given in SNLA422. See section 2.3.4 of USB-2-MDIO User's Guide for how to make
and load scripts.
6. The board is now ready to connect to a link partner. If you wish, perform steps 1-5 on an additional
DP83TG721EVM-MC and connect the boards together using an automotive Ethernet cable with MATEnet
connectors.
a. Ensure that master/slave selection is configured appropriately (Through register write or bootstrap).
b. Verify the power and link LEDs are on (see section Section 3.6).
7. For media conversion, connect an Ethernet cable to the RJ45 port.
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3 Further Configuration
3.1 Power Supply
• The EVM can be powered directly through the micro-USB port.
• Alternately, connect 5-20V to TP7 and GND to TP8, or use the terminal block J28.
Figure 3-1. Power Supply Connection
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3.2 MSP Connection
• By default, the on-board MSP430 is connected to both PHYs for MDC/MDIO communication.
• To use an external MDC/MDIO connection, remove jumpers on J10, J13, J15 and connect external
connections to pin 2 of each header.
Figure 3-2. MDC/MDIO Connections
3.3 Master and Slave Mode Selection
• Master Mode: Place shunt across pins 2 and 3 of J12.
• Slave Mode: Place shunt across pins 1 and 2 of J12.
Figure 3-3. Master/Slave Jumper
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3.4 Wake Selection
• Wake High: Place shunt across pins 1 and 2 of J4.
• Wake Low: Place shunt across pin 2 of J4 and J7.
Figure 3-4. Wake Jumper
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3.5 Autonomous/Managed Mode Selection
The DP83TG721 has two modes of operation, autonomous and managed, to select the behavior immediately
after power up. In autonomous mode, the PHY automatically transitions from Standby to the Normal state
upon POR completion. In managed operation, the PHY only transitions to the Normal state after register write
(<0x018C> = 0x0001). To select the mode, place a shunt on header J5 in the position indicated in Figure 3-5.
Figure 3-5. Autonomous/Managed Mode Selection
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3.6 LED Indication
• LED_0 (LD3 or LD4) and LED_1 (LD1 or LD2) will illuminate when a link is successfully established on the
DP83TG721.
• LED_1 (LD1 or LD2) will blink for TX/RX activity.
• LEDs on the RJ45 connector will illuminate when a link is successfully established on the DP83867.
Figure 3-6. LED Indicators
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3.7 Clock Configuration
• On-board Clock
– The on-board crystal is enabled by default.
• External Clock
– Remove R60 and R61.
– Populate R56 with a 0 ohm resistor.
– Connect external clock source to J16.
Figure 3-7. Clock Reference
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3.8 MDI Connection
By default, the DP83TG721 TRD_P and TRD_M pins are routed to the MATEnet automotive Ethernet connector.
If desired, these signals can be routed to SMA connectors instead. The steps to do this follow:
1. Remove R39, R42.
2. Place 0 ohm resistors on R35, R46.
Figure 3-8. MDI Connection Selection
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4 Schematic, Board Layout, and Bill of Materials
These files can be found on the DP83TG721 product page under "Design Files". Schematics are also shown below.
Schematic, Board Layout, and Bill of Materials www.ti.com
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4.1 Schematic
MDI
DP83TG721
GND
GND
VDDIO_dev_1
GND
VDDIO_dev_2
GND
VDDA_dev
VDD1p0_dev_1
GND
VDD1p0_dev_2
0
R54
0
R59
0
R62
0
R65
2.2uF
C25
2.2uF
C28
2.2uF
C33
2.2uF
C36
2.2uF
C39
0.01uF
C27
0.01uF
C30
0.01uF
C35
0.01uF
C38
0.01uF
C41
Supply Decoupling
VDDIO
VDDA
1V0
INT_N
2.2k
R34
VDDIO
MDIO
2.2k
R50
VDDIO
SMI
0.1uF
C26
0.1uF
C29
0.1uF
C34
0.1uF
C37
0.1uF
C40
L3
BLM18KG601SN1D
L4
BLM18KG601SN1D
VSLEEP
0
R66
1µF
C42
0.1uF
C43
GND
TRD3_N
TRD3_P
TRD_N
TRD_P TRD1_P
TRD1_N
GND721_CONN
GND
GND
GND721_CONN
GND721_CONN
22
1
1
ESD401DPYR
D3
2
211
ESD401DPYR
D5
22
1
1
ESD401DPYR
D4
2
211
D6
0.1uF
C18
0.1uF
C20
1.00k
R47
1.00k
R48
100k
R51
4700pF
C22
GND721_CONN
GND
CLKOUT 1
2 3 4 5
J19
901-144-8RFX
1.00k
R68
1.00k
R69
100k
R70
4700pF
C45
GND
SMA MC CLKOUT
WAKE
VSLEEP
0
R32
0
R33
VDDIO
1
2
3
J4
10k
R38
VSLEEP_dev
1
2
3
J5
GND
Green
12
LD1
Green
1 2
LD2
LED_1
VDDIO
LED1
560
R30
560
R36
1
2
3
J12
GND
Green
12
LD3
Green
1 2
LD4
LED_0
VDDIO
LED0
560
R45
560
R52
1 2
J13
1 2
J15
MDC
MDIO MDIO_MSP
MDC_MSP
RX_D2_RX_P
RX_D3_RX_M
TX_D1_TX_P
TX_D0_TX_M
GND
GND
GND
MDC_CnS
MDIO_CnS
RX_D1
RX_D0
RX_CLK
RX_CTRL
TX_CLK
TX_D3
TX_D2
TX_CTRL
RESET_N
INH
WAKE
12
34
56
78
910
1112
1314
1516
1718
1920
2122
2324
2526
2728
2930
3132
3334
3536
3738
3940
4142
4344
4546
4748
4950
5152
5354
5556
5758
5960
MP1
MP2
MP3
MP4
J14
ERF8-030-01-L-D-EM2-TR
3V3
L2
BLM18HE102SN1D
GND
GND GND
XI
22pF
C31
22pF
C32
0
R61
1
34
2G
G
Y2
Clock Reference
XO
0
R56
GND
1
2 3 4 5
J16
GND
1 2
S3
0.1uF
C19
GND
RESET_N
3V3
EXT_CLK
1
2
3
J6
INH
VSLEEP
VDDIO
EN
GND INH EN
0
R63
0
R64
5V
VDDIO_dev_1
VDDA_dev
XO
XI
RESET_N
MDIO
MDC
LED_0
TRD_N
TRD_P
GND
VDDIO_dev_2
VDD1p0_dev_1 WAKE
VDD1p0_dev_2
INT_N
VSLEEP_dev
INH
LED_1
RX_D3_RX_M
RX_D2_RX_P
RX_D1
RX_D0
RX_CTRL
RX_CLK
TX_D3
TX_D2
TX_D1_TX_P
TX_D0_TX_M
VDD1P0
9
VDD1P0
21
VDDA
11
VDDIO
22
VDDIO
34
LED_0/GPIO_0 35
LED_1/GPIO_1 6
TRD_M 13
TRD_P 12
RX_CLK
27 RX_CTRL
15
RX_D0
26 RX_D1
25 RX_D2/RX_P
24 RX_D3/RX_M
23
TX_CLK
28
TX_CTRL
29
TX_D0/TX_M
33 TX_D1/TX_P
32 TX_D2
31 TX_D3
30
INT
2
RESET
3
CLKOUT/GPIO_2 16
EN
17
INH
10
MDC
1MDIO
36
STRP_1
14
VSLEEP
7
WAKE 8
XI 5
XO 4
NC 18
NC 19
NC 20
GND 37
DP83TG721S-Q1
U5
EN_DIV
CLKOUT
STRP_1
100
R60
25V
0.047uF
C44
GND
0
R67
EN
LED_0
LED_1
1 2
J10
GND GND_MSP
5V
1 2
S 1
S 2 S 3
S 4 S 5 S 6
J8
9-2304372-9
TX_CLK
TX_CTRL
TRD2_P
TRD2_N
0
R35
TRD5_N
0
R46
TRD5_P
0
R98
0
R99
MDC
MDIO
0
R57
0
R58
0
R42
0
R39
0.1uF
C89
0.1uF
C90
TRD5_N
TRD5_P
L1
L7
VDDA
1
2
3
J11
OUT 1
DNC
2FB 3
PG 4
DNC
5
DNC
6
DNC
7GND 8
DNC
9
DNC
10
DNC
11
BIAS 12
NR/SS
13
EN
14
IN
15
IN
16
IN
17
GND 18
OUT 19
OUT 20
PAD 21
TPS7A5201QRGRRQ1
U4
GND
1V0
22uF
C23
GND
22uF
C91
12.4k
R43
33.2k
R44
GND
0.01uF
C21
0.01uFC24
GND
10.0k
R101
10uF
C92
GND
VDDA
0
R100
GND
22uF
C93
GND
22uF
C94
INH
22uF
16V
C95
22uF
16V
C96
22uF
16V
C97
GND
GND
GND
TP9
TP10
GND721_CONN
TRD7_N
TRD7_P
0R105
0
R104 TRD7_N
TRD7_P
1
2 3 4
J18
1
2 3 4
J17
2
3 4 5 6
1
P1
E6S204-40MT5-Y
GND
GND
0
R106
0
R107
GND
VDDAU1
U2
Use TPS7A5201WQRTKRQ1 in BOM
GND GND721_CONN
0.01 µF
1kV
C99
10.0k
R110
10.0k
R109
GND GND721_CONN
0.01 µF
1kV
C98
470
R108
TRD8_N
TRD8_P
TRD9_N
TRD9_P
2.49k
R37
2.49k
R31
2.49k
R49
2.49k
R53
1
J3
0
R40
0
R41
1
J7
GND
Figure 4-1. Schematic : DP83TG721
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TARGET_D_N USB_N
TARGET_D_P
GND_MSP
3V3_MSP
RST/SBWTDIO
3V3_MSP
MSP_XOUT2
GND_MSP
GND_MSP
GND_MSP
P1.0
5V_MSP
MSP_XIN2
P1.1
P1.2
GND_MSP
63
1 8
2 7
54
S2
GND_MSP
3V3_MSP
SW4
SW3
SW2
SW1
RST/SBWTDIO
TEST/SBWTCK
GND_MSP
MSP430
SBW
GND_MSPGND_MSPGND_MSP
P1.2
P1.1
P1.0
G
6 5 4
1
2 3
R B
D2
SBW
DIP Switch
RESET
P6.4/CB4/A4 1
P6.5/CB5/A5 2
P6.6/CB6/A6 3
P6.7/CB7/A7 4
P7.0/CB8/A12
5
P7.1/CB9/A13
6
P7.2/CB10/A14
7
P7.3/CB11/A15
8
P5.0/A8/VREF+/VEREF+
9
P5.1/A9/VREF-/VEREF-
10
AVCC1
11
P5.4/XIN
12
P5.5/XOUT
13
AVSS1 14
P8.0 15
P8.1 16
P8.2 17
DVCC1
18 DVSS1 19
VCORE
20
P1.0/TA0CLK/ACLK
21
P1.1/TA0.0
22
P1.2/TA0.1
23
P1.3/TA0.2
24
P1.4/TA0.3
25
P1.5/TA0.4
26
P1.6/TA1CLK/CBOUT
27
P1.7/TA1.0
28
P2.0/TA1.1 29
P2.1/TA1.2 30
P2.2/TA2CLK/SMCLK 31
P2.3/TA2.0 32
P2.4/TA2.1 33
P2.5/TA2.2 34
P2.6/RTCCLK/DMAE0 35
P2.7/UCB0STE/UCA0CLK 36
P3.0/UCB0SIMO/UCB0SDA
37
P3.1/UCB0SOMI/UCB0SCL
38
P3.2/UCB0CLK/UCA0STE
39
P3.3/UCA0TXD/UCA0SIMO
40
P3.4/UCA0RXD/UCA0SOMI
41
P3.5/TB0.5
42
P3.6/TB0.6
43
P3.7/TB0OUTH/SVMOUT
44
P4.0/PM_UCB1STE/PM_UCA1CLK 45
P4.1/PM_UCB1SIMO/PM_UCB1SDA 46
P4.2/PM_UCB1SOMI/PM_UCB1SCL 47
P4.3/PM_UCB1CLK/PM_UCA1STE 48
DVSS2 49 DVCC2
50
P4.4/PM_UCA1TXD/PM_UCA1SIMO 51
P4.5/PM_UCA1RXD/PM_UCA1SOMI 52
P4.6/PM_NONE 53
P4.7/PM_NONE 54
P5.6/TB0.0
55
P5.7/TB0.1
56
P7.4/TB0.2
57
P7.5/TB0.3
58
P7.6/TB0.4
59
P7.7/TB0CLK/MCLK
60
VSSU 61
PU.0/DP 62
PUR 63
PU.1/DM 64
VBUS
65
VUSB
66
V18
67
AVSS2 68
P5.2/XT2IN
69
P5.3/XT2OUT
70
TEST/SBWTCK 71
PJ.0/TDO 72
PJ.1/TDI/TCLK 73
PJ.2/TMS 74
PJ.3/TCK 75
RST/NMI/SBWTDIO 76
P6.0/CB0/A0 77
P6.1/CB1/A1 78
P6.2/CB2/A2 79
P6.3/CB3/A3 80
MSP430F5529IPN
U1
GND_MSP
MDC_MSP
MDIO_MSP
TARGET_D_N
GND_MSP
TARGET_PUR
TARGET_D_P
TEST/SBWTCK
RST/SBWTDIO
27
R1
27
R2
1.40k
R6
1.00M
R7
10uF
C11
0.22uF C10
4.7uF
C9
0.47uF C8
0.22uF
C7
1
34
2G
G
Y1
1 2
3 4
J2
560
R9
560
R10
560
R11
2.2k
R21
2.2k
R22
2.2k
R23
2.2k
R24
S1
47k
R16
SW1
SW2
SW3
SW4
MSP_INT
MSP_RESET
36pF
C6
36pF
C5
GND_MSP GND_MSP
0
R3
0
R8
GND_MSP
10pF
C3
10pF
C4
USB_P
0.1uF
C12
0.1uF
C13
0.1uF
C14
MSP_WAKE
MOD2
MOD1
MOD0
2200pF
C15
10.0k
R12
REV_SEL_0
REV_SEL_1
REV_SEL_2
REV_SEL_3
10.0k
R13
10.0k
R14
10.0k
R15
0R17
0R18
0R19
0R20
GND_MSP
SOFTWARE REV.
3V3_MSP
REV_SEL_0
REV_SEL_1
REV_SEL_2
REV_SEL_3
USB_N
USB_P
GND_MSP
GND_MSP
GND_MSP
MSP USB
5V_MSP
0.1uF
C2
35V
4.7uF
C1
VBUS
1
D-
2
D+
3
ID
4
GND
5
6 7 8
11 10 9
J1
21
D1
CDBA160-HF
0
R4
0
R5
GND_MSP
GND_MSP
GND
GND
Placeholder for Ferrite Bead
0
R102
0
R103
GND_MSP
GND_MSP
GND
GND
Figure 4-2. Schematic : MSP430
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EN 8
VREF_A
2
A1
3
GND 1
B1 6
VREF_B 7
A2
4B2 5
LSF0102DQER
U2
VDDIO
200k
R25
GND_MSP
INT_N
RESET_N
3V3_MSP
RESET INT MSP
0
R26
0
R27
MSP_INT
MSP_RESET
INT_LVL
RESET_LVL
INT_LVL
RESET_LVL
GND_MSP
0.1uF
C16
EN 6
VREF_A
2
A1
3
GND 1
B1 4
VREF_B 5
LSF0101DRYR
U3
VSLEEP
WAKE
GND_MSP
WAKE_LVL
0
R29
WAKE_LVL MSP_WAKE
GND_MSP
0.1uF
C17
200k
R28
3V3_MSP
Wake MSP
FID2
Fiducial
FID1
Fiducial
FID3
Fiducial
721_C&S
B
PCB Number:
PCB Rev:
Printed Circuit Board
Label Assembly Note
ZZ1
This Assembly Note is for PCB labels only
Assembly Note
ZZ2
These assemblies are ESD sensi

ve, ESD precau

ons shall be observed.
Assembly Note
ZZ3
These assemblies must be clean and free from

ux and all contaminants. Use of no clean

ux is not acceptable.
Assembly Note
ZZ4
These assemblies must comply with workmanship standards IPC-A-610 Class 2, unless otherwise speci

ed.
Variant/Label Table
Variant Label Text
001 DP83TG721EVM-MC Revision B
LOGO
PCB
Texas Instruments
LOGO
PCB
FCC disclaimer
LOGO
PCB
Pb-Free Symbol
FID6
Fiducial
FID4
Fiducial
FID5
Fiducial
LOGO
PCB
Texas Instruments
LOGO
PCB
Pb-Free Symbol
MH1
1902C
MH2
1902C
MH3
1902C
MH4
1902C
1
MH1_1
NY PMS 440 0025 PH
GND_H
1
MH2_1
NY PMS 440 0025 PH
GND_H
1
MH3_1
NY PMS 440 0025 PH
GND_H
1
MH4_1
NY PMS 440 0025 PH
GND_H
Figure 4-3. Schematic : MSP430 Reset and Wake
www.ti.com Schematic, Board Layout, and Bill of Materials
SNLU321 – JANUARY 2023
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DP83TG721EVM-MC User Guide 17
Copyright © 2023 Texas Instruments Incorporated

VBAT Supply
TPS7A4701QRGWTQ1
OUT 1
NC 2
SENSE/FB 3
6P4V2
4
6P4V1
5
3P2V
6
GND 7
1P6V
8
0P8V
9
0P4V
10
0P2V
11
0P1V
12
EN
13
NR 14
IN
15
IN
16
NC 17
NC 18
NC 19
OUT 20
PAD 21
U6
GND
0.47uF
C60
GND
10µF
C55
TPS7A4701QRGWTQ1
OUT 1
NC 2
SENSE/FB 3
6P4V2
4
6P4V1
5
3P2V
6
GND 7
1P6V
8
0P8V
9
0P4V
10
0P2V
11
0P1V
12
EN
13
NR 14
IN
15
IN
16
NC 17
NC 18
NC 19
OUT 20
PAD 21
U10
GND
0.47uF
C84
GND
10µF
C77
VDDA_LDO
VDDIO_LDO5V
5V
VDDIO and VDDA
TP5
VDDIO VDDA
GNDGND
Green
12
D8
Green
12
D9
560
R88
560
R87
Power Indica

on
TPS7A4701QRGWTQ1
OUT 1
NC 2
SENSE/FB 3
6P4V2
4
6P4V1
5
3P2V
6
GND 7
1P6V
8
0P8V
9
0P4V
10
0P2V
11
0P1V
12
EN
13
NR 14
IN
15
IN
16
NC 17
NC 18
NC 19
OUT 20
PAD 21
U7
GND
0.47uF
C61
GND
VSLEEP_LDO5V TP2
VSLEEP and MSP
60V D7
GND
VBAT Connec

on
0
R78
0
R77
0
R76
0
R75
0
R74
20V-5V
TP7
TP8
GND
GND GND
4700pF
C86
PGND
1
VIN
2
NC 3
BOOT 4
VCC
5
AGND 6
FB 7
PG 8
EN
9
VIN
10
PGND
11
SW 12
LMR33620AQRNXRQ1
U8
100k
R72
24.9k
R73
GND
GND
GND
6.8uH
L5
5V_LDO
22µF
C69
22µF
C70
22µF
C71
22µF
C68
5V
GND
1µF
C62
GND
VCC
10pF
C59
220nF
50V
C65
220nF
50V
C67
50V
4.7uF
C66
50V
4.7uF
C64
50V
100uF
C63
GND
20V-5V
10µF
C87
10µF
C88
20V-5V
0.047uF
C57
10µF
C80
GND
0.047uF
C82
GND
0.047uF
C79
GND
10µF
C46
TP1
0.047uF
C48
GND
10µF
C49
GND
0.047uF
C51
10µF
C52
GND
0.047uF
C54
0.1uF
C58 0.1uF
C56 0.1uF
C47
0.1uF
C81 0.1uF
C78
0.1uF
C50
0.1uF
C53
0
R71
GND_BAT
VSLEEP
GND
Green
12
D10
560
R89
TP4
TP6
50V
0.01uF
C85
1
2
3
J21
1
2
3
J26
INH
INH
1
2
3
J22
1
2
3
J27
1
2
3
J23
VDDA_LDO
VDDA
3V3
VDDIO_LDO
VDDIO
3V3
VSLEEP_LDO
VSLEEP
3V3
GND
2.49k
R83
VDDIO
GND
2.49k
R84
VDDIO
GND
RX_D2_RX_P
2.49k
R85
VDDIO
1
2
J32
GND
RX_D3_RX_M
2.49k
R86
VDDIO
1
2
J33
1
2
J34
1
2
J31
STRAPS
GND
RX_CTRL
2.49k DNI
R81
2.49k
R79
VDDIO
PHY_ADD[0,2]
1
2
J29
GND
STRP_1
2.49k DNI
R82
2.49k
R80
VDDIO
PHY_ADD[1,3]
1
2
J30
TPS7A4701QRGWTQ1
OUT 1
NC 2
SENSE/FB 3
6P4V2
4
6P4V1
5
3P2V
6
GND 7
1P6V
8
0P8V
9
0P4V
10
0P2V
11
0P1V
12
EN
13
NR 14
IN
15
IN
16
NC 17
NC 18
NC 19
OUT 20
PAD 21
U9
GND
0.47uF
C83
3V3_MSP TP3
1
2
J24
GND
GND
GND
0.047uF
C73
5V_MSP
5V
10µF
C74
GND
0.047uF
C76
0.1uF
C75
0.1uF
C72
1
2
3
J25
INH
GND
Green
12
D11
560
R90
1V0
1 2
J20
5V_LDO 5V
GND
Green
12
D12
560
R91
3V3_MSP
GND
RX_D1
RX_D0
0
R92
0
R93
0
R94
0
R95
1 2
34
L6
1
2
J28
1803277
RX_CLK
2.49k DNI
R97
2.49k
R96
VDDIO
1
2
J35
GND
TP11
TP13
TP12
1
J51
Figure 4-4. Schematic : Power and Straps
Schematic, Board Layout, and Bill of Materials www.ti.com
18 DP83TG721EVM-MC User Guide SNLU321 – JANUARY 2023
Submit Document Feedback
Copyright © 2023 Texas Instruments Incorporated

S1_1
KSR221GLFS
GND_H
CLOSE TO CHIP XO_H
GND_H
GND_H
470
R80_1
47µF
C86_1
GND_H
RESET_N_H
1 2
Y4_1
XI_H
GND_H
GND_H
VDDIO_H
ANEG_DIS RX_DV/RX_CTRL
GND_H
GND_H
GND_H
RX_D0_H
RX_D2
RGMII_CLK_SKEW_RX[0]
PHY_ADD[2] / PHY_ADD[3]
2.49k
R36_1
PHY_ADD[0] / PHY_ADD[1]
LED_2
2.49k
R25_1
2.49k
R28_1
5.76k
R26_1
2.49k
R13_1
2.49k
R11_1
GPIO0/RX_ER_SMA
MIRROR_EN
GND_H
3
1
2
Q2_1
DNBT8105-7
Green
12
D6_1
QTLP630C4TR
470
R50_1
3V3_H
3
1
2
Q1_1
DNBT8105-7
Bi-color LED
13 24
Y G
D5_1
HSMF-C166
470
R42_1
470
R43_1
3
1
2
Q3_1
DNBT8105-7
LED_2
GND_H
LED_1H
GND_H
3V3_H
GND_H
2.49k
R41_1
LED_0_H
LED Strap
LED_0_H
2.49k
R57_1
GPIO1/COL_SMA
1
2 3 4 5
J7_1
142-0701-851
GND_H
CLK_OUT_SMA
RGMII_CLK_SKEW_RX[1] [2]
5.76k
R54_1
2.49k
R58_1
GND_H
2.49k
R55_1
VDDIO_H
GND_H
2.49k
R56_1
VDDIO_H
GND_H GND_H
LED_1H RGMII_CLK_SKEW_TX[2]
RX_0ns_delayRX_2ns_delayTX_0ns_delayTX_2ns_delay
RX_0ns_delay
RX_2ns_delay
TX_0ns_delay
TX_2ns_delay
RX and TX clock skew
10.0k
R14_1
1
2
J2_1
TSW-102-07-G-S
MDIO_H
VDDIO_H
VDDIO_H
1uF
C57_1
100nF
C58_1
GND_H GND_H
1uF
C67_1
100nF
C68_1
GND_H GND_H
Place one 0.1uF and one 1uF close to each pin of ethernet PHY
VDDA2P5
1uF
C59_1
100nF
C60_1
GND_H GND_H
1uF
C69_1
100nF
C70_1
GND_H GND_H
10µF
C61_1
GND_H GND_H
1uF
C71_1
100nF
C72_1
GND_H GND_H
VDDIO_H
VDDIO_H
VDDA2P5
VDD1P0
1uF
C21_1
100nF
C22_1
GND_H GND_H
1uF
C23_1
100nF
C24_1
GND_H GND_H
VDD1P0
VDD1P0
1uF
C55_1
100nF
C56_1
GND_H GND_H
1uF
C63_1
100nF
C64_1
GND_H GND_H
VDD1P0
10µF
C53_1
GND_H GND_H
10µF
C65_1
GND_H GND_H
50V
0.01uF
C54_1
50V
0.01uF
C62_1
50V
0.01uF
C66_1
50V
0.01uF
C85_1
50V
27pF
C114_1
50V
27pF
C115_1
1
2
3
J8_1
TSW-103-07-G-S
1
2
3
J9_1
TSW-103-07-G-S
0
R206_1
0
R211_1
2.2k
R18_1
2.2k
R51_1
2.2k
R52_1
2.2k
R53_1
1.00M
R213_1
25MHz
Layout Caps placement
CLK_OUT 18
COL/GPIO
40
PAD 49
GTX_CLK
29
INT/PWDN 44
JTAG_CLK 20
JTAG_TDI 23
JTAG_TDO 21
JTAG_TMS 22
LED_0 47
LED_1 46
LED_2 45
MDC 16
MDIO 17
RBIAS 12
RX_CLK
32
RX_D0/SGMII_COP
33
RX_D1/SGMII_CON
34
RX_D2/SGMII_SOP
35
RX_D3/SGMII_SON
36
RX_DV/RX_CTRL
38
RX_ER/GPIO
39
RESET 43
TD_M_A 2
TD_M_B 5
TD_M_C 8
TD_M_D 11
TD_P_A 1
TD_P_B 4
TD_P_C 7
TD_P_D 10
TX_D0/SGMII_SIN
28
TX_D1/SGMII_SIP
27
TX_D2
26
TX_D3
25
TX_EN/TX_CTRL
37
VDD1P1
31
VDD1P1
42
VDD1P1
24 VDD1P1
6
VDDA1P8
48 VDDA1P8
13
VDDA2P5
9VDDA2P5
3
VDDIO
41
VDDIO
19
VDDIO
30
XI 15
XO 14
DP83867RGZR
U4_1
VDDIO_H
VDD1P0
VDDA2P5
VDDA1P8
GTX_CLK
TX_EN/TX_CTRL
TX_D0
TX_D1
TX_D2_H
TX_D3_H
RX_CLK_H
RX_DV/RX_CTRL
GPIO0/RX_ER_SMA
GPIO1/COL_SMA
RX_D0_H
RX_D1_H
RX_D2
RX_D3
GND_H
CLOSE TO CHIP
33pF
C12_1
RBIAS
LED_0_H
LED_1H
LED_2
MDC_H
MDIO_H
INT_PWDN
RESET_N_H
CLK_OUT_SMA
XI_H
XO_H
GND_H
2.2k
R48_1
VDDIO_H
TD_A_P
TD_A_N
TD_B_P
TD_B_N
TD_C_N
TD_D_P
TD_D_N
TD_C_P
11.0k
R21_1
1uF
C13_1
100nF
C14_1
GND_H GND_H
1uF
C17_1
100nF
C18_1
GND_H GND_H
10µF
C15_1
GND_H GND_H
50V
0.01uF
C16_1
VDDA1P8
VDDA1P8
5.76k
R111
10.0k
R113
100
R112
LED Sec

on
Crystal Oscillator
Reset Pin Ethernet PHY
CLKOUT
MDIO Pull Up
Decoupling Caps
Strapping
Figure 4-5. Schematic : DP83867
www.ti.com Schematic, Board Layout, and Bill of Materials
SNLU321 – JANUARY 2023
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DP83TG721EVM-MC User Guide 19
Copyright © 2023 Texas Instruments Incorporated

GND_H
GND_H
1V0_H
100nF
16V
C132_1
Close to LDO
5V_H
GND_H
5V_H
GND_H GND_H
1V8
GND_H
Adjustable Supplies:
3.3-V (Default) - 4.22K
2.5-V - 2.56K
1.8-V - 1.2k
VDD1P0
3V3_H
1V0_H
VDDA2P5
2V5
3V3_H
GND_H
2V5
3V3_H
GND_H
1V8
3V3_H
GND_H
1V0_H
GND_H
GND_H
4.7µF
C2_1
GND_H
GND_H
GND_H
2.49k
R231_1
2.49k
R232_1
2.49k
R233_1
3V3_H
2.49k
R221_1
VDD1P8
Supply
VDD1P0
Supply Supply LED
Indica

on
External or Internal Power Supply
Selec

on
SHDN
1
IN
2
3
OUT 4
ADJ 5
6
GNDTAB
TL1963AQKTTRQ1
U1_1
IN
1
IN
2
PG 3
BIAS
4
EN
5
GND 6
SS
7
FB 8
OUT 9
OUT 10
PAD 11
TPS74701DRCR
U3_1
3
1
2
Q5_1
DNBT8105-7
3
1
2
Q6_1
DNBT8105-7
3
1
2
Q4_1
DNBT8105-7
3
1
2
Q7_1
DNBT8105-7
16V
1uF
C130_1
1.20k
R236_1
VDDA1P8
1V8
GND_H
3V3_H
1
2
J4_1
TSW-102-07-G-S
1
2
J5_1
TSW-102-07-G-S
1
2
J3_1
TSW-102-07-G-S
1µF
C134_1
4.53k
R235_1
1.13k
R4_1
Ferrite Bead Op

on
Ferrite Bead Op

on
10µF
C135_1
10µF
C133_1
3.9V
D17_1
1SMB5915BT3G
3.9V
D15_1
1SMB5915BT3G
1
2
J1_1
TSW-102-07-G-S
GND_H
5V_H
GND_H
GND_H
2V5
GND_H
2.55k
R8_1
VDD2P5
Supply
SHDN
1
IN
2
3
OUT 4
ADJ 5
6
GNDTAB
TL1963AQKTTRQ1
U2_1
16V
1uF
C9_1
Ferrite Bead Op

on
3.9V
D9_1
1SMB5915BT3G
GND_H
5V_H
GND_H GND_H
GND_H
3V3_H
VDD3P3
Supply
SHDN
1
IN
2
3
OUT 4
ADJ 5
6
GNDTAB
TL1963AQKTTRQ1
U7_1
16V
1uF
C26_1
Ferrite Bead Op

on
3.9V
D7_1
1SMB5915BT3G
10V
100uF
C1_1
50V
27pF
C3_1
25V
10uF
C4_125V
10uF
C6_1
25V
10uF
C7_1
25V
10uF
C8_1
25V
10uF
C19_1
25V
10uF
C20_1
50V
0.01uF
C10_1
50V
0.01uF
C27_1
50V
0.01uF
C127_1
16V
22uF
C117_1
16V
22uF
C120_1
16V
22uF
C124_1
16V
22uF
C125_1
Green
12
D1_1
QTLP630C4TR
Green
12
D2_1
QTLP630C4TR
Green
12
D3_1
QTLP630C4TR
Green
12
D4_1
QTLP630C4TR
0
R7_1
0
R2_1
0
R44_1
0
R5_1
0
R3_1
0
R6_1
0
R46_1
0
R1_1
2.40k
R9_1
2.40k
R47_1
2.40k
R237_1
4.22k
R45_1
470
R220_1
470
R228_1
470
R229_1
470
R230_1
10.0k
R239_1
50V
0.01uF
C5_1
VDDIO_H
Figure 4-6. Schematic : DP83867 Power
Schematic, Board Layout, and Bill of Materials www.ti.com
20 DP83TG721EVM-MC User Guide SNLU321 – JANUARY 2023
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Copyright © 2023 Texas Instruments Incorporated