Texas Instruments DAC5687 EVM User manual

DAC5687 EVM
User's Guide
March 2007 Wireless Infrastructure Products
SLWU017B

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Contents
1 Overview .................................................................................................................... 51.1 Purpose............................................................................................................ 51.2 EVM Basic Functions ............................................................................................ 51.3 Power Requirements ............................................................................................ 51.4 Software Installation ............................................................................................. 61.5 Hardware Configuration ......................................................................................... 62 DAC5687 EVM Operational Procedure ........................................................................... 72.1 Starting the Serial Interface Program ........................................................................ 102.2 DAC5687 Initial Setup Tests .................................................................................. 112.3 DAC5687 GUI Register Descriptions ........................................................................ 133 Physical Description .................................................................................................. 163.1 PCB Layout ...................................................................................................... 173.2 Parts List ......................................................................................................... 204 Circuit Description ..................................................................................................... 224.1 Input Clocks ..................................................................................................... 224.2 Input Data ........................................................................................................ 224.3 Output Data ..................................................................................................... 234.4 Control Inputs ................................................................................................... 244.5 Internal Reference Operation ................................................................................. 254.6 External Reference Operation ................................................................................ 255 Revision History ........................................................................................................ 266 Schematics ............................................................................................................... 26
Important Notices ............................................................................................................... 27
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List of Figures
1 Serial Interface GUI ........................................................................................................ 102 DAC5687 Setup for X4L Mode and NCO Tone at F
DAC
/25 ........................................................... 113 Spectrum with CLK2 = 500 MHz, X4L Interpolation and NCO Frequency = 343597383 ......................... 124 DAC5687 Setup for X4 Mode and NCO Tone at F
DAC
/15 ............................................................ 135 Top Layer 1 ................................................................................................................. 176 Layer 2, Ground Plane .................................................................................................... 187 Layer 3, Power Plane ...................................................................................................... 198 Bottom Layer ................................................................................................................ 20
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1 Overview
1.1 Purpose
1.2 EVM Basic Functions
1.3 Power Requirements
1.3.1 Voltage Limits
User's GuideSLWU017B – APRIL 2005 – Revised March 2007
DAC5687 EVM
This user's guide document gives a general overview of the DAC5687 evaluation module (EVM) andprovides a general description of the features and functions to be considered while using this module.
The DAC5687 EVM provides a platform for evaluating the DAC5687 digital-to-analog converter (DAC)under various signal, reference, and supply conditions. This document should be used in combination withthe EVM schematic diagram supplied.
Digital inputs to the DAC can be provided with CMOS level signals up to 250 MSPS (external clock mode)through two 34-pin headers. This enables the user to provide high-speed digital data to the DAC5687device.
The analog outputs from the DAC are available via SMA connectors. Because of its flexible design theanalog outputs of the DAC5687 device can be configured to drive a 50- Ωterminated cable using a 4:1 or1:1 impedance ratio transformer, or single-ended referred to AVDD. The EVM also allows for an option todouble the output power by summing the DAC A and DAC B outputs through a 1:1 transformer.
The EVM allows the user to input single-ended, TTL/CMOS level signals, to generate differential clocksources for both CLK1 and CLK2. See Section 4.1, Input Clocks, for proper configuration and operation.
Power connections to the EVM are via banana jack sockets.
In addition to the internal bandgap reference provided by the DAC5687 device, options on the EVM allowan external reference to be provided to the DAC.
The DAC5687 EVM allows the user to program the DAC5687 internal registers with the supplied computerparallel port cable and serial interface software. The interface allows read and write access to all registersthat define the operation mode of the DAC5687 device.
The demonstration board requires only two power supplies. 3.3 Vdc is required at banana jack J7, with thereturn connected to J9. 1.8 Vdc is required at banana jack J8, with the return to J10.
CAUTION
Exceeding the maximum input voltages can damage EVM components.Undervoltage may cause improper operation of some or all of the EVMcomponents.
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1.4 Software Installation
1.5 Hardware Configuration
Overview
All necessary software to operate the serial interface is provided on the enclosed CD-ROM.1. Insert the CD-ROM into the computer to be used to operate the serial interface.2. Click on the zipped directory called DAC5687SPI_Installv2p2.zip. Extract all of the files into a newdirectory, called C:\temp, on the PC.3. Go the following directory: C:\temp\Installer. Double click on the file called setup.exe.4. The software will create a top level directory at the following location: C:\ProgramFiles\TI.fdr\DAC5687_SPI. This directory will contain the required files as well as a labwindows-cviruntime engine to run the software.5. Once the installation is complete, the software is launched by running DAC5687_SPI.exe. SeeChapter 2, DAC5687 EVM Operational Procedure, for instructions on operating the serial interfacesoftware.
The DAC5687 EVM can be set up in a variety of configurations to accommodate a specific mode ofoperation. Before starting evaluation, the user should decide on the configuration and make theappropriate connections or changes. The demonstration board comes with the following factory-setconfiguration:
•Differential clock mode using transformers T3 and T4. Input single-ended clocks are required at J3 andJ4.•Transformer-coupled outputs using 4:1 transformers T1 and T2.•The converter is set to operate with internal reference. Jumper W1 is installed between pins 2 and 3.•Full-scale output current set to 20 mA through RBIAS resistor R1.•The DAC5687 output is enabled (sleep mode disabled).•TxENABLE is set high to enable the DAC5687 device to process data. A jumper is installed betweenpins 11 and 12 on J15.•Internal PLL disabled. Jumper W3 is installed between pins 2 and 3.•Input data level is set to +3.3VDC. Jumper W2 is installed between pins 1 and 2.
To prepare the DAC5687 EVM for evaluation, connect the following:1. 3.3 V to J7 and the return to J9.2. 1.8 V to J8 and the return to J10.3. Provide a single-ended, 1-V
PP
, 0-V offset sine-wave signal to SMA connector J3 (CLK1) if the internalPLL is to be used. Connect this signal to SMA connector J4 (CLK2) if the PLL is disabled. A secondsine-wave source is required only for dual clock mode. In this mode, the signal on CLK1 is used toclock data into the DAC5687 and the signal on CLK2 is used to clock the internal DAC. CLK1 andCLK2 must be phase-aligned for this option to work properly. In order to preserve the specifiedperformance of the DAC5687 converter, the clock sources must feature very low jitter. Using a clockwith a 50% duty cycle gives optimum dynamic performance.4. Use a digital test pattern generator with 50- Ωoutputs to provide 3.3-V CMOS logic level inputs toconnectors J13 and J14. Adjust the digital inputs to provide the proper voltage levels and setup andhold times at the DAC5687 inputs. See the DAC5687 data sheet (SLWS164 ) for timing information.5. Connect one end of the supplied serial interface cable to the parallel port of a PC. Connect the otherend of the cable to J1 on the EVM.6. The DAC5687 outputs can be monitored using SMA connector J5 for IOUTA and SMA connector J19for IOUTB.
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2 DAC5687 EVM Operational Procedure
DAC5687 EVM Operational Procedure
To prepare the DAC5687 EVM for operation, follow these steps:1. Parallel Port Interface: Connect one end of the supplied serial interface cable to the parallel port of aPC and the other end of the cable to J1 on the EVM and skip steps 2 to 7.2. USB Interface: Connect the provided USB to SPI adapter board to the parallel port connector on theEVM and to a spare USB port on the host PC using the supplied USB cable. The Windows Found NewHardware Wizard should open; if this is not the case make sure the cable is connected properly. Select“No, not this time” from the options available and then click “Next” to proceed with the installation.
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DAC5687 EVM Operational Procedure
3. Select "Install the software automatically (recommended)" as shown below and then click "Next".
4. If Windows is not able to find the appropriate USB drivers press “Back” and select “Install from a list orspecific location (advanced)”. Click “Next”.5. Select "Search for the best driver in these locations" and browse for the folder where the DAC5687program was installed (the default location is C:\Program Files\Texas Instruments\DAC5687). Once thefile path has been selected, click “Next” to proceed.
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DAC5687 EVM Operational Procedure
6. If Windows XP is configured to warn when unsigned (non-WHQL certified) drivers are about to beinstalled, the following screen is displayed unless installing a Microsoft WHQL certified driver. Click on"Continue Anyway" to continue with the installation. If Windows XP is configured to ignore file signaturewarnings, no message will appear.
7. Windows should then display a message indicating that the installation was successful. Click "Finish"to complete the installation.
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2.1 Starting the Serial Interface Program
DAC5687 EVM Operational Procedure
Power up the EVM. After power up, depress switch S1 to reset the DAC5687. Start the software byrunning the following executable:
C:\Program Files\TI.fdr\DAC5687_SPI\ DAC5687_SPI.exe.
If the EVM is powered on with the parallel port connected properly, then the GUI shown in Figure 1 isdisplayed with the default settings read from the device. The hardware and software are now ready fortesting. For serial interface operation, simply click on the switches, up/down arrows, etc.., to select thedesired settings of the DAC5687. If there is a problem with the communication, such as the EVM is notpowered on or the parallel port cable is not connected, an error message will be displayed instructing theuser to correct the problem. Once corrected, hit the "Read All" button, located in the lower right corner ofthe GUI, to read the default settings of the device.
Figure 1. Serial Interface GUI
For normal operation, the user needs only to select values and switches as desired. The values areautomatically sent to the device and read back to verify their configuration.
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2.2 DAC5687 Initial Setup Tests
DAC5687 EVM Operational Procedure
There are several initial tests with the DAC5687 that can be done without any input data. The followingsetup steps are suggested to familiarize the user with the DAC5687 and EVM software and verify that theDAC5687 is functioning properly.1. Provide a CLK2 input if the PLL is disabled or a CLK1 input if the PLL is enabled (W3). Do not provideparallel input data.2. Power up EVM with 1.8V DVDD and 3.3V AVDD3. Start DAC5687_SPI software.4. Click on the "Load Regs" button on the GUI. A new directory window will open. Click on the file called"User Guide Test.reg5687". Click on "OK". This will load a test setting for the DAC, corresponding toF
NCO
/12.5 = 20 MHz for CLK2 = 500 MSPS (F
NCO
= F
DAC
/2 for X4L mode). The GUI should now lookas shown in Figure 2 .
Figure 2. DAC5687 Setup for X4L Mode and NCO Tone at F
DAC
/25
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DAC5687 EVM Operational Procedure
This tone is being generated by the DAC5687 NCO. With no input data provided to connectors J13and J14, the Channel A and B data bus inputs will all be zeros, or a full scale negative value in thedefault offset binary format. In the X4L mode, after the first 2x interpolation, the full scale DC inputsignal at a clock rate of 250 MSPS is mixed with the NCO running at the setting of F
NCO
/12.5(343597383) to generate a tone at 20 MHz. After a second 2x interpolation, a 20 MHz tone is outputfrom the DAC sampling at 500 MSPS. The output spectrum should be similar to Figure 3 .
Figure 3. Spectrum with CLK2 = 500 MHz, X4L Interpolation and NCO Frequency = 343597383
5. Change the Mode to 1000 F
DAC
/4 (+,+), corresponding to F
DAC
/4 (see data sheet). This will increasethe output by F
DAC
/4 to 20 MHz + 125 MHz = 145 MHz.6. Changing the NCO DDS to 3951369913 (2
32
x (1-20/250)) will now result in an output tone at 125 MHz- 20 MHz = 105 MHz.7. Change the interpolation to X4, and the mode to No Mixing, the NCO DDC to 286331153 (F
NCO
/15)and reduce the CLK2 frequency to < 320 MSPS. The GUI should look as shown in Figure 4 . The NCOis now running at the DAC update rate (= CLK2). For CLK2 = 300 MSPS, the result is an output toneat 20 MHz.
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2.3 DAC5687 GUI Register Descriptions
2.3.1 Register Controls
DAC5687 EVM Operational Procedure
Figure 4. DAC5687 Setup for X4 Mode and NCO Tone at F
DAC
/15
⋅Load Regs: Loads register values from a saved file to the DAC5687 and updates theGUI.⋅Save Regs: Saves current GUI registers settings to a text file for future use.⋅Read All: Reads the current registers of the DAC5687. This is used to verify settingson the front panel.⋅Send All: Sends the current front panel registers to the device. This is generally onlyused when the EVM power has recycled or the device has been reset andthe user wants to load the displayed settings to the device.
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2.3.2 Configuration Controls
DAC5687 EVM Operational Procedure
⋅Full Bypass: When set, all filtering, QMC, and NCO functions are bypassed.⋅FIR Bypass: When set, the interpolation filters are bypassed.⋅FIFO When set to bypass, the internal 4 sample FIFO is disabled. WhenBypass: cleared, the FIFO is enabled.⋅FIR A: A side first FIR filter in highpass mode when set, lowpass mode whencleared.⋅FIR B: B side first FIR filter in highpass mode when set, lowpass mode whencleared.⋅Dual Clk: Only used when the PLL is disabled. When set, two differential clocks areused to input the data to the chip; CLK1/CLK1C is used to latch the inputdata into the chip, and CLK2/CLK2C is used as the DAC sample clock⋅Interleave: When set, interleaved input data mode is enabled; both A and B datastreams are input at the DA(15:0) input pins.⋅Inverse Sinc: Enables inverse sinc filter.⋅Half Rate Enables half rate input mode. Input data for the DAC A data path is inputInput: to the chip at half speed using both the DA(15:0) and DB(15:0) input pins.⋅Sif: Sets sif_4pin bit. 4 pin serial interface mode is enabled when on, 3 pinmode when off. The DAC5687 EVM is configured for a 3 pin serialinterface. The 4 bit serial interface will not work with the DAC5687 EVM.⋅Inv. PLL Only used when PLL is disabled and dual clock mode is disabled. WhenLock: cleared, input data is latched into the chip on the rising edge of thePLLLOCK output pin. When set, input data is latched into the chip on thefalling edge of the PLLLOCK output pin.⋅PLL Freq: Sets PLL VCO center frequency to low or high center frequency.⋅PLL Kv: Sets PLL VCO gain to either high or low gain.⋅Qflag: Sets qflag bit. When set, the QFLAG input pin operates as a B sampleindicator when interleaved data is enabled. When cleared, the TXENABLErising determines the A/B timing relationship.⋅2's Comp: When set, input data is interpreted as 2's complement. When cleared,input data is interpreted as offset binary.⋅Rev A Bus: When cleared, Channel A input data MSB to LSB order is DA(15) = MSBand DA(0) = LSB. When set, Channel A input data MSB to LSB order isreversed, DA(15) = LSB and DA(0) = MSB.⋅Rev B Bus: When cleared, Channel B input data MSB to LSB order is DB(15) = MSBand DB(0) = LSB. When set, Channel B input data MSB to LSB order isreversed, DB(15) = LSB and DB(0) = MSB.⋅USB: When set, the data to DACB is inverted to generate upper side bandoutput.⋅Inv. Clk I(Q): Inverts the DAC core sample clock when set, normal when cleared.⋅Sync_Phstr: When set, the internal clock divider logic is initialized with a PHSTR pinlow to high transition.⋅Sync_cm: When set, the coarse mixer is synchronized with a PHSTR low to hightransition.
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DAC5687 EVM Operational Procedure
⋅Sync_NCO: When set, the NCO phase accumulator is cleared with a phstr low to hightransition.⋅Phstr Clk Div Selects the clock used to latch the PHSTR input when restarting theSelect: internal clock dividers. When set, the full rate CLK2 signal latches PHSTR.When cleared, the divided down input clock signal latches PHSTR.⋅DAC Serial When set, both DAC A and DAC B input data is replaced with fixed dataData: loaded into the 16 bit serial interface DAC Static Data.oCounter Mode: Controls the internal counter that can be used as the DACdata source. See the data sheet for more information.oDAC Static Data: When DAC Serial Data is set, both DAC A and DAC Binput data is replaced with fixed data loaded with this value. Range = 0 to65535.⋅NCO: When set, enables NCO.oNCO Gain: Sets NCO gain resulting in a 2x increase in NCO outputamplitude. Except for F
S
/2 and F
S
/4 mixing NCO frequencies, thisselection can result in saturation for full scale inputs. Consider using QMCgain for lower gains.⋅QMC: When set, enables the QMC.oQMCA Gain: Sets QMC gain A to a range = 0 to 2047. See the datasheet for more information.oQMC B Gain: Sets QMC gain B to a range = 0 to 2047. See the datasheet for more information.oQMC Phase: Sets QMC phase to a range = -512 to 511. See the datasheet for more information.⋅Mode: Used to select the coarse mixer mode. See the DAC5687 data sheet formore information.⋅PLL Divider: Sets VCO divider to div by 1, 2, 4, or 8.⋅Interpolation: Sets FIR Interpolation factor: {X2, X4, X4L, X8}. X4 uses lower power than4xL, but F
DAC
= 320 MSPS max when NCO or QMC are used.⋅Phstr Init. Adjusts the initial phase of the F
S
/2 and F
S
/4 cmix block at PHSTR.Phase:
⋅Sync FIFO: Sync source selection mode for the FIFO. When a low to high transition isdetected on the selected sync source, the FIFO input and output pointersare initialized. See the DAC5687 data sheet for source description.⋅Alt. Sets PLLLOCK output pin to F
DAC
frequency when operating in the PLLPLLLOCK mode. Settings must be used in conjunction with the interpolation settingOutput: to achieved desired rate (i.e. set to F
DAC
/2 for 2x interpolation, set toF
DAC
/4 for 4x interpolation). Note, there is no option for the 8x mode. Thejumper at W1 (EXTLO) must be removed to utilize this functionality.
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2.3.3 DAC A(B) Gain
2.3.4 NCO
2.3.5 Additional Control/Monitor Registers
3 Physical Description
Physical Description
⋅DAC Coarse Sets coarse gain of DAC A(B) full scale current. Range is 0 to 15. See theGain: DAC5687 data sheet for full scale gain equation.⋅DAC Fine Sets fine gain of DAC A(B) full scale current. Range is -128 to 127. See theGain: DAC5687 data sheet for full scale gain equation.⋅DAC DC Sets DAC A(B) DC offset register. Range is -4096 to 4095.Offset:
⋅Sleep: DAC A(B) sleeps when set, operational when cleared.
⋅NCO DDS: Sets NCO DDS registers. See the DAC5687 data sheet for formula.⋅NCO Phase: Sets initial NCO phase registers. See the DAC5687 data sheet for moreinformation.
⋅Pll Port Selection of this button will bring up a separate window that shows theConfig: parallel port configuration of the software. The EVM Menu should beloaded with DAC EVM. This button also allows the user to change the LPTaddress used by the PC. This is set by entering a valid address inside thebox labeled "LPT Address". The default setting is 378.⋅Quit: Quits the operation of the DAC5687 software.⋅Version: Displays the version of the silicon. If a version of 0 is read then thecommunication is not functioning and an error message will be displayed.⋅About: Opens an additional window with help related topics for the software.
This chapter describes the physical characteristics and PCB layout of the EVM and lists the componentsused on the module.
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3.1 PCB Layout
Physical Description
The EVM is constructed on a 4-layer, 4.9-inch x 6.5-inch, 0.055-inch thick PCB using FR-4 material.Figure 5 through Figure 8 show the PCB layout for the EVM.
Figure 5. Top Layer 1
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Physical Description
Figure 6. Layer 2, Ground Plane
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Physical Description
Figure 7. Layer 3, Power Plane
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3.2 Parts List
Physical Description
Figure 8. Bottom Layer
Table 1 lists the parts used in constructing the EVM.
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