Texas Instruments UCC14341EVM-069 User manual

User’s Guide
Using the UCC14341EVM-069 for Biasing Traction Inverter
Gate Driver ICs Requiring Single, Positive or Dual,
Positive/Negative Bias Power
ABSTRACT
This user’s guide provides a description as well as directions for use of the UCC14341EVM-069 to evaluate the
UCC14341-Q1, high frequency, integrated transformer, DC-DC converter module from Texas Instruments. This
EVM allows designers to quickly and efficiently evaluate the UCC14341-Q1 for use in automotive or industrial
applications requiring gate driver IC bias power as high as 1.5 W, meeting up to 5-kVRMS isolation.
Table of Contents
1 Introduction.............................................................................................................................................................................2
1.1 Pin Configuration and Functions........................................................................................................................................ 2
2 Description.............................................................................................................................................................................. 4
2.1 EVM Electrical Performance Specifications....................................................................................................................... 5
3 Schematic................................................................................................................................................................................6
4 EVM Setup and Operation......................................................................................................................................................7
4.1 Recommended Test Equipment......................................................................................................................................... 7
4.2 External Connections for Easy Evaluation......................................................................................................................... 7
4.3 Powering the EVM............................................................................................................................................................. 8
4.4 EVM Test Points.................................................................................................................................................................9
4.5 Probing the EVM.............................................................................................................................................................. 10
5 Performance Data ................................................................................................................................................................ 11
5.1 Efficiency Data..................................................................................................................................................................11
5.2 Regulation Data............................................................................................................................................................... 13
5.3 Steady State Input Current...............................................................................................................................................14
5.4 Start-up Waveforms......................................................................................................................................................... 14
5.5 Inrush Current.................................................................................................................................................................. 16
5.6 AC Ripple Voltage............................................................................................................................................................ 18
5.7 EN-to-/PG Timing.............................................................................................................................................................20
5.8 RLIM.................................................................................................................................................................................21
5.9 Fault Protection................................................................................................................................................................ 23
5.10 Shutdown....................................................................................................................................................................... 26
5.11 Thermal Performance.....................................................................................................................................................28
6 Assembly and Printed Circuit Board (PCB) Layers...........................................................................................................29
7 Bill of Materials (BOM)..........................................................................................................................................................32
Trademarks
All trademarks are the property of their respective owners.
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1 Introduction
The UCC14341-Q1 is a high efficiency, low-emissions, 5 kVRMS Isolated DC-DC Converter capable of delivering
1.5-W of power. Since the UCC14341-Q1 provides isolated power in an integrated package, this allows systems
to reduce cost and size by removing the need for separate isolated power supplies. The UCC14341-Q1 delivers
class-leading efficiency in power conversion from the primary to the secondary side while removing the need
for bulky external transformers or power modules commonly used in existing designs. This integration allows for
minimal printed circuit board (PCB) area as well as decreased height profile.
1.1 Pin Configuration and Functions
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
VEE
VEEA
FBVDD
FBVEE
RLIM
VEE
VEE
VDD
VDD
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
PG
GNDP
GNDP
ENA
GNDP
VIN
VIN
GNDP
GNDP
GNDP
GNDP
GNDP
GNDP
GNDP
GNDP
GNDP
GNDP
GNDP
Figure 1-1. DWN Package, 36-Pin SSOP (Top View)
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Table 1-1. Pin Functions
PIN TYPE(1) DESCRIPTION
NAME NO.
GNDP
1, 2, 5, 8, 9, 10,
11, 12, 13, 14,
15, 16, 17, 18
GPrimary-side ground connection for VIN. PIN 1,2, and 5 are analog ground. PIN 8, 9, 10, 11, 12,
13, 14, 15, 16, 17, and 18 are power ground. Place several vias to copper pours for thermal relief.
PG 3 O
Active low power-good open-drain output pin. PG remains low when (UVLO ≤ VVIN ≤
OVLO); (UVP1 ≤ (VDD – VEE) ≤ OVP1); (UVP2 ≤ (COM – VEE) ≤ OVP2); TJ_Primary ≤
TSHUTPPRIMARY_RISE; and TJ_secondary ≤ TSHUTSECONDARY_RISE
ENA 4 I Enable pin. Forcing ENA LOW disables the device. Pull HIGH to enable normal device
functionality. 5.5-V recommended maximum.
VIN 6, 7 P
Primary input voltage. PIN 6 is for analog input, and PIN 7 is for power input. For PIN 7, connect
one 10-µF ceramic capacitor from power VIN PIN 7 to power GNDP PIN 8. Connect a 0.1-µF
high-frequency bypass ceramic capacitor close to PIN 7 and PIN 8.
VEE
19, 20, 21, 22,
23, 24, 25,26,
27, 30,31, 36
GSecondary-side reference connection for VDD and COM. The VEE pins are used for the high
current return paths.
VDD 28, 29 P
Secondary-side isolated output voltage from transformer. Connect a 2.2-µF and a parallel 0.1-µF
ceramic capacitor from VDD to VEE. The 0.1-µF ceramic capacitor is the high frequency bypass
and must be next to the IC pins. A 4.7-µF or 10-µF ceramic capacitor can be used instead of
2.2-µF to further reduce the output ripple voltage.
RLIM 32 P
Secondary-side second isolated output voltage resistor to limit the source current from VDD to
COM node, and the sink current from COM to VEE. Connect a resistor from RLIM to COM to
regulate the (COM – VEE) voltage.
FBVEE 33 I
Feedback (COM – VEE) output voltage sense pin used to adjust the output (COM – VEE) voltage.
Connect a resistor divider from COM to VEE so that the midpoint is connected to FBVEE, and
the equivalent FBVEE voltage when regulating is 2.5 V. Add a 330-pF ceramic capacitor for high
frequency decoupling in parallel with the low-side feedback resistor. The 330-pF ceramic capacitor
for high frequency bypass must be next to the FBVEE and VEEA IC pins on top layer or back layer
connected with vias.
FBVDD 34 I
Feedback (VDD – VEE) output voltage sense pin and to adjust the output (VDD – VEE) voltage.
Connect a resistor divider from VDD to VEE so that the midpoint is connected to FBVDD, and
the equivalent FBVDD voltage when regulating is 2.5 V. Add a 330-pF ceramic capacitor for high
frequency decoupling in parallel with the low-side feedback resistor. The 330-pF ceramic capacitor
for high frequency bypass must be next to the FBVDD and VEEA IC pins on top layer or back
layer connected with vias.
VEEA 35 G
Secondary-side analog sense reference connection for the noise sensitive analog feedback inputs,
FBVDD and FBVEE. Connect the low-side feedback resistors and high frequency decoupling filter
capacitor close to the VEEA pin and respective feedback pin FBVDD or FBVEE. Connect to
secondary-side gate drive lowest voltage reference, VEE. Use a single point connection and place
the high frequency decoupling ceramic capacitor close to the VEEA pin.
(1) P = power, G = ground, I = input, O = output
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2 Description
The UCC14341EVM-069 is intended to allow designers to evaluate the performance characteristics and
capabilities of the UCC14341-Q1 quickly and easily for use in automotive, isolated, gate driver bias applications
as well as a variety of isolated industrial bias power applications. The EVM allows users to test functions of the
UCC14341-Q1 such as: Enable/Disable (EN) of the device as well as configure the isolated output voltage for
15 V<VDD<20 V, and -5 V<VEE<0 V and easily apply variable loads to the outputs. This EVM allows the user
to measure efficiency across the input voltage range and varying output loads according to system requirements.
Another feature of the EVM is the ease of probing during test. Test points, are strategically placed and described
according to Table 4-1
Figure 2-1. UCC14341EVM-069, HVP069E1, Top View
Figure 2-2. UCC14341EVM-069, HVP069E1, Bottom View
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2.1 EVM Electrical Performance Specifications
Table 2-1. EVM Electrical Specifications
VIN = 15 V, VDD=VDD-VEE = 18 V, VEE=VEE-COM = -4 V, TA = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT CHARACTERISTICS
VIN Input voltage range PVDD-VEE=1.5 W 13.5 15 16.5 V
VIN_ON Input voltage on PVDD-VEE=0 W 12 12.5 V
VIN_OFF Input voltage off PVDD-VEE=0 W 11 11.5 V
IIN_FL Input current at full load VIN = 13.5 V, IVDD = 68 mA 230
mAVIN = 15 V, IVDD = 68 mA 210
VIN = 16.5 V, IVDD = 68 mA 200
IIN_NL Input current at no load VIN = 13.5 V, IVDD =IVEE = 0 mA 33
mAVIN = 15 V, IVDD =IVEE = 0 mA 30
VIN = 16.5 V, IVDD =IVEE = 0 mA 29
IIN_OFF Input current at EN LOW EN LOW, VDD = VEE = 0 V 570 650 µA
EN to /PG
delay
IVDD =IVEE = 0 mA 4 5 ms
OUTPUT CHARACTERISTICS
VDD-VEE DC full load set-point 13.5 V<VIN<16.5 V, IVDD = 68 mA 21.5 22.0 22.5 V
IVDD VDD load current range 13.5 V < VIN < 16.5 V 0 68 mA
VDD%LD Load regulation VDDREG =
VImin −VImax
VImax
× 100%
VIN=15 V, 0 mA ≤ IVDD ≤ 68 mA
0.5 %
VDD%LN Line regulation VDDREG =
VImin −VImax
VImax
× 100%
IVDD=68 mA, 13.5 V ≤ VIN ≤ 16.5 V
0.05 %
VDDAC pk-to-pk AC ripple IVDD = 68 mA 290 320 mV
VDDSS Soft-start IVDD = IVEE = 0 mA 1.8 ms
PMAX Maximum output power IVDD(TYP) = 68 mA, IVDD(MAX) = 91 mA 1.5 2 W
VEE-COM DC full load set-point 13.5 V ≤ VIN ≤ 16.5 V, IVEE = 30 mA -3.992 -4.008 V
IVEE VEE load current range 13.5 V≤ VIN ≤ 16.5 V 0 35 mA
VEEAC pk-to-pk AC ripple IVEE = 30 mA 110 120 mV
SYSTEM CHARACTERISTICS
η100% Full load efficiency IVDD = 68 mA 48 %
η50% Half load efficiency IVDD = 34 mA 43 %
FSW Switching frequency (1) VIN = 13.5 V, 0 mA < IVDD < 68 mA 18
MHzVIN = 15 V, 0 mA < IVDD < 68 mA 15
VIN = 16.5 V, 0 mA < IVDD < 68 mA 12
VDD(OCL) VDD overcurrent limit IVDD > 110 mA 130 135 mA
VEE(OCL) VEE overcurrent limit IVEE > 30 mA 35 42 mA
TMAX Maximum temperature rise
above ambient
IVDD = 68 mA 44 50 °C
(1) Switching frequency is specified as primary-side switching frequency. Secondary-side is 2x primary
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3 Schematic
Figure 3-1 shows the EVM electrical schematic. C4 is intentionally unpopulated as indicated by a red X on the secondary side, placed directly over the
component.
VEE
VDD
COM
10V<VIN<15V
GNDP
3.3V<Vbias<5V
-4V
C2
10uF 10uF
C3
+18V
+22V
10uF
C1
3
2
1
J2
ENA
C1-C5, C9-C11 are gate driver bias caps
G
TP9
0.1uF
C14
0.1uF
C7
10uF
C4
0.1uF
C11
C5
0.1uF
TP8
TP7
TP10
TP2
TP5
TP11
G
TP6
VDD
COM
VEE
VIN
GNDP
VBIAS
GNDP
GNDP
VBIAS
ENA
/PG
GNDP
GNDP VEE
VEE
G
TP3
FBVDD
SH-J1
ENA
100k
R2
VEE/VEEA Ground Tie
FBVEE
VEE
TP1
TP4
FBVDD
FBVEE
2
1
J1
1
2
J4
1
3
2
J3
6VIN
7VIN
VEE 26
VEE 27
28
VDD
VDD 29
RLIM 32
FBVEE 33
34
FBVDD
VEEA 35
5GNDP
1GNDP
3PG
2GNDP
4ENA
8GNDP
9GNDP
GNDP
10
11 GNDP
12 GNDP
13 GNDP
GNDP
14
GNDP
15
16 GNDP
GNDP
GNDP
17
18 VEE 19
20
VEE
VEE 21
22
VEE
VEE 23
VEE 24
25
VEE
VEE 30
VEE 31
VEE 36
U1
+4V
UCC14341DWNQ1
330pF
C15
330pF
C16
10uF
C12
10uF
C13
5.11k
R1
C6
0.1uF
Connect R6-7, C15-16 to VEEA (pin 35)
C8
10uF
0.1%
R6
11.3k
0.1%
R7
11k
R4
88.7k
0.1%
6.65k
R5
0.1%
475
R3
3.3uF
C9
3.3uF
C10
Figure 3-1. UCC14341EVM-069 Schematic Diagram
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4 EVM Setup and Operation
4.1 Recommended Test Equipment
• VBIAS: DC power supply1: 5 V, 10 mA
• VIN: DC power supply: 20 V, 500 mA
• IVDD: Electronic load or fixed resistor: 25 V, 200 mA
• IVEE: Electronic load or fixed resistor: 5 V, 10 mA
• (3) DVMs measuring DC voltage < 30 V (V3 must be a battery powered DVM)
• (3) DVMs measuring DC current < 200 mA on IVDD, IVEE, <300 mA on IVIN
• Oscilloscope: 4 channel, 500 MHz or better, voltage probes, current probes
• Minimum wire gauge 20 AWG to 22 AWG or better
• Thermal camera (optional) or thermocouple to measure U1 case temperature
4.2 External Connections for Easy Evaluation
The UCC14341EVM-069 EVM uses screw terminals for quickly connecting to the VIN, VDD ,and VEE pins.
Connecting the appropriate ammeters and voltmeters, as shown in Typical Efficiency Measurement Setup,
allows accurate EVM efficiency measurements to be made.
Connecting Test Equipment
1. Move jumper SH-J1 into the J2:1-2, EN OFF position. This makes sure the EVM cannot start while test
equipment is being connected.
2. Connect a +5 V DC bias power supply to J1:1-2 (+3.3 V to +5 V). Set the power supply to 0 V. The +5 V
supply at J1 serves as the pullup bias for /PG and ENA. Turn off/disable the +5V DC Bias power supply.
3. Connect the VIN DC power supply capable of 10 V<VIN<20 V, 300 mA at J4:1-2 (VIN). Adjust the power
supply to 15 V, and set the current limit to 300 mA. Set the power supply voltage to 12 V. Turn off/disable the
VIN power supply.
4. Connect a variable load between J3:1 (VDD) and J3:3 (VEE). If using an electronic load, set to constant
current (CC), 68 mA. Leave the load disabled until the EVM is powered.
5. Connect a second load between J3:2 (COM) and J3:3 (VEE). If using an electronic load, set to constant
current (CC), 10 mA. Leave the load disabled until the EVM is powered. Since the required load is small, a
through-hole, 250-mW, 400-Ω load resistor can be connected between J3:2-3.
6. Some electronic loads are not be able to regulate/stabilize CC when setting in the low mA range. Monitor the
input current and load currents by inserting ammeters, A1-A3, as shown in Typical Efficiency Measurement
Setup. Use a current probe with the oscilloscope to verify the stability of the DC current being regulated by
an electronic load.
Typical Efficiency Measurement Setup
V1
A1
VIN
10 - 20 V
+5 V
DC Bias
VDD
LOAD
A2
COM
LOAD
V2
A3V3
Figure 4-1. Typical Efficiency Measurement Setup
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4.3 Powering the EVM
WARNING
• Hot Surface. Contact can cause burns. U1 package surface can reach temperatures of 45°C
above ambient. Do not touch!
• Do not test this EVM unless you are trained in the proper safety, handling and testing of power
electronics.
4.3.1 Power on for Start-up
1. Verify VIN and +5-V DC bias power supplies are OFF/disabled and no voltage is applied to the UUT
2. Move EN shorting jumper, SH-J1, to the J2:2-3 EN ON position
3. Turn on the VIN DC power supply. Verify 15-V is present at TP7-to-TP10
4. Verify the loads on VDD and VEE are disabled
5. Turn on the +5-V DC bias power supply. EVM is now enabled with VDD and VEE in regulation under no load
conditions.
6. Verify 22-V is present on VDD-VEE and 4-V is present on COM-VEE
7. Enable the 68-mA load on VDD-VEE, enable the 10-mA load on COM-VEE
8. The UCC14341-Q1 is now regulating VDD and VEE and processing 1.5-W of isolated output power
9. Vary VIN between 13.5 V<VIN<16.5 V, vary IVDD between 0 mA<IVDD<68 mA, vary IVEE between 0
mA<IVEE<30 mA.
10. Insert oscilloscope probes into TP9, TP6 and TP3 for measuring VIN, VDD and VEE start-up, steady state
and AC ripple voltage
4.3.2 Power off for Shutdown
1. Move EN shorting jumper SH-1 to the J3:1-2, EN OFF position
2. Turn off the +5 V, DC bias power supply
3. Disable the IVDD load
4. Disable the IVEE load
5. Turn off VIN power supply
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4.4 EVM Test Points
Table 4-1 describes the various EVM test points, allowing easy access for connecting oscilloscope probes,
DVM test leads and wire connections to lab test equipment as outlined in Figure 4-1. Pay attention to maintain
separation between the primary side, GNDP and secondary side, VEE. Primary-side test points are not to be
referenced to VEE through improper test equipment insertion. Likewise, secondary-side test points are not to be
referenced to GNDP through improper test equipment insertion.
Table 4-1. Input, Output, Test Point (I/O/TP) Description
PIN I/O/TP COLOR DESCRIPTION MIN TYP MAX UNIT
J1 I Green VBIAS, EN and /PG bias 3 VBIAS 5 V
J2:1-2 I Green EN, off 0 V
J2:2-3 I Black EN, on VBIAS V
J3:1-3 O Green Secondary, VDD-to-VEE 18 25 V
J3:2-3 O Green Secondary COM-to-VEE 0 5 V
J4 I Green VIN, primary input voltage 13.5 15 16.5 V
TP1 TP Black VEE, secondary side reference 0 V
TP2 TP Yellow /PG, power good test point VBIAS V
TP3 TP PCB COM-to-VEE, secondary COM scope probe point 0 5 V
TP4 TP White COM-to-VEE, secondary COM output midpoint 0 5 V
TP5 TP Yellow EN, enable test point VBIAS V
TP6 TP PCB VDD-to-VEE, secondary VDD scope probe point 18 25 V
TP7 TP Red VIN, positive probe point 13.5 15 16.5 V
TP8 TP Red VDD, secondary VDD test point 15 25 V
TP9 TP PCB VIN-to-GNDP scope probe point 13.5 15 16.5 V
TP10 TP Black GNDP, shared primary GND test point 0 V
TP11 TP Black GNDP, shared primary GND test point 0 V
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4.5 Probing the EVM
Using TP3, TP6 and TP9 oscilloscope probe PCB test points: The UCC14341-Q1 is a high frequency DC-
DC module that requires careful measurement for accurately capturing transient events and measuring high
frequency, AC ripple voltage. Remove the “witch hat” probe tip cover and ground lead from the scope probe.
If scope probe ground springs are not available, wrap a piece of 22 AWG bare wire around the scope probe
ground ring or use a fitted ground spring and insert the probe tip and ground into the EVM as shown in Figure
4-2.
Figure 4-2. UCC14341EVM-069, PCB Scope Probe Test Points
The EVM output nomenclature (VDD, VEE, COM) corresponds to what is commonly used when referring to
isolated gate driver ICs. As shown in Figure 3-1, TP4 (COM) is the midpoint of a capacitive divider and is
intended to connect to the COM pin of the isolated gate driver IC. When the UCC14341-Q1 is used to bias a
gate driver IC, VDD (VDD-COM) and VEE (VEE-COM) are referred to with respect to COM. COM can therefore
not be considered as a virtual GND to the gate driver IC. Since the midpoint of the capacitive divider is sensitive
to charge imbalance, for the purpose of probing the EVM, do not connect any ground-referenced, test equipment
to TP4 (COM). A battery powered DVM can be used to measure VEE with respect to COM. When testing the
EVM as a stand-alone bias power supply, oscilloscope probing of the secondary-side outputs should be limited
to TP3 and TP6 which are referenced to VEE. This means VDD will show an oscilloscope measurement of
VDD+|VEE| and VEE will show |VEE|. Connecting any ground-referenced test equipment to COM may result in
a “false” but safe overcurrent condition causing VDD and VEE to inadvertently drop out of regulation during light
load operation.
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5 Performance Data
Unless otherwise specified, all performance data collected using electronic load set to constant current.
5.1 Efficiency Data
PVDD-VEE (W)
Efficiency (%)
0 0.5 1 1.5 2 2.5 3
0
10
20
30
40
50
60
VIN = 13.5 V
VIN = 15 V
VIN = 16.5 V
Figure 5-1. Measured Efficiency, VDD-VEE Loading Only
Table 5-1. Efficiency Test Data (VIN = 13.5 V)
VIN (V) IIN (mA) VDD-VEE (V) IVDD-VEE (mA) VDD-COM (V) VEE-COM (V) PIN (W) PVDD-VEE (W) Eff (%)
13.52 32.81 22.21 0.00 18.17 4.04 0.44 0.00 0.00
13.51 52.67 22.18 7.29 18.14 4.04 0.71 0.16 22.71
13.50 67.69 22.18 12.58 18.14 4.04 0.91 0.28 30.53
13.51 90.37 22.17 20.67 18.13 4.04 1.22 0.46 37.54
13.51 125.55 22.15 32.54 18.11 4.04 1.70 0.72 42.49
13.51 149.01 22.14 40.71 18.10 4.04 2.01 0.90 44.77
13.51 172.28 22.13 48.81 18.08 4.05 2.33 1.08 46.41
13.51 195.95 22.12 56.98 18.07 4.05 2.65 1.26 47.61
13.51 230.88 22.10 69.05 18.06 4.05 3.12 1.53 48.94
13.51 262.87 22.09 80.06 18.04 4.04 3.55 1.77 49.80
13.51 287.76 22.07 88.35 18.03 4.04 3.89 1.95 50.16
13.51 311.76 22.04 96.36 18.00 4.04 4.21 2.12 50.43
13.51 330.85 21.95 104.35 17.93 4.02 4.47 2.29 51.25
13.51 338.69 21.75 112.18 17.74 4.02 4.58 2.44 53.34
13.51 342.90 20.87 116.45 16.86 4.02 4.63 2.43 52.47
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Table 5-2. Efficiency Test Data (VIN = 15 V)
VIN (V) IIN (mA) VDD-VEE (V) IVDD-VEE (mA) VDD-COM (V) VEE-COM (V) PIN (W) PVDD-VEE (W) Eff (%)
15.02 30.69 22.21 0.00 18.17 4.04 0.46 0.00 0.00
15.02 47.36 22.19 6.79 18.15 4.04 0.71 0.15 21.18
15.01 60.72 22.18 11.98 18.14 4.04 0.91 0.27 29.15
15.01 81.00 22.17 20.02 18.13 4.04 1.22 0.44 36.50
15.01 111.84 22.15 31.85 18.11 4.04 1.68 0.71 42.03
15.01 144.68 22.14 43.98 18.10 4.04 2.17 0.97 44.84
15.01 166.18 22.13 52.08 18.09 4.05 2.49 1.15 46.21
15.01 187.97 22.12 60.27 18.08 4.05 2.82 1.33 47.25
15.01 209.51 22.11 68.41 18.07 4.05 3.14 1.51 48.11
15.01 239.42 22.10 79.47 18.05 4.05 3.59 1.76 48.87
15.01 261.61 22.08 87.68 18.04 4.04 3.93 1.94 49.31
15.01 284.65 22.07 95.96 18.02 4.04 4.27 2.12 49.56
15.01 307.42 22.04 104.05 18.00 4.04 4.61 2.29 49.69
15.01 325.15 21.96 112.12 17.94 4.02 4.88 2.46 50.45
15.01 333.62 21.76 120.39 17.73 4.02 5.01 2.62 52.31
15.01 344.85 20.38 128.48 16.35 4.02 5.18 2.62 50.59
Table 5-3. Efficiency Test Data (VIN = 16.5 V)
VIN (V) IIN (mA) VDD-VEE (V) IVDD-VEE (mA) VDD-COM (V) VEE-COM (V) PIN (W) PVDD-VEE (W) Eff (%)
16.51 29.29 22.21 0.00 18.18 4.04 0.48 0.00 0.00
16.51 45.65 22.19 7.03 18.15 4.04 0.75 0.16 20.71
16.50 58.60 22.18 12.30 18.14 4.04 0.97 0.27 28.21
16.50 77.99 22.17 20.40 18.13 4.03 1.29 0.45 35.14
16.50 107.53 22.15 32.36 18.11 4.04 1.77 0.72 40.40
16.50 138.53 22.14 44.46 18.10 4.04 2.29 0.98 43.06
16.50 158.95 22.13 52.58 18.09 4.04 2.62 1.16 44.37
16.50 179.72 22.12 60.80 18.08 4.05 2.97 1.34 45.36
16.50 200.62 22.11 68.92 18.07 4.05 3.31 1.52 46.04
16.50 229.37 22.10 79.92 18.05 4.04 3.78 1.77 46.66
16.50 250.58 22.08 88.05 18.04 4.04 4.13 1.94 47.03
16.50 272.27 22.07 96.25 18.03 4.04 4.49 2.12 47.28
16.50 294.35 22.04 104.45 18.00 4.04 4.86 2.30 47.39
16.50 310.78 21.96 112.47 17.94 4.02 5.13 2.47 48.17
16.50 319.04 21.66 120.65 17.64 4.02 5.26 2.61 49.64
16.50 325.52 20.92 124.82 16.90 4.02 5.37 2.61 48.62
16.50 331.45 20.25 128.78 16.21 4.02 5.47 2.61 47.68
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5.2 Regulation Data
PVDD-VEE (W)
VDD-VEE (V)
0 0.5 1 1.5 2 2.5 3
20
20.5
21
21.5
22
22.5
VIN = 13.5 V
VIN = 15 V
VIN = 16.5 V
Figure 5-2. Regulation vs Power, VDD-VEE Loading Only
IVDD-VEE (mA)
VDD-VEE (V)
0 20 40 60 80 100 120 140
20
20.5
21
21.5
22
22.5
VIN = 13.5 V
VIN = 15 V
VIN = 16.5 V
Figure 5-3. Regulation vs Current, VDD-VEE Loading Only
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5.3 Steady State Input Current
PVDD-VEE (W)
IIN (mA)
0 0.5 1 1.5 2 2.5 3
0
50
100
150
200
250
300
350
VIN = 13.5 V
VIN = 15 V
VIN = 16.5 V
Figure 5-4. Input Current vs Power, VDD-VEE Loading Only
5.4 Start-up Waveforms
Figure 5-5. Start-up 1: VIN=15 V, IVDD-VEE=0 mA, (top: VDD-VEE, 10 V/div, mid-1: COM-VEE, 2 V/div, mid-2:
VDD-COM, 10 V/div, bot: VEE-COM, 5 V/div), time = 1 ms/div
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Figure 5-6. Start-up 2: VIN=15 V, IVDD-VEE=68 mA, (top: VDD-VEE, 10 V/div, mid-1: COM-VEE, 2 V/div,
mid-2: VDD-COM, 10 V/div, bot: VEE-COM, 5 V/div), time = 1 ms/div
Figure 5-7. Start-up 3: VIN=15 V, IVDD-VEE=68 mA, (top: VDD-VEE, 10 V/div, mid-1: COM-VEE, 2 V/div,
mid-2: VDD-COM, 20 V/div, mid-3: VEE-COM, 5 V/div, mid-4: EN, 5 V/div, bot: /PG, 5 V/div), time = 1
ms/div, EN to /PG delay = 4.6 ms
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Figure 5-8. Start-up 4: VIN=15 V, IVDD-VEE=68 mA, (top: VDD-VEE, 10 V/div, mid-1: COM-VEE, 2 V/div,
mid-2: VDD-COM, 20 V/div, mid-3: VEE-COM, 5 V/div, mid-4: EN, 5 V/div, bot: /PG, 5 V/div), time = 1
ms/div, Reg to /PG delay = 2.07 ms
5.5 Inrush Current
Inrush current measurement made with VIN applied and toggle EN pin. This makes sure the input capacitors are
pre-biased to VIN and make negligible contribution to the measured inrush current. Inrush current is measured
by connecting a current probe to the positive connecting cable between the input supply voltage and the EVM,
J4 terminal block.
Figure 5-9. Inrush Current 1: VIN=15 V, IVDD-VEE=68 mA, (top: VDD-VEE, 10 V/div, mid-1: COM-VEE, 2
V/div, mid-2: VDD-COM, 20 V/div, mid-3: VEE-COM, 5 V/div, mid-4: IIN, 1 A/div, bot: /PG, 5 V/div), time = 1
ms/div
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Figure 5-10. Inrush Current 2: VIN=15 V, IVDD-VEE=0 mA, (top: VDD-VEE, 10 V/div, mid-1: COM-VEE, 2
V/div, mid-2: VDD-COM, 20 V/div, mid-3: VEE-COM, 5 V/div, mid-4: IIN, 1 A/div, bot: /PG, 5 V/div), time =1
ms/div
Figure 5-11. Inrush Current 3: VIN=15 V, IVDD-VEE=0 mA, (top: VDD-VEE, 10 V/div, mid-1: COM-VEE, 2
V/div, mid-2: VDD-COM, 20 V/div, mid-3: VEE-COM, 5 V/div, mid-4: IIN, 1 A/div, bot: /PG, 5 V/div, zoom: 250
mA/div), time =1 ms/div, time_zoom=200 µs/div
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5.6 AC Ripple Voltage
Figure 5-12. AC Ripple 1: VDDAC=290 mV, VEEAC=90 mV, IVDD=68 mA, IVEE=0 mA (top: VDD-VEE, 200
mV/div, bot: COM-VEE, 50 mV/div), time = 100 ms/div
Figure 5-13. AC Ripple 2: VIN=15 V, IVDD=68 mA, IVEE=0 mA, (top: VDD-VEE, 100 mV/div, bot: COM-VEE,
50 mV/div), time = 20 µs/div
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Figure 5-14. AC Ripple 3: VIN=15 V, IVDD=68 mA, IVEE=0 mA, FMOD=33 kHz, (top: VDD-VEE, 100 mV/div,
bot: COM-VEE, 50 mV/div), time =10 µs/div
Figure 5-15. AC Ripple 4: VIN=15 V, IVDD=68 mA, FSW(PRI)=14.53 MHz, (top: VDD-VEE, 100 mV/div, bot:
COM-VEE, 50 mV/div, Zoom: VDD-VEE, 13.6 mV/div), time =10 µs/div, time_zoom=50 ns/div
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Figure 5-16. AC Ripple 5: VIN=15 V, IVDD=68 mA, FBURST=1 MHz, (top: VDD-VEE, 100 mV/div, bot:
COM-VEE, 50 mV/div, Zoom: VDD-VEE, 10 mV/div), time =10 µs/div, time_zoom=150 ns/div
5.7 EN-to-/PG Timing
Figure 5-17. ENA to /PG Delay, 4.6 ms, VIN=15 V, IVDD-VEE=68 mA, (top: VDD-VEE, 10 V/div, mid-1: COM-
VEE, 2 V/div, mid-2: VDD-COM, 20 V/div, mid-3: VEE-COM, 5 V/div, mid-4: EN, 5 V/div, bot: /PG, 5 V/div),
time = 1 ms/div
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