Texas Instruments TPSF12C1EVM-FILTER User manual

EVM User's Guide: TPSF12C1EVM-FILTER
Active EMI Filter Evaluation Module for Single-Phase AC
Power Systems
Description
The TPSF12C1EVM-FILTER evaluation module
(EVM) is specifically designed to validate the
performance of the TPSF12C1 power-supply filter
IC. The active EMI filter (AEF) helps to improve
the common-mode (CM) electromagnetic interference
(EMI) signature in single-phase AC power systems by
amplification of the effective Y-capacitance value.
Get Started
1. Order the TPSF12C1EVM-FILTER EVM
2. Study this EVM user's guide and PCB layout files
3. Use the TPSF12C1 quickstart calculator to assist
with EMI filter design and component selection
4. Prior to connecting the power stage, test the
active filter circuit with a low-voltage signal source
5. Connect the filter to an AC-input power stage and
verify the INJ voltage swing is within limits
6. Measure the total (DM and CM) EMI signature
and use a splitter to isolate the CM contribution
Features
• Improved CM EMI performance for applications
with single-phase AC input
– Voltage-sense, current-inject AEF topology
presents low shunt impedance by amplifying
the effective value of Y-capacitance
• Up to 30 dB reduction in the CM EMI
signature from 100 kHz to 3 MHz
– A higher effective Y-capacitance enables a
reduction in CM choke size, weight and cost
• Simple configuration for single-phase AC systems
– Integrated sensing filter and summing network
– Low Y-capacitor line-frequency leakage current
to chassis ground maintains safety
– Simplified compensation network
• Inherent protection features for reliable design
– Withstands 6-kV+ surge with minimal external
component count
• Helps meet IEC 61000-4-5 surge immunity
system-level specification
• Integrated SENSE input surge protection
– Wide VDD supply voltage range of 8 V to 16 V
• Undervoltage lockout (UVLO) set to turn on
and off at 7.7 V and 6.7 V, respectively
• The EVM includes a high-PSRR LDO for
step-down regulation to 12 V (if needed)
– 175°C thermal shutdown protection
– Integrated VDD-to-EN pullup allows use of an
open-drain/collector device for disable function
• Fully assembled, tested and proven two-layer PCB
design with 5" × 3" (127 mm × 76 mm) total area
Applications
•On-board charger for BEVs and PHEVs
•Power delivery – high-density server rack PSUs
•Welders and other industrial systems
•Telecom AC/DC rectifiers
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Active EMI Filter Evaluation Module for Single-Phase AC Power Systems 1
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1 Evaluation Module Overview
1.1 Introduction
The TPSF12C1EVM-FILTER evaluation module (EVM) is designed to conveniently evaluate the performance
of the TPSF12C1 active filter IC. The EVM helps to improve the CM EMI signature in single-phase AC power
systems.
The TPSF12C1 provides a low shunt impedance path for CM noise in the frequency range of interest for EMI
measurement and helps to meet prescribed limits for EMI standards, such as:
• CISPR 11, EN 55011 – Industrial, Scientific and Medical (ISM) applications
• CISPR 25, EN 55025 – Automotive applications
• CISPR 32, EN 55032 – Multimedia applications
Enabling up to 30 dB of CM noise reduction at the lower end of specified frequency ranges (for example, 100
kHz to 3 MHz) significantly reduces the footprint, volume, weight and cost of the CM filter implementation,
especially the CM choke components that are designed to attenuate lower-order harmonics – and hence are
large size. The TPSF12C1 senses the high-frequency noise on each power line using two Y-rated sense
capacitors and injects a noise-canceling current back into the power lines using a Y-rated inject capacitor. The
GND terminal of the EVM requires a direct, low-inductance connection to the chassis ground or Earth terminal of
the filter circuit.
1.2 Kit Contents
• A complete filter board (EVM) rated at 10 A, including the TPSF12C1 active EMI filter IC
• EVM Disclaimer Read Me
• High Voltage Read Me
1.3 Specifications
Table 1-1 lists the EVM specifications. The input accepts 120 VAC or 240 VAC standard single-phase mains
supply voltages. VVDD = 12 V, unless otherwise indicated.
Table 1-1. Electrical Performance Specifications
PARAMETER CONDITIONS MIN TYP MAX UNIT
INPUT CHARACTERISTICS – EMI FILTER BOARD
Filter input voltage, VAC 85 240 265 VRMS
Filter rated current, IAC 10 ARMS
INPUT CHARACTERISTICS – TPSF12C1 AEF IC
VDD supply voltage, VVDD (1) 8 12 16
VVDD UVLO turn-on threshold, VVDD(on) VVDD rising 7.7
VDD UVLO turn-off threshold, VVDD(off) VVDD falling 6.7
VDD supply current, enabled, IVDD(on) EN open or tied high 12.5 mA
VDD supply current, disabled, IVDD(off) EN tied to GND 50 µA
OUTPUT CHARACTERISTICS – TPSF12C1 AEF IC
Inject voltage, VINJ (2) 2.5 VVDD – 2 V
Inject current, IINJ VVDD = 8 V to 16 V –80 80 mA
SYSTEM CHARACTERISTICS
Common-mode EMI reduction(3) 150 kHz to 1 MHz 20 dB
Ambient temperature, TA–40 85 °C
IC junction temperature, TJ–40 150
(1) The nominal VDD supply voltage (relative to chassis GND) of the TPSF12C1 is 12 V.
(2) Verify that the INJ pin voltage swing is between the prescribed limits to avoid saturation and clipping.
(3) The expected EMI reduction with this EVM is up to 30 dB (with the TPSF12C1 enabled vs. disabled) when swept from 100 kHz
to 3 MHz. This performance metric can change based on the VDD supply voltage, passive filter component values, active circuit
compensation and damping component values, ambient temperature, and other parameters.
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1.4 Device Information
CM filters for both commercial (Class A) and residential (Class B) environments typically have limited Y-
capacitance due to touch-current safety requirements and, thus require large-sized CM chokes to achieve the
requisite attenuation; ultimately resulting in filter designs with bulky, heavy and expensive passive components.
The deployment of active filter circuits enable more compact filters for next-generation power conversion
systems.
The EVM, a practical filter circuit realization for a single-phase power system, showcases the EMI performance
improvement or size reduction achievable with the TPSF12C1, a single-phase power-supply filter IC.
The circuit advantages summarize as:
1. Simple filter structure – with wide operating frequency range and high stability margins
2. Reduced CM choke size – for lower volume, weight and cost. This also enables much less copper loss and
better high-frequency performance due to lower choke self-parasitics and higher self-resonant frequency
3. No additional magnetic components – only uses Y-rated sense and inject capacitors with minimal impact to
peak touch current (measured according to IEC 60990)
4. Enhanced safety – using a low-voltage AEF IC referenced to chassis ground
5. Standalone AEF IC implementation – enables maximum flexibility in terms of placement near the filter
components
6. Surge immunity – robust to line voltage surges to meet IEC 61000-4-5 (with appropriate voltage clamping
internal or external to the IC).
Note
The damping and compensation component values included with this EVM can require modification
if the passive filter components (the CM chokes in particular) are changed. Refer to the TPSF12C1
Standalone Active EMI Filter for Common-mode Noise Mitigation in Single-Phase AC Automotive
Power Systems data sheet and TPSF12C1 quickstart calculator for additional guidance pertaining to
AEF circuit operation and loop gain, passive component selection and expected EMI performance.
CAUTION
Hot surface. Contact can cause burns. Do not touch.
CAUTION
High Voltage. Risk of electric shock.
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General Texas Instruments High Voltage Evaluation (TI HV EVM) User Safety Guidelines
WARNING
Always follow TI's set-up and application instructions, including use of all interface components within their
recommended electrical rated voltage and power limits. Always use electrical safety precautions to help ensure
your personal safety and those working around you. Contact TI's Product Information Center http://ti.com/
customer support for further information.
Save all warnings and instructions for future reference.
WARNING
Failure to follow warnings and instructions can result in personal injury, property damage or death
due to electrical shock and burn hazards.
The term TI HV EVM refers to an electronic device typically provided as an open framed, unenclosed printed
circuit board assembly. It is intended strictly for use in development laboratory environments, solely for qualified
professional users having training, expertise and knowledge of electrical safety risks in development and
application of high voltage electrical circuits. Any other use and/or application are strictly prohibited by Texas
Instruments. If you are not suitably qualified, then immediately stop from further use of the HV EVM.
1. Work Area Safety:
a. Keep work area clean and orderly.
b. Qualified observers must be present anytime circuits are energized.
c. Effective barriers and signage must be present in the area where the TI HV EVM and the interface
electronics are energized, indicating operation of accessible high voltages can be present, for the
purpose of protecting inadvertent access.
d. All interface circuits, power supplies, evaluation modules, instruments, meters, scopes, and other related
apparatus used in a development environment exceeding 50Vrms/75VDC must be electrically located
within a protected Emergency Power Off EPO protected power strip.
e. Use stable and non-conductive work surface.
f. Use adequately insulated clamps and wires to attach measurement probes and instruments. No
freehand testing whenever possible.
2. Electrical Safety:
a. As a precautionary measure, a good engineering practice is to assume that the entire EVM has fully
accessible and active high voltages.
b. De-energize the TI HV EVM and all the inputs, outputs and electrical loads before performing any
electrical or other diagnostic measurements. Revalidate that TI HV EVM power has been safely de-
energized.
c. With the EVM confirmed de-energized, proceed with required electrical circuit configurations, wiring,
measurement equipment hook-ups and other application needs, while still assuming the EVM circuit and
measuring instruments are electrically live.
d. Once EVM readiness is complete, energize the EVM as intended.
WARNING
While the EVM is energized, never touch the EVM or the electrical circuits, as the ciruits can
be at high voltages capable of causing electrical shock hazard.
3. Personal Safety
a. Wear personal protective equipment e.g. latex gloves or safety glasses with side shields or protect EVM
in an adequate lucent plastic box with interlocks from accidental touch.
Limitation for safe use:
EVMs are not to be used as all or part of a production unit.
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2 Hardware
2.1 EVM Description
The TPSF12C1EVM-FILTER can be used for evaluation and for system development of an EMI filter circuit and
application. Figure 2-1 presents typical schematics of equivalent single-phase passive and active filter designs –
with the active circuit component values corresponding to this EVM. Terminals designated L, N and PE refer to
live, neutral and protective earth, respectively. Comparing the passive and active circuits in this example, the CM
inductance of chokes LCM1 and LCM2 reduces from 12 mH to 2 mH by virtue of the higher effective Y-capacitance
with AEF.
RG
CG1
IGND
VDD
INJ
EN
COMP1
SENSE1A
SENSE2A
COMP2
REFGND
CINJ
CSEN1
CSEN2
LCM1 LCM2
AC/DC
regulator
Chassis
CG2
CD1
RD2
CD2
RD3
CD3
CVDD
12 V
RD1
RD1A
SENSE1B
SENSE2B
AC
source
L
N
PE
TPSF12C1
CY3 CY4
DINJ
LCM1 LCM2
AC/DC
regulator
Chassis
AC
source
L
N
PE
CY3 CY4 CY5 CY6
4-6 times
lower
inductance
4-6 times
lower
inductance
Passive filter circuit
Active filter circuit
CX2 CX3
CX1
CX2 CX3
CX1
CY1 CY2
CY1 CY2
12 mH
2.2 F
2.2 nF
4.7 nF
680 pF 680 pF
2.2 F2.2 F
2.2 nF 2.2 nF 2.2 nF 2.2 nF 2.2 nF
12 mH
2 mH
2.2 F
2.2 nF
2.2 F2.2 F
2.2 nF 2.2 nF 2.2 nF
2 mH
Figure 2-1. Passive and Active Filter Schematics
The AEF circuit uses a capacitive multiplier circuit in place of the two Y-capacitors normally placed between
the CM chokes in a conventional two-stage passive filter design. The TPSF12C1 senses the high-frequency
CM disturbance on the two power lines using two Y-rated sense capacitors and injects a noise-canceling
current back into the power lines using a Y-rated inject capacitor. The X-capacitor placed between the two
CM chokes provides a low-impedance path between the power lines from a CM standpoint, typically up to
low-MHz frequencies. This allows current injection onto one power line (neutral in this case) using only one inject
capacitor.
Acting as a complete filter with features such as surge immunity protection and X-capacitor resistive discharge,
the EVM uses a recommended PCB layout to minimize the overall noise signature and required board area. If
required, the user can add external components for inrush limiting and fuse protection.
2.2 Setup
Figure 2-2 shows a typical EMI measurement setup. A line impedance stabilization network (LISN) in series with
each supply line enables measurement of the total EMI that includes DM and CM propagation components. A
splitter/combiner can be used to extract the DM and CM noise signatures from the total noise measurement.
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Load
L
N
DM loop area
CM loop area
VCM
+
–
iDM
+
–VDM
Ground Reference Plane
iDM
iCM
iCM /2
iCM /2
CM loop
EMI
filter
AC/DC
switching
regulator
(EMI source)
VOUT+
VOUT–
LISN
EMI
receiver
LISN
V1
V2
Chassis
Y caps
tied to
chassis
GND
Chassis bonded
to the GND plane
VSW The load may
be floating or
tied to chassis
GND for safety
LISNs are
bonded to the
GND plane
VDM = V1– V2
VCM = V1+ V2
2
PE
Figure 2-2. EMI Measurement Setup for a Single-Phase System
The AC/DC regulator has internal high-dv/dt switching nodes that can capacitively couple CM noise to the
chassis. As such, verifying the Y-capactiors in the EMI filter are closely referenced to the chassis is imperative,
as illustrated in Figure 2-2. The Y-capacitors can then return the CM noise current back to the noise source in
a tight conduction loop. Otherwise, the noise current can flow in the reference ground plane back to the LISNs,
rendering the EMI filter less effective.
Figure 2-3 shows the recommended setup to evaluate the performance of the TPSF12C1 with a power stage
connected.
VDD
NC
COMP1
COMP2
IGND
INJ
NC
EN
NC
REFGND
SENSE1A
SENSE1B
SENSE2A
SENSE2B
AC Mains
Chassis (PE)
Interleaved boost PFC
To enable the IC, leave EN open or
connect it to VDD using a jumper
Chassis-referred VDD bias supply = 12 V
CSEN2 CINJ CSEN1
S2 S1 INJ VDD
EN
J1
CY3 CY4
CX2 CX3
CX1
LCM1
= AC/DC regulator
= Single-phase AEF IC
= Y-rated sense and inject capacitors
= 6-pin header
CY1 CY2
Chassis
(PE)
Chassis (PE)
Filter board EVM with AEF
TPSF12C1
U1
RD1A
RD1
RD3
CD3
CD1
CD2
RD2
RG
CG1
CG2
D1
Dual
LISN
GND
= Dual LISN for EMI measurement
LCM2
LISNs bonded
to the Ground
Reference
Plane for EMI
measurement
2.2 mH2.2 mH
2.2 F 2.2 F
2.2 F
2.2 nF 2.2 nF
2.2 nF 2.2 nF 4.7 nF
680 pF 680 pF
CVDD
L
N
Figure 2-3. EVM Setup Schematic for High-Voltage Testing with AC/DC Power Stage Connected
A two-phase interleaved boost PFC topology in Figure 2-3 represents a typical single-phase AC/DC regulator
and is drawn for illustrative purposes. The setup is essentially agnostic to regulator topology.
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Meanwhile, Figure 2-4 shows a schematic that is designed for low-voltage testing of the active filter design,
including insertion loss measurement and EMI performance characterization. This facilitates an easy and
convenient verification of the active filter circuit prior to connection to a high-voltage switching regulator. A good
signal source and coupling capacitor provide CM excitation that mimics the CM noise source voltage and noise
source impedance related to the switch-node behavior of an actual power stage.
VDD
NC
COMP1
COMP2
IGND
INJ
NC
EN
NC
REFGND
SENSE1A
SENSE1B
SENSE2A
SENSE2B
Chassis (PE)
To enable the IC, leave EN open
Chassis-referred VDD bias power = 12 V
CSEN2 CINJ CSEN1
S2 S1 INJ VDD
EN
J1
CY3 CY4
CX2 CX3
CX1
LCM1
= Single-phase AEF IC
= Y-rated sense and inject capacitors
= 6-pin header
CY1 CY2
Chassis
(PE)
Chassis (PE)
Filter board EVM with AEF
TPSF12C1
U1
RD1A
RD1
RD3
CD3
CD1
CD2
RD2
RG
CG1
CG2
D1
Dual
LISN
GND
= Dual LISN for EMI measurement
LCM2
LISNs bonded
to the Ground
Reference
Plane for EMI
measurement
2.2 mH2.2 mH
2.2 F 2.2 F
2.2 F
2.2 nF 2.2 nF
2.2 nF 2.2 nF 4.7 nF
680 pF 680 pF
CVDD
CSRC
1 nF
L
N
Square-wave
CM excitation source
5 V pk-pk, 100 kHz
22% duty cycle
L’
N’
Figure 2-4. EVM Setup Schematic for Low-Voltage Testing
2.3 Header Information
Table 2-1, Table 2-2 and Table 2-3 detail the various signal headers installed on the EVM. In addition, SMB jacks
designated J2, J3 and J4 on the PCB facilitate oscillator signal injection and frequency sweep for measurement
of filter insertion loss or attenuation.
Header J1 specifically provides connections to the low-voltage side of the sense capacitors (corresponding to
the SENSE pins of the TPSF12C1), the low-voltage side of the inject capacitor, the IC bias power supply (VDD
and GND pins), which is set between 8 V and 16 V, and a remote enable (EN) signal.
Table 2-1. J1 Header Connections
POSITION(1) LABEL DESCRIPTION
1 EN Enable input – leave open or tie high to enable the IC; tie to GND to disable
2 VDD Supply voltage connection – connect to a 12-V bias power supply referenced to GND(2)
3 INJ Low-voltage terminal of the Y-rated inject capacitor, C10. Also connects to the AEF damping network
4 GND Ground – connect to the chassis ground of the system with a direct, low-inductance connection
5 S1 Low-voltage terminal of sense capacitor, C9. Also connects to the SENSE1A and SENSE1B pins of the IC
6 S2 Low-voltage terminal of sense capacitor, C8. Also connects to the SENSE2A and SENSE2B pins of the IC
(1) Pin positions of header J1 are designated right to left when viewed from the top side of the EVM.
(2) Working at an ESD-protected workstation, verify that any wrist straps, bootstraps or mats are connected and referencing the user to
earth ground before power is applied to the EVM.
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Table 2-2. J7 Header Connections
POSITION LABEL DESCRIPTION
1 VDD Connect a low-noise external source (8 V to 16 V) between the VDD and GND terminals
2 GND Connected by a trace on the PCB to GND
3 LDO Connect an external source (maximum 36 V) between the LDO and GND terminals to supply the on-board
LDO that outputs a regulated 12 V to VDD
Table 2-3. J8 Header Connections
POSITION LABEL DESCRIPTION
1 ON Connected by a trace on the PCB to VDD
2 EN Jumper EN to ON or OFF to enable and disable the TPSF12C1, respectively
3 OFF Connected by a trace on the PCB to GND
2.4 EVM Performance Validation
1. Apply a bias supply voltage of 8 V to 16 V (nominal 12 V, with ripple voltage less than 20 mV peak-to-peak)
between the VDD and GND terminals of J7. Probe the INJ terminal at header J1 with respect to GND; it
should operate at a DC voltage of VVDD/2 and have no AC perturbations that indicate instability. The VDD
current consumption should be approximately 12 mA.
2. The user should perform low-voltage testing prior to connection to a high-voltage power stage. To provide
CM excitation, connect a 5-V peak-to-peak square-wave source from a function generator on the regulator-
side power connector J6, as shown in Figure 2-4. A 1-nF capacitor in series with the source emulates a
practical CM noise source impedance.
• Using the CM excitation source, verify the dynamic voltage range of the TPSF12C1 INJ pin. Ensure that
the INJ pin voltage relative to GND operates in a window between 2.5 V and VVDD – 2 V.
3. Connect a LISN on the input side at J5 and measure the EMI with AEF disabled (EN jumpered to OFF at
J8) to benchmark the existing passive filter. The bottom terminal of inject capacitor can be shorted to GND
when AEF is disabled by tying the INJ terminal of J1 to GND. This emulates the Y-capacitor connection in an
equivalent passive filter design.
4. Remove the pulldown short on the inject capacitor and enable the AEF circuit by allowing the EN to float
high. Repeat the EMI measurement, thus quantifying the EMI reduction related to AEF circuit operation.
5. In a similar fashion (but with the LISN replaced by a 50-Ω load connecting from L and N to GND), perform a
comparison of filter insertion loss performance using a suitable network analyzer. SMB jacks J2, J3 and J4
on the EVM facilitate signal injection, reference measurement and test measurement, respectively.
6. Using high-voltage safety precautions, connect the switching power stage as shown in Figure 2-3.
Depopulate components R1, R2 and C20 to maximize the clearance spacing from high-voltage nodes to
ground adjacent the SMB jacks. Turn the regulator ON and perform EMI measurements with AEF enabled
and disabled, similar to the procedure outlined in steps 3 and 4 above.
7. Turn the regulator OFF. Wait for all high-voltage capacitors to fully discharge.
8. Power down the IC and remove the VDD supply.
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2.5 AEF Design Flow
Follow these steps to design an active filter circuit:
1. Quickstart Calculator – Use the TPSF12C1 quickstart calculator as a convenient starting point. See Figure
2-5 for illustration.
Figure 2-5. Quickstart Calculator With CM Choke Impedance, Loop Gain and Insertion Loss Plots
Typical steps to complete the quickstart calculator are as follows:
• Choose the core material for the CM chokes – the primary choices being nanocrystalline (NC) or ferrite.
NC chokes are preferable for active filter designs given their higher permeability (and thus fewer winding
turns), broader impedance characteristic over frequency, more damped impedance behavior with softer
phase transition, and better stability over temperature.
• Define the CM choke impedances – two options are available:
– Measure the CM impedance magnitude and phase vs. frequency using a network analyzer. Paste the
data directly into the calculator file.
– Enter the behavioral model parameters for each choke based on (a) a parallel LRC circuit for a ferrite
choke (LCM || RPAR || CPAR), or (b) a ladder network for an NC choke consisting of three parallel RL
circuits connected in series along with a parasitic capacitance across the total network. An equivalent
circuit model is the most convenient option if the choke data sheet includes the CM impedance data.
• Enter values for the grid-side and regulator-side Y-capacitors, sense capacitors and inject capacitor.
• Enter values for source impedance of the grid supply and the noise source. Select from a drop-down
menu if a LISN (50 µH or 5 µH) is installed.
• Review the AEF loop gain plot for stability based on the calculated component values for the damping
network. Adjust the damping network values to ensure the phase does not reach –180° at the resonant
frequencies (when the gain is positive). Refer to the TPSF12C1 data sheet for guidance on component
selection. Check the insertion loss plots with AEF enabled and disabled.
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2. Circuit Simulation – Avail of PSPICE or SIMPLIS simulation models for the TPSF12C1 device. Use such
models along with prepared test benches to investigate the operation of the complete active filter circuit.
See the SIMPLIS schematic in Figure 2-6 as an example. Perform both time-domain and frequency-domain
analyses as required.
Figure 2-6. SIMPLIS Simulation Schematic of an Active Filter Circuit Using the TPSF12C1
Note that the CM choke model schematics are not shown above. If the choke model equivalent circuit
parameters are defined in the quickstart calculator, transfer them directly to the simulation model as needed.
3. Low-Voltage Tests – Validate the filter design at low voltage prior to connecting to the switching regulator.
This is a relatively easy step to confirm various aspect of the design, including filter stability, insertion loss,
voltage swing on the INJ pin, and EMI performance with CM signal excitation. See Figure 2-4 and refer to
tests 4 through 7 described in Section 2.4.
• Insertion loss – measure with 50-Ω source and load impedances.
• Apply a CM excitation signal with a function generator.
– Check the dynamic voltage range of the INJ pin (TPSF12C1 pin 13).
– Measure the EMI (CM only, there is no DM propagation in this test).
4. High-Voltage Tests – Validate the filter design while connected to the switching regulator. See Figure 2-3
and refer to tests 8 and 9 described in Section 2.4.
• Check the dynamic voltage range of the INJ pin.
• Calculate the device power dissipation based on VVDD, IVDD, TA and RθJA. Verify that the maximum
junction temperature is less than 150°C under the worst case operating conditions.
• Check the sense and inject capacitance variation over temperature and ensure the circuit is stable under
all operating conditions.
• Measure the total EMI. Separate the CM (asymmetrical) and DM (symmetrical) propagation components,
as the TPSF12C1-based AEF circuit only attenuates the CM noise.
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