Texas Instruments LOG200EVM User manual

EVM User's Guide: LOG200EVM LOG200
LOG200 Evaluation Module
Description
The LOG200 evaluation module (EVM) is a
development platform for evaluating the LOG200,
which is a precision, high-speed logarithmic amplifier
with integrated photodiode bias and dark current
correction. The LOG200 is optimized for current
measurements across 160 dB wide dynamic range,
over several decades with unparalleled speed and
accuracy.
Features
• High-accuracy logarithmic transfer function
• Logarithmic ratio internally set to 250 mV/decade
of current-to-voltage conversion
• Footprint for photosensor connection
• Integrated photodiode bias and dark current
correction adaptive biasing circuit
• Integrated precision 1 µA current reference
• Integrated precision 1.65 V and 2.5 V voltage
references
• Single supply (+5 V) or dual supply (±5 V)
operation
• Sub-miniature version A (SMA) connectors and
test points allow for quick tests
Applications
•Optical modules
•Inter_DC interconnect
•Optical network terminal unit
•Chemistry/gas analyzer
LOG200EVM Hardware Board
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1 Evaluation Module Overview
1.1 Introduction
The LOG200EVM is the evaluation module (EVM) for the LOG200 precision, high-speed logarithmic amplifier.
The device features two logarithmic amplifiers followed by a high-accuracy differential amplifier to convert
current signals into a single-ended voltage that represents the log-compressed ratio of the two currents. The log
amplifier ratio is internally set to 250 mV/decade of current-to-voltage conversion.
The LOG200 device integrates an uncommitted high-speed amplifier to allow the output to be configured for
differential or filtered responses.
The LOG200EVM operates over a 4.5 V to 12 V range unipolar supply or dual supply of ±2.25V to ±6 V supply.
See Table 2-2 for details. SMA and Test points provide convenient access to all critical functions of the LOG200.
For a full schematic of the LOG200EVM, see Figure 3-1.
1.2 Kit Contents
Table 1-1. LOG200EVM Kit Contents
Item Description Quantity
LOG200EVM PCB 1
1.3 Specification
The LOG200EVM offers the following features:
• The evaluation board enables users to connect the LOG200 to current sources through SMA connections via
series resistors.
• The PCB includes a footprint to mount an optional photodiode to the INUM input for optical power
measurement applications. The photosensor can be biased externally through a test point, or through the
use of the LOG200 IBIAS adaptive biasing current output function by modifying the EVM.
• Allows access to the integrated precision 1 µA current reference
• Allows the use of the Integrated precision 1.65 V and 2.5 V voltage references in different circuit
configurations
• The LOG200EVM provides access to the inputs and output of the secondary op-amp. The PCB provides
optional passive component footprints to support different op-amp or filter configurations.
1.4 Device Information
The EVM is built with the LOG200IRGT device in the 16-pin QFN package with the thermal pad.
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2 Hardware
2.1 Read this first: EVM Cleaning Guidelines
Logarithmic amplifier applications requiring picoampere range performance are very sensitive to PCB board
contamination. Contaminants in the form of solder flux, oils and other impurities can form conductive paths
over the sensitive PCB traces that allow small currents to leak from the input traces or other sensitive nodes,
degrading performance. For best performance, make sure to keep the LOG200EVM as clean as possible. The
following list shows best practices to clean the evaluation board and to help prevent the EVM from becoming
contaminated:
• Leakage currents from solder flux contamination can disturb the logarithmic amplifier's operation, specially at
lower current levels. The LOG200EVM undergoes a standard cleaning protocol after the fabrication, soldering
and assembly process prior shipping to customers, providing picoampere level performance. The EVM must
be re-cleaned anytime devices are soldered into the PCB or modified near the logarithmic amplifier sensitive
nodes, if the LOG200 U1 device is replaced, or if these input sensitive connections become contaminated by
other means.
• The recommended cleaning procedure requires access to an ultrasonic deionized (DI) water bath:
– Place the EVM in the ultrasonic cleaner and fill with fresh deionized (DI) water.
– Run the ultrasonic cleaner for 20 minutes at 45°C.
– Remove all moisture from PCB.
• If an ultrasonic bath is not available, then a manual cleaning procedure is possible:
– Scrub contaminants from the top layer I1 and I2 inputs at top layer.
– Use a toothbrush to gently scrub for 60 seconds. Focus on areas surrounding U1 I1, I2, VCM, and IREF
inputs, R9, R13, R16, R17, R35, D1, input SMA connectors J4 and J6 and guard traces.
– Scrub contaminants from the bottom layer around the diode D1 photosensor footprint and input SMA
connectors J4 and J6.
– Flush the scrubbed areas with fresh DI water, tilting the board to allow runoff to flow away from the input
areas.
– Remove all moisture from PCB.
• When handling the EVM, always hold the board by the edges.
• When not in use, place the EVM in ESD bag or other enclosure to prevent dust and other contaminants from
settling on the board.
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2.2 Input and Output Connections
The current input signals for the logarithmic numerator, I1, and logarithmic denominator, I2, are provided through
SMA connectors J4 and J6. These inputs are located at the left of the EVM. The input connections of the log
amplifier have a series 10 kΩ resistors, R9 and R10. The logarithmic output connection is provided through SMA
J5 and test point TP4 at the right side of the EVM.
The secondary op-amp inputs are accessible through SMA J14 and the output amplifier connection is provided
through SMA connector J14, and test point TP16, located at the right side of the EVM. For a full schematic of the
LOG200EVM, see Figure 3-1 and Figure 3-2.
Table 2-1 summarizes the input and output connectors and corresponding test points.
Table 2-1. LOG200EVM Input and Output Connections
Designator Signal Connector Type Description
J4 I1_IN SMA Current input for logarithm numerator
J6 I1_IN SMA Current input for logarithm denominator
J5 OUT_A SMA Logarithm function voltage output
J13 IN_AMP_B SMA Secondary op-amp voltage non-inverting
and inverting input
J14 OUT_B SMA Secondary op-amp voltage output
J16 REF_GND Banana plug Optional ext voltage reference negative
J10 Ext_RefA Banana plug Optional ext Logarithm function voltage
output reference
J12 GND Banana plug EVM PCB ground
TP1 DBIAS Test point Optional ext Photodiode Vbias Cathode
TP4 OUT_A Test point Logarithm function voltage output
TP16 OUT_B Test point Secondary op-amp voltage output
TP11 VCM Test point Input common-mode voltage
TP14 REF1 Test point REF25: 2.5V reference output
TP15 REF2 Test point REF165: 1.65V reference output
TP18 REF_GND Test point Voltage reference negative
TP2, TP3,
TP8, TP12,
TP17
GND Test point EVM PCB ground
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2.3 Power Requirements
The power-supply connections for the LOG200EVM are provided through standard banana jack connectors J1,
J2, and J3 at the top of the EVM. The LOG200EVM can be set up with a single unipolar supply or with dual
bipolar supplies by setting jumper J9. Table 2-2 summarizes the pin definition for supply connector J1, J2, and
J3 and the allowed voltage range for each supply connection when configured with either unipolar or bipolar
supplies.
Table 2-2. LOG200EVM Supply-Range Specifications
Connector
Number
Supply Connection Voltage Range
J1 (V+) supply Unipolar: +4.5 V to +12 V
Bipolar: +2.25 V to +6 V
J2 Ground 0 V
J3 (V-) Supply Unipolar: Do not Connect
Bipolar: –2.25 V to –6 V
The EVM is configured by default using bipolar supply by opening jumper J9. To configure the device with
unipolar supply, set jumper J9 to shunt pin 1–2.
Figure 2-1 shows the J1, J2, and J3 standard banana supply connectors, and jumper J9 configuration.
J3
J2
GND
J1
VS+
VS+
10µF
C6 C5
TP5
VS+
12V
D3
VS+
VS+
12V
D2
GND
12V
D4
LOG200
+
–
+
–
+
–
+
–
+
–
PD
BIAS
+
–
1µA
2.5V 1.65V
VS+
C7
100 nF
C11
100 nF
VS–
C8
100 nF
I1
I2
VCM
IBIAS
IN– IN+
VS+
OUTB
OUTA
REFA
IREF REF25 REFGND REF165
TP6
VS–
VS–
R4
10.0 
R5
10.0 
10µF
VS–
VS–
VS–
PAD
Thermal Pad
Connected to
VCM
1
2
J9
VS–
Power-Supply
Connector
Jumper J9
Shunt 1-2 for Unipolar Supply
Open 1-2 for Bipolar Supply
VS–
Shunt
GND
TP9
Figure 2-1. LOG200EVM Voltage Supply Connections
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2.4 Jumper Information
Figure 2-2 details the default jumper settings of the LOG200EVM. Table 2-3 explains the configuration for these
jumpers.
Figure 2-2. LOG200EVM Default Jumper Settings
Table 2-3. Default Jumper Configuration
Jumper Function Default Position Description
J7 Out_A
SMA J5 reference Shunt 2-3 Shunt 2-3: SMA connector J3 referred to GND
Shunt 1-2: SMA connector J3 referred to REFA
J8 VCM
Select Shunt 1-2 Shunt 1-2: VCM input connected to GND Shunt 3-4: Connects VCM input to 2.5V reference
J9 VS– connection Open
Open: Bipolar supply configuration
Shunt 1-2: Connects VS– to GND for unipolar supply
configuration
J11 REF A Select Shunt 7-8
Shunt 1-2: Sets log voltage REFA to external voltage through J10
Shunt 3-4: Sets REFA to REF25
Shunt 5-6: Sets REFA to REF165
Shunt 7-8: Sets REFA to GND
J15 Secondary
op-amp input Shunt 1-2 Shunt 1-2: Connects Aux AMP+IN to OUTA Shunt 3-4: Connects Aux AMP -IN to OUTA
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2.5 Optional Photodiode Connections
The LOG200EVM PCB board layout includes a photosensor footprint (D1) to install a radial photodiode on
current input I1 for the logarithmic numerator. See Figure 2-3 for the photosensor input and photosensor biasing
connections.
The photodiode IBIAS adaptive biasing current output is accessible through optional jumper resistor R2. The
adaptive current output biasing scheme creates a voltage to bias a photodiode with a current that is proportional
to the photocurrent. This allows small bias voltages for low photodiode currents, reducing the dark current of
the photodiode, and higher reverse-bias voltages as the photocurrent increases, reducing the capacitance of the
photodiode.
The IBIAS function produces a current that is approximately 1.1x larger than the numerator current I1. Since
the photosensor produces the input numerator current, the remaining 0.1*I1 current flows through the RBIAS
resistor R3. The RBIAS resistor R3 needs to be scaled depending on the photosensor biasing requirements, the
photosensor current range and the LOG200 supply voltage. The voltage at the IBIAS pin must not exceed (V+)
- 1 V at the photosensor maximum current. If the IBIAS function is not used, then leave the IBIAS pin floating by
removing resistor jumper R2.
Alternatively, the photosensor cathode can be reverse biased via test point TP1, DBIAS. Verify the resistor R2 is
removed when biasing the photosensor through TP1.
Capacitors C1 and C3 can help providing dynamic currents during fast transients and help to improve stability.
The value for best bias response depends on the photosensor and application requirements.
Figure 2-3 presents a simplified diagram of the photodiode connections. For a detailed schematic of the
photosensor connections, see Figure 3-1.
LOG200
+
–
+
–
+
–
+
–
+
–
PD BIAS
1.1x I1
+
–
1µA
2.5V 1.65V
I1
I2
VCM
IBIAS
IN– IN+
OUTB
OUTA
REFA
IREF
REF25 REFGND REF165
J6
SMA
Connector
I2_IN
R9
C1
VCM2
R16
0

R2 0

D1
RBIAS
R3
GND
C3
Photodiode
Guard
Guard
R1 TP1
DBIAS
Guard
C2
GND
C9
GND
1000 pF
1000 pF
PAD / VCM
J8
1
2
To
REF25
GND
3
4
Jumper J8
Shunt 1-2 VCM to GND
Shunt 3-4 VCM to 2.5V reference
Shunt
Figure 2-3. LOG200EVM Photodiode Connections
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3 Hardware Design Files
3.1 Schematics
Figure 3-1 and Figure 3-2 show the EVM schematics.
Pin1_I1
Pin2_Vcm
Pin3_I2
Pin4_Iref
Pin15_IBias
Pin16_Vcm2
Current Reference
Pin10_RefA
Pin11_OUTA
Vcm
Vcm
Vcm
GND
I1_IN
I2_IN
GND
GND
GND
GND Vcm
Vcm
GND GND
VCM
2
VCM2
16
REF25
5
REF165
9
VS+
8
VS- 7
IN+
14
IN-
13
I1
1
I2
3
IBIAS
15
IREF
4
OUTA 11
OUTB 12
REFA
10
Thermal_Pad
17
REFGND 6
LOG200RGT
U1
Pin1_I1
Pin2_Vcm
Pin3_I2
Pin4_Iref
Pin5_Ref25
Pin6_RefGND
VS-
VS+
Pin9_Ref165
Pin10_RefA
Pin11_OUTA
Pin12_OUTB
Pin13_-IN
Pin14_+IN
Pin15_IBias
Pin16_Vcm2
Pin17_Pad
GND
TP8
GND
TP12
GND
TP4
OUT_A1
R8
100
R6
TP10
REFA1
TP3
GND
0
R14
0
R10
1
2
3
4 5
J6
I2_IN
1
2 3
4
5
J4
I1_IN 1
2 3 4 5
J5
OUT_A1
TP1
DBias
GND
Vcm
R3
R11
Vcm
R15
OUTA
100V
100pF
C4
1 2
3
D1
TP2
GND
R1
Vcm
GND
GND
GND
0
R7
1000pF
50V
C9
Pin2_Vcm
C3C1
1000pF
50V
C2
1 2
3 4
J8
Vcm_Sel1
TP11
Vcm
Pin5_Ref25
R2
249
R31
R32
GND
0
R12
C18
GND
R35
C10
1
2
3
J7
OutA_Ref_conn
GND
10.0k
R9
10.0k
R13
0
R16
R17
Pin10_RefA Pin5_Ref25
Pin9_Ref165
Ext_RefA
J10
Ext_RefA1
TP14
Ref1
TP15
Ref2
1 2
3 4
5 6
7 8
J11
REFA_Sel
GND
REFA Diff Amp Select
LOG200
DNP
DNP
DNP
DNP
DNP
DNP
DNP DNP DNP
DNP
DNP
DNP
DNP
Note: DNP components are not populated.
Figure 3-1. LOG200EVM Schematic
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GND
VS-
1
2
J9
VS-_to_GND
Power Supplies
Pin17_Pad
Vcm
Voltage Reference Bypass Cap
Pin6_RefGND
GND
GND
GND
Pin9_Ref165
Pin5_Ref25
GND
Pin12_OUTB
Pin13_-IN
Pin14_+IN AMP_B
GND
AMPB_IN+
AMPB_IN-OUTA
LOG200 Operational Amplifier B
GND
GND
GND
GND
J3
VS-
J2
GND
J1
VS+
GNDVS+ VS-
TP5
VS+
VS+VS+
TP6
VS-
GND
VS+
VS-
TP9
GND
VS-GND
VS-
10.0
R4
10.0
R5
10uF
C5
GND
10uF
C6
GND
100nF
50V
C8
100nF
50V
C7
100nF
50V
C11
12V
D2
12V
D4
12V
D3
R19
0
R26
TP17
GND
TP16
OUT_B1
R28
100
R25
0
R24
J12
GND
20pF
C13
R23
0
R30
J16
Ref_GND1
TP18
Ref_GND1
J13
IN_AMP_B1
J14
OUT_B1
1 2
3 4
J15
INB_SEL1
1.00k
R21
1.00k
R20
1.00k
R27
R29
20pF
C16
AMPB_IN+
AMPB_IN-
100V
100pF
C15
100V
330pF
C12
100V
330pF
C14
0
R18
0
R22
R33
Pin9_Ref165
C17
1.00k
R34
DNP
DNP
DNP
DNP
DNP
DNP
Note: DNP components are not populated.
Figure 3-2. LOG200EVM Schematic
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3.2 PCB Layout
The LOG200EVM is a four-layer PCB design. Figure 3-3 to Figure 3-7 show the PCB layer illustrations.
The top layer routes the sensitive input current signal path traces. The logarithmic amplifier is optimized to
perform current measurements across several decades. At the low current level ranges, leakage current can
cause significant errors. To minimize leakage current paths, a complete guard ring is implemented with traces
that encircle the complete signal path of each high-impedance current input of the log amplifier. The guard
presents a low-impedance path for leakage currents of equal potential to the high-impedance traces that are
being guarded. The guard traces are driven to the input common-mode voltage (VCM); therefore, the current
flowing between the input current traces and the guard is negligible because both traces are similarly at the
same potential.
The LOG200EVM provides a footprint to connect a photodiode to the I1 input pin. The photosensor is kept in
close proximity to the I1 input to minimize parasitic capacitance. The evaluation board provides all the necessary
photosensor and adaptive bias circuit connections through resistor R2, R3 and optional capacitors C1, C3. For a
detailed explanation, refer to the photodiode connections section of the User Guide.
Decoupling capacitors C7, C8 and C11 are positioned on the top layer as close as possible to the power-supply
pins of the device. Similarly, reference bypass capacitor C12 and C14 are located in close proximity to the
reference pins.
The second internal layer is a dedicated to the power supplies connections and contains a common-mode
(VCM) plane. The third internal layer and bottom layers contain a ground plane and route additional auxiliary
amplifier/reference signals.
Figure 3-3. Top Overlay PCB Layout
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