Texas Instruments DS80PCI810EVM User manual

DS80PCI810EVM Evaluation Board
User's Guide
Literature Number: SNLU171
September 2014

Contents
1 Overview............................................................................................................................. 4
1.1 Features....................................................................................................................... 4
1.2 Applications................................................................................................................... 4
1.3 Ordering Information ........................................................................................................ 4
2 4-Level IO Control ................................................................................................................ 6
3 DS80PCI810EVM Configuration Overview ............................................................................... 8
3.1 Quick Start Guide............................................................................................................ 9
4 Bill of Materials .................................................................................................................. 12
5 Schematic ......................................................................................................................... 13
6 EVM Layout ....................................................................................................................... 14
2Contents SNLU171–September 2014
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List of Figures
1-1. DS80PCI810EVM Front..................................................................................................... 5
1-2. DS80PCI810EVM Back..................................................................................................... 5
2-1. Switch Orientation for User Configuration................................................................................ 6
5-1. Schematic .................................................................................................................. 13
6-1. Top Assembly Layer....................................................................................................... 14
6-2. Bottom Assembly Layer ................................................................................................... 15
List of Tables
1-1. Ordering Information ........................................................................................................ 4
2-1. Description of 4-Level Voltage Inputs..................................................................................... 6
2-2. Switch Configuration ........................................................................................................ 7
3-1. Description of Connections................................................................................................. 8
3-2. Description of Switch Configuration and Settings ....................................................................... 8
3-3. SMA Channel Connections ............................................................................................... 10
3-4. EQA and EQB Settings Available in Pin Mode......................................................................... 10
3-5. VOD Output Settings available in Pin Mode............................................................................ 11
4-1. Bill of Materials ............................................................................................................. 12
3
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Chapter 1
SNLU171–September 2014
Overview
The DS80PCI810EVM – SMA evaluation kit provides a complete high bandwidth platform to evaluate the
PCIe signal conditioning features of the Texas Instruments DS80PCI810 repeater/redriver. The
DS80PCI810EVM can be used for standard compliance testing, performance evaluation, and initial system
prototyping. The SMA edge launch connectors used for the DS80PCI810EVM will interface to multiple
system connector types via commercially available breakout cables, adaptors, and boards (not included).
This flexible connectivity enables integrated system level testing between TI repeaters and 3rd party
ASIC/FPGA host boards. For a functional description of the DS80PCI810, refer to the DS80PCI810
datasheet.
1.1 Features
• 8-Channel unidirectional repeater operating at rates up to 8 Gbps
• Linear equalization to support link training protocols
• EQ up to ~10 dB at 4 GHz
• Variable voltage range up to 1200 mVpp
• Linear output driver
• Programmable by pin selection (pin mode), EEPROM, or SMBus interface
• Single supply operation: VIN = 3.3 V ± 10% or VDD = 2.5 V ± 5%
• –40°C to +85°C operation
• 4 kV HBM ESD rating / 1 kV CDM ESD rating
• High speed signal flow–thru pin-out package: 54-pin QFN (10 mm x 5.5 mm, 0.5 mm pitch)
1.2 Applications
• FR-4 Backplane traces and high speed cable in serial Interfaces up to 8 Gbps
• PCIe Gen 1/2/3
1.3 Ordering Information
Table 1-1. Ordering Information
EVM ID DEVICE ID DEVICE PACKAGE
DS80PCI810EVM DS80PCI810NJY WQFN-54
4Overview SNLU171–September 2014
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Figure 1-1. DS80PCI810EVM Front
Figure 1-2. DS80PCI810EVM Back
5
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1 2 3 4 5 6
ON
OFF
{ {
VODA0 VODA1
Chapter 2
SNLU171–September 2014
4-Level IO Control
The channel settings and controls are configurable in pin mode for the DS80PCI810 via four logic levels
(0, R, F, 1). The four logic levels correspond to the following voltages in Table 2-1.
Table 2-1. Description of 4-Level Voltage Inputs
Internal Pin Voltage (3.3 V Internal Pin Voltage (2.5 V
Level Setting Mode) Mode)
0 Tie 1kΩto GND 0.10 V 0.08 V
R Tie 20kΩto GND 1/3 x VIN 1/3 x VDD
F Float (leave pin open) 2/3 x VIN 2/3 x VDD
1 Tie 1kΩto VIN or VDD VIN – 0.05 V VDD – 0.04 V
Typical 4-level input thresholds:
• Internal threshold between 0 and R = 0.2 * VIN or VDD
• Internal threshold between R and F = 0.5 * VIN or VDD
• Internal threshold between F and 1 = 0.8 * VIN or VDD
To set these 4-level voltage inputs, each input is controlled by a group of three switches in accordance
with Figure 2-1. These switches are located on the back of the EVM. For switch modules that come in a
set of six (such as SW3), switches 6-5-4 control one setting, and switches 3-2-1 control another.
Figure 2-1. Switch Orientation for User Configuration
NOTE: The switches on the back of the EVM physically display the switch numbers in ascending
order, as shown from the example in Figure 2-1. However, conventional notation of switch
settings are typically given in descending order. Therefore, switch configurations for the
EVM will appear in descending order for the rest of this User's Guide as a result of this
notation convention.
The following switches are used to set the input condition for 4-level inputs: SW1, SW2, SW3, SW5, SW6,
SW8, and SW9.
The switch configurations for each of the 4-level inputs are shown in Table 2-2. Note the notation in
descending order.
64-Level IO Control SNLU171–September 2014
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3 2 1
OFF-OFF-ON
ON
OFF
(6 5 4)
3 2 1
OFF-OFF-OFF
ON
OFF
(6 5 4)
3 2 1
OFF-ON-OFF
ON
OFF
(6 5 4)
3 2 1
ON-OFF-OFF
ON
OFF
(6 5 4)
3 2 1
ON-OFF-OFF
ON
OFF
(6 5 4)
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Table 2-2. Switch Configuration
4-Level Input Setting Switch Settings (3-2-1 or 6-5-4)
0 Tie 1kΩto GND
R Tie 20kΩto GND
F Float (leave pin open)
1 Tie 1kΩto VIN or VDD
NOTE: Since each 4-level input setting is controlled by a set of three adjacent switches, only one of
the three switches can be in the ON position at any time.
7
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Chapter 3
SNLU171–September 2014
DS80PCI810EVM Configuration Overview
The following tables describe the various connectors and user-controllable settings available on the
DS80PCI810EVM. Since the device can operate in one of three modes (pin mode, SMBus slave mode,
and SMBus master mode), note the switch description that matches the intended mode of operation. For
more information about specific EQ, VOD, and SD_TH values, see the DS80PCI810 datasheet.
Table 3-1. Description of Connections
Component Name Function
J1, J2 IN_B2+, IN_B2-
J3, J4 IN_B3+, IN_B3- High-speed differential input pairs
J5, J6 IN_A0+, IN_A0-
J7, J8 IN_A1+, IN_A1-
J9, J10 OUT_B2+, OUT_B2-
J11, J12 OUT_B3+, OUT_B3- High-speed differential output pairs
J13, J14 OUT_A0+, OUT_A0-
J15, J16 OUT_A1+, OUT_A1- Optional SMBus access pins. See
J17 SDA, SCL datasheet for additional information on
SMBus.
EEPROM slot for operation in master
J18 EEPROM mode (optional)
J19 PWR VIN (3.3 V) or VDD (2.5 V) for DC power
Tie VIN (3.3 V) or VDD (2.5 V) to VIH power
J20 VIH_SEL (jumper required)
Table 3-2. Description of Switch Configuration and Settings
Component Switch No. Name and Description
[Pin and SMBus modes] AD2: ADDR[2]
6-5-4 Note: In Pin mode, this must be tied to GND (6-5-4 = ON-OFF-OFF)
SW1 [Pin mode] EQB: 4-level EQ setting for B-Channels
3-2-1 [SMBus modes] AD3: ADDR[3]
ENSMB: Enable SMBus modes
3-2-1 = ON-OFF-OFF for pin mode
SW2 3-2-1 3-2-1 = OFF-OFF-ON for SMBus slave mode
3-2-1 = OFF-OFF-OFF for SMBus master mode (load configuration from
EEPROM)
[Pin mode] VODA1: VOD Control [1] for A-Channels
6-5-4 [SMBus modes] Set all switches to OFF. VOD is controlled individually via
registers.
SW3 [Pin mode] VODA0: VOD Control [0] for A-Channels
3-2-1 [SMBus modes] Set all switches to OFF. VOD is controlled individually via
registers.
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Table 3-2. Description of Switch Configuration and Settings (continued)
Component Switch No. Name and Description
SCL
2ON for SMBus modes
OFF for Pin mode
SW4 SDA
1ON for SMBus modes
OFF for Pin mode
[Pin mode] VODB1: VOD Control [1] for B-Channels
6-5-4 [SMBus modes] AD1: ADDR[1]
SW5 [Pin mode] VODB0: VOD Control [0] for B-Channels
3-2-1 [SMBus modes] AD0: ADDR[0]
[Pin and SMBus modes] LPBK-RES (RES1): Reserved
6-5-4 Note: Set all switches to OFF for normal operation.
[Pin and SMBus slave mode] SD_TH: Signal detect assert/de-assert
SW6 Threshold level for signal detect monitor
3-2-1 [SMBus master mode] READ_EN: See description of Read Enable button
on SW10.
RESET/PWDN
2ON to enable device
OFF to disable device
SW7 VDD_SEL
1ON for 3.3 V mode
OFF for 2.5 V mode
[Pin and SMBus modes] RES3: Reserved
6-5-4 Note: In Pin mode, this must be tied to GND (6-5-4 = ON-OFF-OFF)
SW8 [Pin mode] EQA: 4-level EQ settings for A-Channels
3-2-1 [SMBus modes] Set all switches to OFF. EQA is controlled individually via
registers.
[Pin and SMBus modes] RES2: Reserved
6-5-4 Note: Set all switches to OFF for normal operation.
SW9 [Pin and SMBus modes] RX_DET: Enable or disable the internal 50Ωto
3-2-1 VDD Input Termination. See datasheet for more information.
[SMBus master mode] READ_EN: Enable load from external EEPROM in
master mode
SW6: SD_TH (3-2-1) becomes the READ_EN pin.
SW10 N/A To start the loading at power up, set SW6 pin 3 to ON (pull to GND).
To control the start manually, set SW6 pin 1 to ON (pull to VDD) and push
the SW10 button for the high-to-low transition to start the loading. When
loading is complete, the LED – D1 will turn off.
3.1 Quick Start Guide
1. Connect J19: VIN = 3.3 V or VDD = 2.5 V and GND.
• For VIN = 3.3 V: Set SW7 pin1 (VDD_SEL) to the ON position (enable internal LDO regulator) and
float VDD at J19.
• For VIN = 2.5 V: Set SW7 pin1 (VDD_SEL) to the OFF positions (disable internal LDO regulator)
and float VIN at J19.
2. Set Jumper J20 for VIH connection to VIN or VDD.
• For 3.3 V mode: VIH tied to VIN (see Figure 1-1)
• For 2.5 V mode: VIH tied to VDD (see Figure 1-1)
3. Set the control switches for normal operation:
9
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• SW6 – SD_TH = F (default signal detect threshold level): Set switches (3-2-1) = (OFF-OFF-OFF).
• SW6 – LPBK-RES = F (normal operation): Set switches (6-5-4) = (OFF-OFF-OFF).
• SW7 – RESET = 0 (enables the device): Set switch pin 2 to the ON position.
• SW9 – RX_DET = F (enables RX detection): Set switches (3-2-1) = (OFF-OFF-OFF).
• SW9 – RES2 = F (normal operation): Set switches (6-5-4) = (OFF-OFF-OFF).
4. Connect 50ΩSMA cables to the board depending on the desired input and output channels:
• The input signals J1 to J8 can be connected from a pattern generator.
• The output signals J9 to J16 can be connected to a scope.
Table 3-3. SMA Channel Connections
A/B Channels Input Channel Output Channel
J1: IN_B2+, J2: IN_B2- J9: OUT_B2+, J10: OUT_B2-
B-Channels J3: IN_B3+, J4: IN_B3- J11: OUT_B3+, J12: OUT_B3-
J5: IN_A0+, J6: IN_A0- J13: OUT_A0+, J14: OUT_A0-
A-Channels J7: IN_A1+, J8: IN_A1- J15: OUT_A1+, J16: OUT_A1-
5. Pin Mode – Set the input equalization level:
• Set ENSMB = 0 (1 kΩto GND) by using SW2 (3-2-1) = (ON-OFF-OFF).
• Set SW4 switches 1 and 2 to the OFF positions so the SMBus signals are disconnected.
• Refer to Table 2-1 for information on 3-switch settings for the 4-level input.
• [Example] Set EQA to Level 3: SW8 (3-2-1) = (OFF-OFF-OFF) = EQA = F
Table 3-4. EQA and EQB Settings Available in Pin Mode
EQUALIZATION BOOST RELATIVE TO DC
SW8 (3-2-1)
EQA dB at 1.5 dB at 2.5
SW1 (3-2-1)
Level dB at 4 GHz
EQB GHz GHz
3 2 1
1 0 ON OFF OFF 2.1 2.5 2.7
2 R OFF ON OFF 4.0 5.1 6.4
3 F OFF OFF OFF 5.5 7.0 8.3
4 1 OFF OFF ON 6.8 8.3 9.5
NOTE: For normal operation in pin mode, ensure that RES3 SW8 (6-5-4) = (ON-OFF-OFF) and
AD2 SW1 (6-5-4) = (ON-OFF-OFF).
6. Pin mode: Set the output VOD level:
• Set ENSMB = 0 (1 kΩto GND) by using SW2 (3-2-1) = (ON-OFF-OFF).
• Set SW4 switches 1 and 2 to the OFF positions so the SMBus signals are disconnected.
• Refer to Table 2-1 for information on 3-switch settings for the 4-level input.
• [Example] Set VODB[1:0] to Level 4: SW5 (6-5-4), (3-2-1) = (OFF-ON-OFF), (OFF-OFF-OFF) =
VODB[1:0] = R, F
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