Texas Instruments TPS70151 Series User manual

Low Dropout, DualĆOutput
Linear Regulator EVM Using
the TPS70151
April 2000 Mixed-Signal Products
User’s Guide
SLVU025A

IMPORTANT NOTICE
TexasInstruments andits subsidiaries(TI) reservethe rightto makechanges totheir productsor todiscontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TIdeemsnecessarytosupport thiswarranty.Specifictestingofall parametersofeachdeviceis notnecessarily
performed, except those mandated by government requirements.
Customers are responsible for their applications using TI components.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TIassumes noliabilityforapplicationsassistance orcustomer productdesign. TIdoes notwarrantorrepresent
thatanylicense,eitherexpressorimplied,isgrantedunderanypatentright,copyright,maskworkright,orother
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 2000, Texas Instruments Incorporated

iii
Read This First
Preface
About This Manual
Thisuser’sguidedescribestheTPS70151EVM–152lowdropout,dual-output
evaluation module (SLVP152). The SLVP152 provides a convenient method
for evaluating the performance of a dual-output linear regulator.
How to Use This Manual
- Chapter 1 Introduction
- Chapter 2 EVM Adjustments and Test Points
- Chapter 3 Circuit Design
- Chapter 4 Test Results
Information About Cautions and Warnings
This book may contain cautions and warnings.
This is an example of a caution statement.
A caution statement describes a situation that could potentially
damage your software or equipment.
This is an example of a warning statement.
A warning statement describes a situation that could potentially
cause harm to you.
The information in a caution or a warning is provided for your protection.
Please read each caution and warning carefully.
Related Documentation From Texas Instruments
- TPS70151 data sheets (literature number SLVS222)

iv

Running Title—Attribute Reference
v
Chapter Title—Attribute Reference
Contents
1 Introduction 1–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1 Low Dropout Voltage Linear Regulator Circuit Operation 1-2. . . . . . . . . . . . . . . . . . . . . . . . .
1.2 Design Strategy 1-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3 Schematic 1-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4 Bill of Materials 1-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5 Board Layout 1-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 EVM Adjustments and Test Points 2-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1 Adjustment by Switch and Jumper 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2 Adjustment Through Component Changes 2-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3 Test Setup 2-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 Circuit Design 3-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1 Temperature Considerations 3-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2 ESR and Transient Response 3-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4 Test Results 4-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1 Test Results 4-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Running Title—Attribute Reference
vi
Figures
1–1 Typical LDO Application 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1–2 SLVP152 EVM Universal LDO Tester Schematic Diagram 1-4. . . . . . . . . . . . . . . . . . . . . . . . . .
1–3 Top Layer 1-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1–4 Bottom Layer (top view) 1-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1–5 Assembly Drawing (top assembly) 1-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–1 Test Setup 2-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–1 ESR and ESL 3-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–2 LDO Output Stage With Parasitic Resistances ESR 3-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–3 Correlation of Different ESRs and Their Influence to the Regulation of VOat a
Load Step From Low-to-High Output Current 3-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–1 No Load – Full Load (500 mA) Transition With CO= 33 µF POSCAP– LDO Settling
Time 4-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–2 No Load – Full Load (500 mA) Transition With CO= 33 µF POSCAP– LDO Response
Time 4-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–3 No Load – Full Load (500 mA) Transition With CO= 33 µF POSCAP– Maximum
Transient Droop Voltage 4-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–4 Timing When SEQUENCE = Low 4-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–5 Timing When SEQUENCE = Low, Including RESET 4-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–6 Timing When SEQUENCE = High 4-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–7 Timing When SEQUENCE = High and VOUT1 Faults Out 4-5. . . . . . . . . . . . . . . . . . . . . . . . . . .
4–8 Timing When SEQUENCE = High and VOUT2 Faults Out 4-5. . . . . . . . . . . . . . . . . . . . . . . . . . .
4–9 Timing When MR is Toggled 4-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Tables
1–1 Summary of the TPS701xx LDO Family Features 1-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1–2 SLVP152 EVM Bill of Materials 1-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–1 Jumper Functions 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–2 Commonly Changed Components 2-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–3 Timing Equations 2-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–4 Regulator Loading Options 2-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
POSCAP is a trademark of Sanyo Electric Company, LTD.

1-1
Introduction
Introduction
Thisuser’sguidedescribestheTPS70151EVM–152lowdropout,dual-output
evaluation module (SLVP152). LDOs provide ideal power supplies for rapidly
transitioning DSP loads. The TPS701xx family of devices is designed to
provide a complete power management solution for DSP, processor power,
ASIC,FPGA,anddigitalapplicationswheredualoutputvoltageregulatorsare
required. Easy programmability of the sequencing function makes this family
ideal for any DSP applications with power sequencing requirement.
Differentiated features, such as SVS supervisory circuit, manual reset inputs,
and enable function, provide a complete system solution. Moreover, with its
low quiescent current, low dropout voltage, low output noise, high PSRR, fast
transient response, and high accuracy compared to standard LDOs, the
TPS701xxprovidesan ideal solutionwhere standard linearregulators are too
inefficient or too slow and where a switch converter solution or the source
power supply is too noisy.
Topic Page
1.1 Low Dropout Voltage Linear Regulator Circuit Operation 1–2. . . . . . . . .
1.2 Design Strategy 1–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3 Schematic 1–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4 Bill of Materials 1–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5 Board Layout 1–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 1

Low Dropout Voltage Linear Regulator Circuit Operation
1-2
Introduction
1.1 Low Dropout Voltage Linear Regulator Circuit Operation
In TI’s low dropout voltage linear regulator topology, a PMOS transistor acts
as the pass element. Because the PMOS device behaves as a low-value
resistor,thedropoutvoltageisverylowandisdirectlyproportionaltotheoutput
current.Additionally,sincethePMOSpasselementisavoltage-drivendevice,
the quiescent current is very low and independent of output loading.
The basic LDO regulator circuit includes the LDO and an output capacitor for
stabilization. Figure 1–1 shows the circuit of a typical LDO application.
Figure 1–1.Typical LDO Application
_
+
Control
_
+
R1
R2
Q1
Vref
LDO
CO
VO
Load
_
+
VCC
In the LDO application shown in Figure 1–1, the LDO regulates the output
voltage VO.
If VOfalls below the regulation level, the controller increases the VSG
differential and the PMOS transistor conducts more current, resulting in an
increaseinVO.IfVOexceedstheregulationlevel,thecontrollerdecreasesthe
VSG differential and the PMOS transistor conducts less current, resulting in a
decreaseinVO.ThePMOSpasselementactslikeanadjustableresistor.The
morenegative the gatebecomes versus thesource, the lessthe source-drain
resistance becomes, resulting in higher current flow through the PMOS.

Design Strategy
1-3
Introduction
1.2 Design Strategy
The TI SLVP152 EVM provides a convenient method for evaluating the
performance of TPS701xx dual-output linear regulators. The EVM provides
proven, demonstrated reference designs and test modes to aid in evaluation.
Theboardcontainsapowersupplyalongwithanonboardtransientgenerator.
The transient slew rate can be modified by changing two resistors. Jumpers
allow settings of minimum/maximum load as well as device-enabling and
power sequencing. There is enough room on the EVM to evaluate different
typesofoutputcapacitorsincludingESRbehaviors.Manytestpointsallowthe
measuring of input, output, and dropout voltage.
The EVM contains a TPS70151. Regulator 1 provides an output voltage of
3.3 V and a maximum output current of 500 mA. Regulator 2 provides an
output voltage of 1.8 V and a maximum output current of 250 mA.
Table 1–1 summarizes the TPS701xx family’s features. See the TPS701xx
datasheet,TIliteraturenumberSLVS222
, forafurtherexplanationoffeatures.
Table 1–1.Summary of the TPS701xx LDO Family Features
DESCRIPTION TPS701xx FEATURE
Maximum input voltage [V] 6
Maximum output current [mA] 500/250
Typical quiescent current [µA] 190
Typical dropout voltage [mV] 150/200
Typical output noise [µVrms]
(30 Hz ≤f ≤50 kHz, CO= 33 µF) 65
Accuracy over line, load, and
temperature 2%
PSRR (at 1 kHz, CO= 10 µF,
TJ= 25°C) 80/60 dB
Package PWP
Minimum output capacitor > 10 µF (ceramic)
Available voltage option [V] 3.3/1.5, 3.3/1.2, 3.3/1.8, 3.3/2.5, and adj/adj
Performance advantage Dual output LDO, power-up sequencing, DSP application,
PG and RESET

Schematic
1-4
Introduction
1.3 Schematic
Figure1–2 shows the SLVP152 EVM schematic diagram.
Figure 1–2.SLVP152 EVM Universal LDO Tester Schematic Diagram
0.1
µF
VOUT2
ENABLE
7DISCH
6THRES
2TRIG
8VCC
1GND
4RESET 3
OUT
5
CTL
D1
DL4148
C1
J2
C6
+C3
C8
C9
C10
1000 pF
TP9
3VIN1
2VIN1
7SEQUENCE
8GND
9VIN2
10 VIN2
1NC
11NC
12
13
VOUT2
14
VSENSE2
16
PG_1
17
VSENSE1
18
VOUT1
19
VOUT1
20
NC
4MR2
5MR1
6 15
RESET
PwrPad
R5 10
R7 10
3GND
1VDD
21IN
42IN
8
REG
6
VCC
5
2OUT
7
1OUT Q1
Si4410
Si4410
Q2
C11
1000 pF
DL4148
D2
DL4148
D3
R6 510
R8 510
+C2
C4
J1
JP4
JP3
JP2
TP7
TP8 D4
Green
TP4
TP3
TP6
TP5
JP1
J3
TP11
TP12
TP13
R13
0
D5
RED
R11
0
TP10
+
C12 C14
TP17
R14
1.8K
TP14
TP16
JP5
JP6
+C13 C15
TP15
U3
TPS70151PWP
VO1
GND
GND
VO2
4
3
2
1
VIN1
GND
GND
VIN2
1
2
3
4
Default Jumper Settings
JP1 2–3 = PG Controls MR2
JP3 Low – Enabled
JP4 1–2 = VO1 an first
100 µF
0.1 µF
TP1
VIN1
Sense PG_1
GND
GND
VIN
TP2
VIN2
Sense
100 µF 0.1 µF
VCC
GND 1
2
U2
TPS2812
R3
5.1 kΩ
R1
4.3 kΩ
R2
10 kΩ
1 µFEnable
On
Off
S1 U1
TPS555D
C7
0.1 µF
10 µF
R9
2 kΩR10 2 kΩ
VO1
Sense
0.1 µF
33 µF
R12
3.3 kΩ
VO2
Sense
0.1 µF
33 µF
R4
10 kΩ
R24 R23 R22 R21 R20
JP16 JP15 JP14 JP13 JP12 JP11
JP10
JP9 JP8 JP7
R19 R18 R17 R16 R15
C5
0.1 µF

Bill of Materials
1-5
Introduction
1.4 Bill of Materials
Table 1–2 lists materials required for the SLVP152 EVM.
Table 1–2.SLVP152 EVM Bill of Materials
Ref Des Qty Part Number Description MFG Size
C1 1 ECJ-2VF1C105Z Capacitor, ceramic, 1.0 uF, 16 V,
80% – 20%, Y5V Panasonic 805
C4 – 7, 9,
14, 15 7 GRM39X7R104K016A Capacitor, ceramic, 0.1 uF, 16 V, 10%, X7R Murata 603
C2 – 3 2 TPSD107M010R100 Capacitor, tantalum, 100 µF, 10 V,
100-mΩ, 20% AVX D Case
C10, 11 2 GRM39X7R102K050A Capacitor, Ceramic, 1000 pF, 50 V,
10%, X7R Murata 603
C12, 13 2 10TPA33M Capacitor, POSCAP, 33 µF, 10 V, 20% Sanyo D Case
C8 1 GRM235Y5V106Z016A Capacitor, ceramic, 10 µF, 16 V,
80%–20%, Y5 V TDK 1210
D1 – 3 3 DL4148 Diode, signal, 75 V, 200 mA Diodes, Inc. DL–35
D4 1 SML-LX2832GC-TR Diode. LED, green, 2.1 V, 25 mcd, SM Lumex 1210
D5 1 SML-LX2832RC-TR Diode. LED, red, 1.7 V, 40 mcd, SM Lumex 1210
J1, 3 2 ED1516 Terminal block, 4-pin, 6-A, 3.5 mm OST 3.5 mm
J2 1 ED1514 Terminal block, 2-pin, 6A, 3.5 mm OST 3.5 mm
JP1, 4 2 PTC36SAAN Header, single-row, straight, 3-pin,
0.100” x 25 mil Sullins 0.1”
JP2, 3,
5 – 16 14 PTC36SAAN Header, single-row, straight, 2-pin, 0.100” x 25 mil Sullins 0.1”
Shunts 16 929950-00-ND Shunt, jumper, 0.1” 3M 0.1”
Q1, 2 2 Si4410DY MOSFET, N-ch, 30-V, 10-A, 13 mΩSiliconix SO–8
Q1,2 (Alt) IRF7811 MOSFET, N-ch, 30-V, 10-mΩIR SO–8
R1 1 Std Resistor, chip, 4.3 kΩ, 1/16W, 5% 603
R2 1 Std Resistor, chip, 10 kΩ, 1/16W, 5% 603
R3 1 Std Resistor, chip, 5.1 kΩ, 1/16W, 5% 603
R4 1 Std Resistor, chip, 10 kΩ, 1/16W, 5% 603
R5, 7 2 Std Resistor, chip, 10 Ω, 1/16W, 5% 603
R6, 8 2 Std Resistor, chip, 510 Ω, 1/16W, 5% 603
R9, 10 2 Std Resistor, chip, 2.0 kΩ, 1/16W, 5% 603
R11, 13 2 Std Resistor, chip, 0 Ω, 1/16W, 5% 603
R12 1 Std Resistor, chip, 3.3 kΩ, 1/16W, 5% 603
R14 1 Std Resistor, chip, 1.8 kΩ, 1/16W, 5% 603
R15 – 20 6Resistor, chip, 33.2 Ω, 1 W, 1% 2512
R21 – 24 4Resistor, chip, 51.1 Ω, 1 W, 1% 2512

Bill of Materials
1-6
Introduction
Table 1–2. SLVP152 EVM Bill of Materials (Continued)
Ref Des Qty Part Number Description MFG Size
S1 1 EG1218 Switch, 1P2T, slide, PC-mount E–Switch 0.1”
TP1, 2,
16, 17 4 131–4244–00 Adaptor, 3.5-mm probe clip (or 131–5031–00) Tektronix
TP3 – 15 13 240–345 Test point, red Farnell
U1 1 TLC555D IC, timer TI SO8
U2 1 TPS2812D IC, MOSFET driver, dual buffer TI SO8
U3 1 TPS70151PWP IC, LDO regulator, dual-output TI PWP20
–– 1SLVP152, Rev. A PCB, 2-layer, 2-oz,
3.10”(L) x 2.425”(W) x 0.062”(T)

Board Layout
1-7
Introduction
1.5 Board Layout
Figures 1–3 through 1-5 show the board layout for the SLVP125 EVM.
Figure 1–3.Top Layer
Top Layer
Figure 1–4.Bottom Layer (top view)
Bottom Layer (Top View)

Board Layout
1-8
Introduction
Figure 1–5.Assembly Drawing (top assembly)
Top Assembly
Dual – Output LDO EVM
SLVP152

2-1
EVM Adjustments and Test Points
EVM Adjustments and Test Points
This chapter explains the following EVM adjustment modes:
- Adjustment by switch and jumper
- Adjustment through changing components
Figure 2–1 shows the locations of the adjustment points on the board.
Topic Page
2.1 Adjustment by Switch and Jumpers 2–2. . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2 Adjustment Through Component Changes 2–3. . . . . . . . . . . . . . . . . . . . . .
2.3 Test Setup 2–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 2

Adjustment by Switch and Jumpers
2-2
EVM Adjustments and Test Points
2.1 Adjustment by Switch and Jumpers
S1 switches the transient generator on or off. Table 2–1 lists adjustments that
can be made by jumpers.
Table 2–1.Jumper Functions
Jumper Setting Functional Description
JP1 Short 1-2 – MR2 tied to GND RESET follows MR2
Short 2-3 – MR2 tied to PG_1 RESET will go high after a 120 ms delay when
VOUT2 reaches 95% of its regulated voltage
and when PG_1 goes high due to VOUT1
reaching 95% of its regulated voltage.
Open MR2 is disabled
JP2 Shorted – MR1 tied to GND RESET follows MR1
Open MR1 is disabled
JP3 Shorted – EN tied to GND Enable DUT
Open Disable DUT
JP4 Short 1-2 – SEQ tied to GND SEQ low – regulator 1 powers up first with regu-
lator 2 powering up when VOUT1 is 83% of max
output voltage.
Short 2-3 – SEQ tied to VIN SEQ high or left open – regulator 2 powers up
first with regulator 1 powering up when VOUT2 is
83% of max output voltage
JP5 Shorted – bypass transient generator
for regulator 1 Allows continuous load through onboard load resistors on regulator 1.
Open – engage transient generator
for regulator 1 Allows pulsed load through onboard load resis- tors on regulator 1.
JP6 Shorted – bypass transient generator
for regulator 2 Allows continuous load through onboard load resistors on regulator 2.
Open – engage transient generator
for regulator 2 Allows pulsed load through onboard load resis- tors on regulator 2.
JP7 – JP11 Shorted – include resistor in parallel
combination Increase regulator 1 load from no load to max load.
Open – remove resistor from parallel
combination Decrease regulator 1 load from max load to no load.
JP12 – JP16 Shorted – include resistor in parallel
combination Increase regulator 2 load from no load to max load.
Open – remove resistor from parallel
combination Decrease regulator 2 load from max load to no load.
TheTPS701xxdatasheet, TILiteraturenumberSLVS222,providesfurtherex-
planationofalternativeconfigurationsusingtheSVSsupervisory circuit, pow-
er good, manual reset, and enable inputs.

Adjustment Through Component Changes
2-3
EVM Adjustments and Test Points
2.2 Adjustment Through Component Changes
Through minor soldering work, the DUT can be changed to any of the fixed-
voltagemembersoftheTPS701xxLDOfamily. Inaddition,Table2–2summa-
rizes the most common components which a user might wish to replace in or-
der to more fully characterize the LDO.
Table 2–2.Commonly Changed Components
Component Regulator 1 Regulator 2 EVM Value
Input capacitor C2 C3 100 µF
Output capacitor C12 C13 33 µF
Resistors controlling transient pulse generator pulse width and
duty cycle (see Table 2-3) R1, R2 R1, R2 4.3 kΩ,
10 kΩ
Resistor controlling load transient rise time†R6 R8 510 Ω
†Larger resistance slows rise time.
Table 2–3 gives the equations for computing the resistor sizes necessary for
changing the transient pulse width and/or duty cycle.
Table 2–3.Timing Equations
Timing Equations With Diode D1 for
Low Duty Cycles Timing Equations Without Diode D1
R 1 +
t
on
0.693 CR
1 +
t
on
(2
D * 1)
0.693
D C
R 2 +
t
on
(1
* D
)
0.693
D CR
2 +
t
on
(1
* D
)
0.693
D C
Note: ton = desired load on-time [s]
D = on-time duty cycle
C = total capacitance in circuit (1 uF)
RH1, RH2 = Timer resistors value (refer to schematics) [Ω]
2.3 Test Setup Figure 2–1 shows the test setup. Follow these steps for initial power up of the
SLVP152
1) Adjust the settings of jumpers to fit test requirements (see jumper func-
tionsinTable 2-1). Verifythattheswitchcontrollingtheloadtransientgen-
eratorisoff,noexternalloadisconnectedthroughJ3andthatJP5andJP6
are open to prevent loading through the onboard resistors.
2) Connecta12-VlabpowersupplytotheVCC inputandGNDatJ2.Thepo-
larityisprintedontheboard.Acurrentlimit of100mAshouldbe adequate
for the test and measure circuit.
3) Connect a second lab power supply (at least capable of supplying 2 A) to
the J1 connector at VIN1, VIN2, GND1 and GND2. The polarity is printed
on the board. Verify that the lab power supply output voltage limit is set to
6 V and that the output is set to 0 V.
4) Turn on the 12-V lab supply. Turn on the second power supply and ramp
the input voltage up to the desired maximum but not higher than 6 V.

Test Setup
2-4
EVM Adjustments and Test Points
5) Verifythattheoutputvoltage(measuredattheVOUT1 andVOUT2pinsre-
spectively) has the desired value.
6) Table2–4showsthethreerecommendedoptionsforloadingeachregula-
tor.
Table 2–4.Regulator Loading Options
Type JP5–Regulator 1
JP6–Regulator 2 SW_1 External Load
Continuous load off-board Open Off Connected
Continuous load onboard Shorted On/off Not connected
Pulsed load onboard Open On Not connected
Jumpers JP7 – JP11 and JP12 – JP16 vary the current through the onboard
resistorsfrom0tomaxloadcurrentforregulator1andregulator2respectively.
Figure 2–1.Test Setup
+
–
Power Supply
5–V, 1–A Supply
External
Load
0–500 mA
+
–
Power Supply
12–V, 0.25–A Supply External
Load
0–250 mA
All wire pairs should be twisted.
Transient Generator Enable
Output 1 Load
Output 2 Load
+
–
+
–
Dual – Output LDO EVM
SLVP152 Rev. C
The PG_1 LED indicator (D4) has Von = 2.1 V; therefore, for this test board,
the maximum PG_1 output voltage (TP11) is 2.1 V. Since the PG_1 pin is an
opendrain,activehighoutputterminalinatypicalapplication,thePG_1output
could have a typical TTL range.

3-1
Circuit Design
Circuit Design
This chapter describes the LDO circuit design procedure.
Topic Page
3.1 Temperature Considerations 3–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2 ESR and Transient Response 3–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 3

Temperature Considerations
3-2
Circuit Design
3.1 Temperature Considerations
To protect the device and assure the specifications, the maximum junction
temperature should not exceed 125°C. If the temperature exceeds 150°C,
thermal shutdown will turn off the device. This restriction limits the power
dissipation the regulator can handle in any given application. To ensure the
junction temperature is within acceptable limits, calculate the maximum
allowable dissipation, PD(max), and the actual dissipation, PD, which must be
less than or equal to PD(max). The maximum power dissipation limit is
determined using the following equation:
P
D ( max )
+
T
J , max
* T
A
R
q JA
Where:
- TJ,max is the maximum allowed junction temperature [°C], i.e., 125°C for
the TPS701xx families
- RθJA is the thermal resistance junction-to-ambient for the package, i.e.,
32.6°C/W for the 20-terminal TSSOP package
- TAis the ambient temperature
The regulator dissipation is calculated using:
P
D
+ǒ V
IN
* V
OUT
Ǔ
I
OUT
3.2 ESR and Transient Response
LDOstypicallyrequireanexternaloutputcapacitorforstability.Infasttransient
response applications, capacitors are used to support the load current while
the LDO amplifier is responding. In most applications, one capacitor is used
to support both functions.
Besides its capacitance, every capacitor also contains parasitic impedances.
Theseimpedancesareresistiveaswellasinductive.Theresistiveimpedance
is called equivalent series resistance (ESR), and the inductive impedance is
calledequivalentseriesinductance(ESL).Theequivalentschematicdiagram
of any capacitor can therefore be drawn as shown in Figure 3–1.
Figure 3–1.ESR and ESL
RESR LESL C
In most cases one can neglect the effect of inductive impedance ESL. There-
fore,thefollowingapplicationfocusesmainlyontheparasiticresistance ESR.