Texas Instruments DUAL-DIYAMP-EVM User manual

1
SBOU193–July 2017
Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated
DUAL-DIYAMP-EVM
User's Guide
SBOU193–July 2017
DUAL-DIYAMP-EVM
This user's guide contains support documentation for the DUAL-DIYAMP Evaluation Module (EVM).
Included is a description of how to set up and configure the EVM, printed circuit board (PCB) layout,
schematic, and bill of materials (BOM) of the DUAL-DIYAMP-EVM.
Contents
1 Introduction ................................................................................................................... 3
1.1 DUAL-DIYAMP-EVM Kit Contents................................................................................ 3
1.2 Features.............................................................................................................. 3
1.3 List of Circuits on EVM............................................................................................. 3
2 Hardware Setup.............................................................................................................. 3
2.1 EVM Circuit Locations.............................................................................................. 4
2.2 EVM Assembly Instructions ....................................................................................... 5
3 Schematic and PCB Layout ................................................................................................ 6
3.1 Schematic PCB Drawing........................................................................................... 6
3.2 Non-Inverting Amplifier............................................................................................. 7
3.3 Inverting Amplifier................................................................................................... 8
3.4 Difference Amplifier With Reference Buffer ................................................................... 10
3.5 Multiple Feedback Active Filter.................................................................................. 11
3.6 Sallen-Key Filter................................................................................................... 12
3.7 Riso With Dual-Feedback........................................................................................ 13
3.8 Two Op-Amp Instrumentation Amplifier ........................................................................ 14
3.9 Single-Ended Input to Differential Output ...................................................................... 16
3.10 Parallel Op Amps.................................................................................................. 17
3.11 Differential Input to Differential Output ......................................................................... 18
4 Connections................................................................................................................. 19

www.ti.com
2SBOU193–July 2017
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
DUAL-DIYAMP-EVM
4.1 Inputs and Outputs................................................................................................ 19
4.2 Power ............................................................................................................... 22
5 Bill of Materials and References ......................................................................................... 22
5.1 Bill of Materials .................................................................................................... 22
5.2 References......................................................................................................... 22
List of Figures
1 Circuit Configuration Location.............................................................................................. 4
2 Detach Desired Circuit Configuration ..................................................................................... 5
3 Detach Configuration With Attached IC and Passive Components................................................... 5
4 Terminal Strip (TS-132-G-AA) Broken Into 4-Pin Lengths ............................................................. 5
5 4-Pin Length Terminal Strips Inserted in DIP Socket................................................................... 5
6 Detached Board Configuration Position Over Terminal Pins .......................................................... 6
7 Fully-Assembled Circuit Configuration From DIYAMP-SOIC-EVM.................................................... 6
8 Silk Screen Schematic...................................................................................................... 6
9 Non-Inverting Amplifier Schematic ........................................................................................ 7
10 Non-Inverting Amplifier Top Layer PCB Layout ......................................................................... 8
11 Inverting Amplifier Schematic .............................................................................................. 8
12 Inverting Amplifier Top Layer PCB Layout ............................................................................... 9
13 Difference Amplifier with Reference Buffer Schematic................................................................ 10
14 Difference Amplifier with Reference Buffer Top Layer PCB Layout................................................. 11
15 Multiple Feedback Active Filter Schematic ............................................................................. 11
16 Multiple Feedback Active Filter Top Layer PCB Layout .............................................................. 12
17 Sallen-Key Active Filter Schematic ...................................................................................... 12
18 Sallen-Key Active Filter PCB Layout .................................................................................... 13
19 Riso With Dual-Feedback Schematic.................................................................................... 13
20 Riso With Dual-Feedback PCB Layout.................................................................................. 14
21 Two Op-Amp Instrumentation Amplifier Schematic.................................................................... 14
22 Two Op-Amp Instrumentation Amplifier Top Layer PCB Layout..................................................... 15
23 Single-Ended Input to Differential Output Schematic.................................................................. 16
24 Single-Ended Input to Differential Output Top Layer PCB Layout................................................... 16
25 Parallel Op Amp Schematic............................................................................................... 17
26 Parallel Op-Amp Top Layer PCB Layout................................................................................ 18
27 Differential Input to Differential Output Schematic..................................................................... 18
28 Differential Input to Differential Output Top Layer PCB Layout...................................................... 19
29 SMA Vertical Connectors ................................................................................................. 19
30 SMA Horizontal Connectors .............................................................................................. 20
31 Wire Connections .......................................................................................................... 20
32 Through-Hole Test Points................................................................................................. 20
33 Input and Output Labeled as INA, INB and OUTA and OUTB....................................................... 21
34 Input and Output Labeled as Vin and Vout............................................................................. 21
35 Wire Alternative for Terminal Area....................................................................................... 22
List of Tables
1 DUAL-DIYAMP-EVM Kit Contents ........................................................................................ 3
2 Circuit Configuration Location Legend.................................................................................... 4
3 MFB Filter Type Component Selection.................................................................................. 11
4 Sallen-Key Filter Component Type Selection .......................................................................... 12
5 DUAL-DIYAMP-EVM Bill of Materials ................................................................................... 22

www.ti.com Introduction
3
SBOU193–July 2017
Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated
DUAL-DIYAMP-EVM
Trademarks
FilterPro is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
1 Introduction
The DUAL-DIYAMP-EVM is an EVM developed for dual package op amps to give users the ability to
easily evaluate amplifier circuits. This “break apart” EVM has several popular op-amp configurations
including amplifiers, filters, stability compensation, and other signal conditioning circuits that require two
amplifiers. The EVM is designed for 0805 and 0603 package size surface mount components enabling
easy prototyping. This board gives the user the ability to build anything from a simple amplifier to complex
signal chains by combining different configurations.
1.1 DUAL-DIYAMP-EVM Kit Contents
Table 1 details the contents included in the DUAL-DIYAMP-EVM kit.
Table 1. DUAL-DIYAMP-EVM Kit Contents
Item Description Quantity
DUAL-DIYAMP-EVM PCB 1
Header Strip 100-mil (2.54 mm) spacing, 32 position, through hole 2
1.2 Features
The EVM has the following features:
• Multiple circuit configurations
• Breadboard compatible
• Schematic provided in silk screen on the PCB
• Multiple connector options for the input and output connections: SMA, test point, and wires.
1.3 List of Circuits on EVM
The EVM has the following circuits:
• Non-inverting amplifier
• Inverting amplifier
• Difference amplifier with reference buffer
• Multiple feedback active filter
• Sallen-Key filter
• Riso with dual feedback
• Two op amp instrumentation amplifier
• Single-ended input to differential output
• Parallel op amps
• Differential input to differential output
2 Hardware Setup
Assembly of the DUAL-DIYAMP-EVM involves identifying and breaking out the desired circuit
configuration from the EVM, soldering the components, header strip, and input and output connections.
This section presents the details of these procedures.

A A B B
C C D D
E E F F
G H IJ
Hardware Setup www.ti.com
4SBOU193–July 2017
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
DUAL-DIYAMP-EVM
2.1 EVM Circuit Locations
Figure 1 and Table 2 map the location of each circuit configuration on the EVM. Figure 1 labels each
circuit configuration with a letter ranging from A to J. Table 2 matches the circuit configuration to a letter in
Figure 1 and also provides the name of each individual circuit written in silk screen on the EVM.
Figure 1. Circuit Configuration Location
Table 2. Circuit Configuration Location Legend
Circuit Name Silk Screen Label Letter in Figure 1
Non-inverting amplifier Non-inverting Amplifier A
Inverting amplifier Inverting Amplifier B
Difference amplifier with reference buffer Difference Amp C
Multiple feedback filter MFB - Filter D
Sallen-Key filter SK Filter E
Riso with dual feedback Riso Dual Feedback F
Two op amp instrumentation amplifier 2 Op Amp INA G
Single-ended input to differential output SE to Diff H
Parallel op amps Parallel Op Amps I
Differential input to differential output Diff In Diff Out J

www.ti.com Hardware Setup
5
SBOU193–July 2017
Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated
DUAL-DIYAMP-EVM
2.2 EVM Assembly Instructions
This section has step-by-step instructions on how to assemble a circuit configuration from the EVM.
1. Choose the desired circuit configuration. See Section 2.1 for the location of each circuit configuration.
2. Gently flex the PCB panel at the score lines to separate the desired circuit configuration from the EVM.
Figure 2. Detach Desired Circuit Configuration
3. Solder device and surface mount passive components to the separated PCB.
Figure 3. Detach Configuration With Attached IC and Passive Components
4. Use long-nose pliers to break header strips, provided in the EVM kit, into 8-position lengths.
Figure 4. Terminal Strip (TS-132-G-AA) Broken Into 4-Pin Lengths
5. Insert header strips into a spare DIP socket as shown in Figure 5.
Figure 5. 4-Pin Length Terminal Strips Inserted in DIP Socket

Schematic and PCB Layout www.ti.com
6SBOU193–July 2017
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
DUAL-DIYAMP-EVM
6. Position separated PCB over pins and solder the connections. Carefully remove from the DIP socket.
Figure 6. Detached Board Configuration Position Over Terminal Pins
7. Attach SMA connectors, test points, or wires to the inputs and outputs of the separated PCB.
Figure 7. Fully-Assembled Circuit Configuration From DIYAMP-SOIC-EVM
3 Schematic and PCB Layout
This section provides the schematic and PCB layout of each circuit configuration provided on the EVM.
3.1 Schematic PCB Drawing
Each circuit board has the schematic of the circuit in silk screen located on the back of the PCB for easy
reference. Figure 8 displays an example of a schematic on the back of the PCB.
Figure 8. Silk Screen Schematic

c
1/4 2/6
1
2 R C
=
´ p ´ ´
f
1/4
2/5
R
OUTA / B 1 INA / B
R
æ ö
= +
ç ÷
è ø
+
±
C3/7 R2/5 R1/4
R3/6
C4/8
OUTA/B
INA/B
V+ C1
REFA/B
C2/6
C5
V-
www.ti.com Schematic and PCB Layout
7
SBOU193–July 2017
Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated
DUAL-DIYAMP-EVM
3.2 Non-Inverting Amplifier
Figure 9 displays the schematic for the non-inverting amplifier circuit configuration.
Figure 9. Non-Inverting Amplifier Schematic
The non-inverting amplifier circuit configuration takes an input signal that is applied directly to the high
impedance non-inverting input and outputs a signal that is the same polarity as the input signal. The
feedback network for this topology is R1, R2, C2, and C3 for channel A and R4, R5, C6, and C7 for
channel B.
There are multiple ways to configure the non-inverting amplifier circuit configuration. The following cases
show the two primary use-case configurations for this circuit.
Case 1: Standard non-inverting circuit
This circuit can be configured into a standard non-inverting circuit by shorting C4/8 and C3/7 with a 0-Ω
resistor and leaving R3/6 unpopulated.
Equation 1 displays the transfer function of the non-inverting amplifier circuit configuration shown in
Figure 9.
where
• C4/8 is shorted with a 0-Ωresistor
• C3/7 is shorted with a 0-Ωresistor
• R3/6 is unpopulated (1)
Capacitor C2 for channel A and C6 for channel B provide the option to filter the output. The cutoff
frequency of the filter can be calculated using Equation 2.
(2)
Case 2: AC-coupled, non-inverting amplifier configuration
This circuit board can be configured as an ac-coupled, non-inverting circuit by populating C4/8 and C3/7
with capacitors and populating R3/6 with resistors. Test points REFA for channel A and REFB for channel
B are used to set the dc biasing of the circuit. The dc bias voltage is typically set to one half of the supply
voltage of the amplifier.

+
±
C4/7 R3/8 R2/7
R4/9
R5/10 C5/8
OUTA/B
INA/B V+ C1
REFA/B
C3/6
R1/6
V-
C2
c
3/7 2/5
1
2 C R
=
´ p ´ ´
f
c
4/8 3/6
1
2 C R
=
´ p ´ ´
f
Schematic and PCB Layout www.ti.com
8SBOU193–July 2017
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
DUAL-DIYAMP-EVM
Populating C4/8 with capacitors ac couples the input of the circuit. The corner frequency of the high-pass
filter created by C4/8 and R3/6 is calculated in Equation 3:
(3)
Similarly, capacitor C3/7 creates a high-pass filter with R2/5. The corner frequency of the high-pass filter
created by C3/7 and R2/5 is calculated in Equation 4.
(4)
Figure 10 displays the PCB layout of the top layer of the non-inverting amplifier circuit configuration.
Figure 10. Non-Inverting Amplifier Top Layer PCB Layout
3.3 Inverting Amplifier
Figure 11 shows the schematic for the inverting amplifier circuit configuration.
Figure 11. Inverting Amplifier Schematic
The inverting amplifier configuration takes an input signal and outputs a signal that is the opposite polarity
as the input signal. The benefit of this topology is that it avoids common mode limitations. The ratio of the
resistors in the feedback network will determine the amount of gain the input signal will be amplified by.
The inverting amplifier circuit configuration provides the option to ac couple the input, filter the output, and
bias the output of the amplifier to a desired value.

c _ REF
5/8 4/9 5/10
1
2 C R / /R
=
´ p ´ ´
f
c _ OUT
3/6 2/7
1
2 C R
=
´ p ´ ´
f
c _highpass
4/7 3/8
1
2 C R
=
´ p ´ ´
f
5/10
4/9 5/10
R
OUTA / B REFA / B
R R
æ ö
=ç ÷
+
è ø
5/10
2/7 2/7
3/8 4/9 5/10 3/8
R
R R
OUTA / B INA / B 1 REFA / B
R R R R
æ ö æ öæ ö
= - + +
ç ÷ ç ÷ç ÷
+
è ø è øè ø
www.ti.com Schematic and PCB Layout
9
SBOU193–July 2017
Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated
DUAL-DIYAMP-EVM
Equation 5 displays the dc transfer function of the inverting amplifier circuit configuration.
where
• C4/7 is shorted with a 0-Ωresistor (5)
Capacitor C4 for channel A and C7 for channel B provide the option to ac couple the input of the circuit.
Equation 6 displays the dc transfer function of the ac-coupled inverting amplifier circuit configuration.
where
• The input is ac coupled with C4/7 (6)
Equation 7 calculates the cut-off frequency of the high-pass filter.
(7)
Capacitors C3 and C6 provide the option to filter the output. Equation 8 calculates the cut-off frequency of
the filter.
(8)
Capacitor C5 for channel A and C8 for channel B provide the option to filter noise introduced from the
reference voltage, REFA/B. Equation 9 calculates the cutoff frequency of the filter.
(9)
Figure 12 displays the PCB layout of the top layer of the inverting amplifier circuit configuration.
Figure 12. Inverting Amplifier Top Layer PCB Layout

c
2 1
1
2 R C
=
´ p ´ ´
f
( ) 6
2
out IN IN ref
1 5 6
R
R
V V V V
R R R
+ -
æ ö
= - + ç ÷
+
è ø
3 6
4 2 1 2
out
3 4 1 3 4 5 6 2 1
R R
R R R R
V 1 (IN ) 1 Vref (IN )
R R R R R R R R R
æ ö æ öæ ö
æ ö æ ö
= + + + + - -
ç ÷ ç ÷ç ÷
ç ÷ ç ÷
+ + +
è ø è ø
è ø è øè ø
+
±OUT
V+ C2
C3
V-
R3
R1
C1
+
±
V-
V+
IN-
IN+
VREF
C4 R4
C6C7
R7
R2
R5
C5R6
Schematic and PCB Layout www.ti.com
10 SBOU193–July 2017
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
DUAL-DIYAMP-EVM
3.4 Difference Amplifier With Reference Buffer
Figure 13 shows the schematic for the difference amplifier with reference buffer circuit configuration.
Figure 13. Difference Amplifier with Reference Buffer Schematic
The difference amplifier utilizes both inverting and non-inverting inputs and produces an output that is
dependent on the difference between the inputs. The gain of the difference amplifier is dependent on the
ratio of R2 to R1 (and subsequently R4 to R3). The reference buffer in the circuit buffers the reference
voltage to maintain the common mode rejection of the difference amplifier.
Equation 10 displays the transfer function of the difference amplifier with reference buffer circuit
configuration.
(10)
If R1= R3and R2= R4,Equation 10 simplifies to Equation 11:
(11)
Capacitors C1 and C4 provide the option to filter the output of the amplifier. Equation 12 calculates the
cut-off frequency of the filter.
where
• R1= R3
• R2= R4
• C1= C4(12)

+
±
C1
Z1/6
Z4/9
Z5/10
Z3/8
Z2/7
VOUT
V+
INA/B C3
V-
R1/3
R2/4 C2/4
REFA/B
www.ti.com Schematic and PCB Layout
11
SBOU193–July 2017
Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated
DUAL-DIYAMP-EVM
Figure 14 displays the PCB layout of the top layer of the difference amplifier with reference buffer circuit
configuration.
Figure 14. Difference Amplifier with Reference Buffer Top Layer PCB Layout
3.5 Multiple Feedback Active Filter
Figure 15 shows the schematic for the multiple feedback (MFB) active filter circuit configuration.
Figure 15. Multiple Feedback Active Filter Schematic
The MFB topology (sometimes called infinite gain or Rauch) is often preferred due to low sensitivity to
component variation. The MFB topology creates an inverting second-order stage.
The MFB filter circuit can be configured as a low-pass filter, high-pass filter, or band-pass filter based on
the component selection of Z1/6 through Z5/10. Table 3 displays the type of passive component that
should be chosen for Z1/6 through Z5/10 for each filter configuration.
Table 3. MFB Filter Type Component Selection
Pass-Band Filter
Type Type of Component (Z1/6) Type of Component (Z2/7) Type of Component (Z3/8) Type of Component (Z4/9) Type of Component (Z5/10)
Low Pass R1/6 C2/7 R3/8 R4/9 C5/10
High Pass C1/6 R2/7 C3/8 C4/9 R5/10
Band Pass R1/6 R2/7 C3/8 C4/9 R5/10

+
±
+
±
C1
Z1/8
Z3/10
Z5/12
Z2/9
Z4/11
OUTA/B
V+
INA/B
REFA/B
R2/4
R1/3
VBA/B
V- C2
c _ REF
2/4 1/3 2/4
1
2 C R / /R
=
´ p ´ ´
f
Schematic and PCB Layout www.ti.com
12 SBOU193–July 2017
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
DUAL-DIYAMP-EVM
For additional guidance in designing a filter, download FilterPro™ active filter design software.
Capacitor C2 for channel A and C4 for channel B provide the option to filter noise that may be introduced
from the REFA/B. Equation 13 calculates the cut-off frequency due to C2/4.
(13)
Figure 16 displays the PCB layout of the top layer of the multiple feedback active filter circuit configuration.
Figure 16. Multiple Feedback Active Filter Top Layer PCB Layout
3.6 Sallen-Key Filter
Figure 17 displays the schematic for the Sallen-Key active filter circuit configuration.
Figure 17. Sallen-Key Active Filter Schematic
The Sallen-Key filter is one of the most commonly applied active filter topologies. The Sallen-Key filter can
be configured as a low-pass filter, high-pass filter, or band-pass filter based on the component selection of
Z1/8 through Z5/12. Table 4 displays the type of passive components that should be chosen for Z1/8
through Z5/12 for each filter configuration.
Table 4. Sallen-Key Filter Component Type Selection
Pass-Band Filter
Type Type of Component (Z1/8) Type of Component (Z2/9) Type of Component (Z3/10) Type of Component (Z4/11) Type of Component (Z5/12)
Low Pass R1/8 R2/9 C3/10 Not Populated C5/12
High Pass C1/8 C2/9 R3/10 Not Populated R5/12
Band Pass R1/8 C2/9 R3/10 C4/11 R5/12

4/9 1/6
5/10 4/9 2/7
R R
OUTA / B 1 INA / B
R R R
æ öæ ö
= +
ç ÷ç ÷
+è ø
è ø
+
±
R4/9
OUTA/B
INA/B
V+ C2
C3
V-
R5/10 C4/8
R2/7
R1/6
C1/5
R3/8
www.ti.com Schematic and PCB Layout
13
SBOU193–July 2017
Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated
DUAL-DIYAMP-EVM
For guidance in designing a filter, download the FilterPro™ active filter design software.
Figure 18 displays the PCB layout of the top layer of the multiple feedback active filter circuit configuration.
Figure 18. Sallen-Key Active Filter PCB Layout
3.7 Riso With Dual-Feedback
Figure 19 displays the schematic for the Riso with dual-feedback circuit configuration.
Figure 19. Riso With Dual-Feedback Schematic
Equation 14 calculates the dc gain of the Riso with dual-feedback circuit configuration.
(14)
This capacitive load (C4/8) compensation technique uses an isolation resistor (R3/8) to compensate the
circuit by adding a zero to cancel the pole from the output impedance and capacitive load. Refer to the TI
Precision Labs - Op Amps: Stability 5 video for detailed information on this technique.

+
±
V+ C2
V-
C1
R5
C4
VREF
VIN-
R3
R4
VREF
RG R2
+
±
V+
V-
R1
VOUT
R6
C3
VREF
VIN+
Schematic and PCB Layout www.ti.com
14 SBOU193–July 2017
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
DUAL-DIYAMP-EVM
Figure 20 displays the PCB layout of the top layer of the Riso with dual-feedback circuit configuration.
Figure 20. Riso With Dual-Feedback PCB Layout
3.8 Two Op-Amp Instrumentation Amplifier
Figure 21 displays the schematic for the two op-amp instrumentation amplifier circuit configuration.
Figure 21. Two Op-Amp Instrumentation Amplifier Schematic
The two op-amp instrumentation amplifier takes a differential input and outputs a single-ended signal. This
circuit configuration provides a high-impedance input to sources interfacing with this circuit. While the two
op-amp instrumentation amplifier does not provide as high of common mode rejection ration (CMRR) as
the three op-amp instrumentation amplifier topology, the two op-amp instrumentation requires only two op
amps, thereby reducing cost.

c
3 6
1
2 C R
=
´ p ´ ´
f
( ) 1 1
2 G
R 2R
VOUT (VIN ) (VIN ) 1 VREF
R R
æ ö
= + - - + + +
ç ÷
è ø
www.ti.com Schematic and PCB Layout
15
SBOU193–July 2017
Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated
DUAL-DIYAMP-EVM
Equation 15 calculates the transfer function of the two op-amp instrumentation amplifier shown in
Figure 21.
where
• R1= R4
• R2= R3(15)
Capacitors C3 and C4 provide the option to ac couple the input. Equation 16 calculates the cut-off
frequency of the high-pass filter.
where
• C3= C4
• R6= R5(16)
Figure 22 displays the PCB layout of the top layer of the two op-amp instrumentation amplifier circuit
configuration.
Figure 22. Two Op-Amp Instrumentation Amplifier Top Layer PCB Layout

c
3 3 4
1
2 C R / /R
=
´ p ´ ´
f
( ) ( ) ( )
2 4 2
OUT o o
1 3 4 1
R R R
V V V 1 INA 1 VREF
R R R R
æ ö
æ ö æ ö
= + - - = + + + +
ç ÷
ç ÷ ç ÷
+
è ø è ø
è ø
+
±
V+ C1
V-
C2
R6
INA+
R5 Vo+
+
±
VREF
V-
V+
Vo-
R3
R4 C3
R1
R2
Schematic and PCB Layout www.ti.com
16 SBOU193–July 2017
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
DUAL-DIYAMP-EVM
3.9 Single-Ended Input to Differential Output
Figure 23 displays the schematic for the single-ended input to differential output circuit configuration.
Figure 23. Single-Ended Input to Differential Output Schematic
The single-ended input to differential output circuit is used to convert a single-ended input to a differential
output.
Equation 17 displays the transfer function of the single-ended input to differential output circuit
configuration.
(17)
Capacitor C3 provides the option to filter noise introduced from the reference voltage (VREF). Equation 18
calculates the cut-off frequency of the filter.
(18)
Figure 24 displays the PCB layout of the top layer of the single-ended input to differential output circuit
configuration.
Figure 24. Single-Ended Input to Differential Output Top Layer PCB Layout

c
6 5
1
2 R C
=
´ p ´ ´
f
c
2 2
1
2 R C
=
´ p ´ ´
f
2
1
R
VOUT 1 VIN
R
æ ö
= +
ç ÷
è ø
+
±
V-
V+
C3
+
±
VIN VOUT
C5
R6
R1 R2
VREF
C1
C2
R3
C4
R5 R4
www.ti.com Schematic and PCB Layout
17
SBOU193–July 2017
Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated
DUAL-DIYAMP-EVM
3.10 Parallel Op Amps
Figure 25 displays the schematic of the parallel op-amp circuit configuration.
Figure 25. Parallel Op Amp Schematic
Parallel op amps are used to increase the maximum current supplied to a load. Placing two op amps in
parallel doubles the maximum current into the load compared to using a single amplifier. This circuit is
useful for applications that require driving low impedance loads or applications that require more current
supplied into a load than a single op amp can typically supply.
There are multiple ways to configure the non-inverting amplifier circuit configuration. The following cases
show the two primary use-case configurations for this circuit.
Case 1: Standard non-inverting configuration
This circuit can be configured into a standard non-inverting circuit by shorting C1 and C5 with a 0-Ω
resistor and leaving R6 unpopulated.
Equation 19 displays the transfer function of the non-inverting amplifier circuit configuration shown in
Figure 25.
where
• C1is shorted with a 0-Ωresistor
• C5is shorted with a 0-Ωresistor
• R6is unpopulated (19)
Capacitor C2 provides the option to filter the output. Equation 20 calculates the cut-off frequency of the
filter.
(20)
Case 2: AC-coupled non-inverting amplifier configuration
This circuit can be configured into an ac-coupled, non-inverting circuit by populating C1 and C5 with
capacitors and R6 with a resistor. Test point VREF is used to set the dc biasing of the circuit. The dc
biasing is typically set to one half of the supply voltage of the amplifier.
Populating C5 ac couples the input of the circuit. Equation 21 calculates the corner frequency of the high-
pass filter created by C5 and R6.
(21)

( ) ( )
( ) ( ) ( ) ( ) 1 2
3
R R
VOUT VOUT VOUT VIN VIN 1
R
æ ö
+
= + - - = + - - +
ç ÷
è ø
+
±
V+ C2
V-
C1
R5
C4
VREF
VIN+
R2
R3
+
±
V+
V-
R1
VOUT+
R4
C3
VREF
VIN-
VOUT-
c
1 1
1
2 R C
=
´ p ´ ´
f
Schematic and PCB Layout www.ti.com
18 SBOU193–July 2017
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
DUAL-DIYAMP-EVM
Similarly, capacitor C1 creates a high-pass filter with R1. Equation 22 calculates the corner frequency of
the high-pass filter created by C1 and R1.
(22)
Figure 26 displays the PCB layout of the top layer of the parallel op amp circuit configuration.
Figure 26. Parallel Op-Amp Top Layer PCB Layout
3.11 Differential Input to Differential Output
Figure 27 displays the schematic for the differential input to differential output circuit configuration.
Figure 27. Differential Input to Differential Output Schematic
The differential input to differential output circuit configuration is used to condition a differential signal,
such as gain or attenuation, and still maintain the signal as differential.
Equation 23 calculates the transfer function of the differential input to differential output circuit
configuration shown in Figure 27.
(23)

c
4 3
1
2 R C
=
´ p ´ ´
f
www.ti.com Connections
19
SBOU193–July 2017
Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated
DUAL-DIYAMP-EVM
Capacitors C3 and C4 provide the option to ac couple the input to the circuit. Equation 24 calculates the
corner frequency of the high-pass filter created by C3 and R4 and C4 and R5.
where
• C3= C4
• R4= R5(24)
Test point VREF is used to set the dc biasing of the circuit which is typically set to one half of the supply
voltage.
Figure 28 displays the PCB layout of the top layer of the differential input to differential output circuit
configuration.
Figure 28. Differential Input to Differential Output Top Layer PCB Layout
4 Connections
This section provides a description for each connection available on the EVM.
4.1 Inputs and Outputs
The input and output connection slots were designed to fit the following connections: vertical SMA,
horizontal SMA, wires, or through-hole test points. Examples of these four connectors are shown in this
section.
The SMA recommended for this board is TE Connectivity part number 5-1814400-1. Figure 29 shows
SMA vertical connectors attached to both the input and output terminal.
Figure 29. SMA Vertical Connectors

Connections www.ti.com
20 SBOU193–July 2017
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
DUAL-DIYAMP-EVM
Figure 30 shows SMA horizontal connectors attached to the input signal terminal.
Figure 30. SMA Horizontal Connectors
Figure 31 shows a wire attached to the input and output terminal.
Figure 31. Wire Connections
Figure 32 shows a through-hole test point connector attached to the output and Vref terminal.
Figure 32. Through-Hole Test Points