Texas Instruments DLP LightCrafter DLPC910 User manual

User's Guide
DLP® LightCrafter™ DLPC910 Evaluation Module (EVM)
ABSTRACT
The DLP® LightCrafter™ DLPC910 evaluation module (EVM) offers a reference design to enable faster
development cycles for users of the DLPC910 Controller architecture in support of DMDs that use the DLPC910
controller. This platform targets applications needing high speed pattern management along with high resolution
patterns.
Table of Contents
1 Overview..................................................................................................................................................................................4
2 If You Need Assistance.......................................................................................................................................................... 4
3 DLP LightCrafter DLPC910 EVM (DLPLCRC910EVM) Overview........................................................................................ 5
3.1 Welcome............................................................................................................................................................................ 5
3.2 DLP LightCrafter DLPC910 Evaluation Module (DLPLCRC910EVM) Hardware ..............................................................6
3.3 DLPLCRC910EVM Board.................................................................................................................................................. 7
3.4 Other Items Needed for Operation.....................................................................................................................................8
3.5 DLPLCRC910EVM Connections........................................................................................................................................8
3.6 DLP LightCrafter DLPC910 LEDs.................................................................................................................................... 12
3.7 Apps FPGA Trigger Input................................................................................................................................................. 13
3.8 DLPLCRC910EVM HPC FMC Cables............................................................................................................................. 14
3.9 DLPLCRC910EVM and DMD EVM Assembly................................................................................................................. 14
3.10 Connecting an Apps FPGA Board to the DLPLCRC910EVM........................................................................................17
4 Quick Start.............................................................................................................................................................................21
4.1 Power-up the DLPLCRC910EVM.................................................................................................................................... 21
4.2 Power-down the DLPLCRC910EVM................................................................................................................................21
5 Operating the DLPLCRC910EVM.........................................................................................................................................22
5.1 DLPLCRC910EVM GUI and Apps FPGA Software......................................................................................................... 22
5.2 PC Software..................................................................................................................................................................... 22
5.2.1 Menu Bar................................................................................................................................................................... 24
5.2.2 Icon Bar..................................................................................................................................................................... 25
5.2.3 Main Window............................................................................................................................................................. 26
5.2.4 DLPC910 Registers...................................................................................................................................................34
5.2.5 Apps FPGA Registers............................................................................................................................................... 45
5.3 JTAG Flash Programming................................................................................................................................................ 62
5.4 SPI Flash Programming................................................................................................................................................... 63
5.5 AMD Xilinx VC-707 Configuration PROM Programming..................................................................................................63
5.6 USB Firmware Programming........................................................................................................................................... 64
6 Connectors............................................................................................................................................................................66
6.1 J1 - USB - Micro B USB 2.0 Connector........................................................................................................................... 66
6.2 J2 - DLPC910 I2C Connector...........................................................................................................................................66
6.3 J4 - PMBUS (I2C) Connector........................................................................................................................................... 66
6.4 J6 - USB GPIO Connector............................................................................................................................................... 67
6.5 J8 - 400 Position FMC Connector (Female).....................................................................................................................67
6.6 J14 - Power (Alternate).................................................................................................................................................... 67
6.7 J15 - Power...................................................................................................................................................................... 68
6.8 J17 - JTAG Boundary Scan Connector............................................................................................................................ 68
6.9 J18 - SPI Programming Connector.................................................................................................................................. 69
6.10 J19, J20, and J21 - Fan Connectors.............................................................................................................................. 69
6.11 J500, J501 - FMC Connector (Male).............................................................................................................................. 69
7 DLPLCRC910EVM Power Supply Requirements............................................................................................................... 70
7.1 External Power Supply Requirements............................................................................................................................. 70
8 Related Documentation from Texas Instruments.............................................................................................................. 71
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9 Abbreviations and Acronyms..............................................................................................................................................71
10 Safety................................................................................................................................................................................... 73
10.1 Caution Labels............................................................................................................................................................... 73
List of Figures
Figure 1-1. DLP LightCrafter DLPC910 Evaluation Module........................................................................................................ 4
Figure 3-1. DLPLCRC910EVM Hardware Components..............................................................................................................6
Figure 3-2. DLP LightCrafter DLPC910 EVM Block Diagram......................................................................................................7
Figure 3-3. DLPLCRC910EVM Connectors (Top View)...............................................................................................................8
Figure 3-4. DLP LightCrafter DLPC910 EVM LEDs (Top View - Upper Left).............................................................................12
Figure 3-5. DLP LightCrafter DLPC910 EVM LEDs (Top View - Lower Left).............................................................................12
Figure 3-6. J3 Apps FPGA Test Point Header........................................................................................................................... 13
Figure 3-7. VC-707 SW5........................................................................................................................................................... 13
Figure 3-8. HPC FMC Cable (Front and Back)..........................................................................................................................14
Figure 3-9. DLPLCRC910EVM Female HPC FMC Connector..................................................................................................14
Figure 3-10. DLPLCR65FLQEVM Male HPC FMC Connector..................................................................................................14
Figure 3-11. DLPLCR90XEVM Male HPC FMC Connector.......................................................................................................14
Figure 3-12. Samtec 300 mm HPC FMC Extension cable (Front and Back).............................................................................15
Figure 3-13. Assembled DLPLCRC910EVM with DLPLCR65FLQEVM (without cable)........................................................... 15
Figure 3-14. Assembled DLPLCRC910EVM with DLPLCR90XEVM or DLPLCR90XUVEVM (without cable)......................... 15
Figure 3-15. Assembled DLPLCRC910EVM with DLPLCR65FLQEVM (with cable)................................................................ 16
Figure 3-16. Assembled DLPLCRC910EVM with DLPLCR90XEVM or DLPLCR90XUVEVM (with cable).............................. 16
Figure 3-17. AMD VC-707 Board Dip Switch Settings...............................................................................................................17
Figure 3-18. DLPLCRC910EVM Male HPC FMC Connectors (for Apps FPGA Board)............................................................ 17
Figure 3-19. AMD Xilinx VC-707 Female HPC FMC Cable Connectors................................................................................... 17
Figure 3-20. Assembled DLPLCRC910EVM with AMD Xilinx VC-707 board (without cables)................................................. 18
Figure 3-21. Fully Assembled DLPLCRC910EVM - AMD Xilinx VC-707 - DLPLCR65FLQEVM (without cables).................... 18
Figure 3-22. Fully Assembled DLPLCRC910EVM - AMD Xilinx VC-707 - DLPLCR90XEVM or DLPLCR90XUVEVM
(without cables)...................................................................................................................................................................... 18
Figure 3-23. Assembled DLPLCRC910EVM with AMD Xilinx VC-707 board (with cables)...................................................... 19
Figure 3-24. Fully Assembled DLPLCRC910EVM - AMD Xilinx VC-707 - DLPLCR65FLQEVM (with cables)......................... 20
Figure 3-25. Fully Assembled DLPLCRC910EVM - AMD Xilinx VC-707 - DLPLCR90XEVM or DLPLCR90XUVEVM
(with cables)........................................................................................................................................................................... 20
Figure 5-1. DLPLCRC910EVM GUI.......................................................................................................................................... 22
Figure 5-2. High DPI Settings.................................................................................................................................................... 23
Figure 5-3. File Menu.................................................................................................................................................................24
Figure 5-4. Control Menu...........................................................................................................................................................24
Figure 5-5. Help Menu............................................................................................................................................................... 24
Figure 5-6. About Box................................................................................................................................................................25
Figure 5-7. Icon Bar................................................................................................................................................................... 25
Figure 5-8. Load Tab..................................................................................................................................................................26
Figure 5-9. Reset Tab................................................................................................................................................................ 28
Figure 5-10. Clear Tab............................................................................................................................................................... 29
Figure 5-11. Float Tab................................................................................................................................................................30
Figure 5-12. Control Tab............................................................................................................................................................ 31
Figure 5-13. Script Sub-Window................................................................................................................................................33
Figure 5-14. Status sub-window................................................................................................................................................ 34
Figure 5-15. Status/Control Tab.................................................................................................................................................34
Figure 5-16. Status items...........................................................................................................................................................35
Figure 5-17. DMD Control section............................................................................................................................................. 36
Figure 5-18. Design Items......................................................................................................................................................... 37
Figure 5-19. DLPC910 Register List Tab................................................................................................................................... 38
Figure 5-20. DLPC910 I2C Address Settings Tab......................................................................................................................44
Figure 5-21. Status/Control Tab.................................................................................................................................................45
Figure 5-22. Status Items.......................................................................................................................................................... 46
Figure 5-23. PBC Control section.............................................................................................................................................. 47
Figure 5-24. Row/Block Operations...........................................................................................................................................48
Figure 5-25. Test Pattern Items................................................................................................................................................. 50
Figure 5-26. Apps Registers Tab............................................................................................................................................... 52
Figure 5-27. VC-707 USB-JTAG Port........................................................................................................................................ 63
Figure 5-28. USB Control Center Window.................................................................................................................................64
Figure 5-29. FX2/64KB EEPROM............................................................................................................................................. 64
Figure 5-30. Select File to Download Dialog............................................................................................................................. 64
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List of Tables
Table 3-1. DLPLCRC910EVM Connector Reference.................................................................................................................. 9
Table 3-2. DLP LightCrafter DLPC910 EVM LED Reference.................................................................................................... 12
Table 5-1. DESTOP_INTERRUPT_CLEAR Definition...............................................................................................................39
Table 5-2. DESTOP_INTERRUPT_SET Definition....................................................................................................................39
Table 5-3. DESTOP_INTERRUPT_ENABLE Definition.............................................................................................................39
Table 5-4. MAIN_STATUS Definition......................................................................................................................................... 40
Table 5-5. DESTOP_CAL Definition.......................................................................................................................................... 41
Table 5-6. DESTOP_DMD_ID_REG Definition..........................................................................................................................41
Table 5-7. DESTOP_CATBITS_REG Definition.........................................................................................................................41
Table 5-8. DESTOP_910VERSION_REG Definition................................................................................................................. 41
Table 5-9. DESTOP_RESET_REG Definition............................................................................................................................42
Table 5-10. DESTOP_INFIFO_STATUS Definition....................................................................................................................42
Table 5-11. DESTOP_BUS_SWAP Definition............................................................................................................................42
Table 5-12. DESTOP_DMDCTRL Definition..............................................................................................................................43
Table 5-13. DESTOP_BIT_FLIP Definition................................................................................................................................ 43
Table 5-14. APPS_INTERRUPT_CLEAR Definition..................................................................................................................53
Table 5-15. APPS_INTERRUPT_SET Definition.......................................................................................................................53
Table 5-16. APPS_INTERRUPT_ENABLE Definition................................................................................................................54
Table 5-17. MAIN_STATUS Definition....................................................................................................................................... 54
Table 5-18. APPS_CNTRL Definition........................................................................................................................................ 55
Table 5-19. APPSTOP_PATTERNSEL Definition...................................................................................................................... 56
Table 5-20. APPSTOP_TEST_ROWADDR Definition............................................................................................................... 57
Table 5-21. APPSTOP_LOADER_RESET_TYPE Definition.....................................................................................................57
Table 5-22. DMD_TYPEREG Definition.....................................................................................................................................57
Table 5-23. APPS_BUFFER_WSTART Definition..................................................................................................................... 58
Table 5-24. APPS_FIFO_BURST Definition.............................................................................................................................. 58
Table 5-25. APPS_ROW_CTRL Definition................................................................................................................................ 58
Table 5-26. APPS_BLK_CTRL Definition.................................................................................................................................. 58
Table 5-27. APPS_ROW_LOADER Definition...........................................................................................................................58
Table 5-28. APPS_LOAD_TRIG_INTERVAL Definition.............................................................................................................59
Table 5-29. APPS_EXPOSE_TIME Definition........................................................................................................................... 59
Table 5-30. APPS_LOADER_CTRL Definition.......................................................................................................................... 59
Table 5-31. APPS_DMD_PARK Definition.................................................................................................................................60
Table 5-32. APPS_EXT_RST_EVT Definition........................................................................................................................... 60
Table 5-33. APPS_BUILD_DATE Definition...............................................................................................................................61
Table 5-34. APPS_VERSION Definition.................................................................................................................................... 61
Table 5-35. APPS_FIXED_ID Definition.................................................................................................................................... 61
Table 5-36. APPS_GPIF_TEST Definition.................................................................................................................................61
Table 6-1. Micro B USB 2.0 Receptacle Connector Pins...........................................................................................................66
Table 6-2. I2C Connector Pins................................................................................................................................................... 66
Table 6-3. PMBUS (I2C) Connector Pins................................................................................................................................... 66
Table 6-4. USB GPIO Connector Pins....................................................................................................................................... 67
Table 6-5. Alternate Power Connector Pins...............................................................................................................................67
Table 6-6. Power Connector Pins.............................................................................................................................................. 68
Table 6-7. JTAG Boundary Scan Connector Pins......................................................................................................................68
Table 6-8. SPI Programming Connector Pins............................................................................................................................ 69
Table 6-9. Fan Connector Pins.................................................................................................................................................. 69
Trademarks
LightCrafter™ is a trademark of Texas Instruments.
Samtec™ is a trademark of Samtec Inc.
EZ-USB™ is a trademark of Infineon.
DLP® is a registered trademark of Texas Instruments.
Virtex® is a registered trademark of AMD.
Digilent® is a registered trademark of National Instruments.
All trademarks are the property of their respective owners.
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1 Overview
This guide explains the hardware features of the DLP LightCrafter DLPC910 EVM (DLPLCRC910EVM) system
and operation of the DLPC910 Graphical User Interface (GUI). The EVM architecture and connectors are
described along with a quick start guide on how to connect a supported DMD EVM and an AMD Xilinx
VC-707 Evaluation Board (or equivalent) to the DLPLCRC910EVM to run patterns. A separate Virtex® 7 field
programmable gate array (FPGA) Code User Guide [Link here] can be used to display patterns. Specific details
for each DLP component can be found in related component documentation.
Note
DMD EVMs, the AMD Xilinx VC-707 evaluation board, power supply, optics, illumination source, and
FPGA Mezzanine Card (FMC) cables are sold separately.
Figure 1-1. DLP LightCrafter DLPC910 Evaluation Module
2 If You Need Assistance
Refer to the TI E2E DLP products forum.
Overview www.ti.com
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3 DLP LightCrafter DLPC910 EVM (DLPLCRC910EVM) Overview
3.1 Welcome
The DLPLCRC910EVM, coupled to a supported DMD EVM allows for easy evaluation of the DLP LightCrafter
subsystem in bringing together high speed and high resolution display with advanced pattern control which is an
excellent choice for:
• Lithography applications
– Direct imaging
– Flat panel display
– Printed circuit board manufacturing
• Industrial
– 3D printing
– 3D scanners for machine vision
– Quality control
• High speed imaging and display
– 3D imaging
– Augmented reality and information overlay
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3.2 DLP LightCrafter DLPC910 Evaluation Module (DLPLCRC910EVM) Hardware
The DLPLCRC910EVM is one third of a complete DMD imaging electronics subsystem. The DLP LightCrafter
DLPC910 EVM (DLPLCRC910EVM) consists of the DLPC910 board which includes a DLPC910 Digital
Controller, a USB interface, power management circuits, and supporting digital logic.
Also needed to complete the imaging subsystem is a compatible DLP LightCrafter DMD EVM which is
compatible with the DLPLCRC910EVM and an Apps FPGA board or other front end to send patterns to the
DLPC910 controller. A DMD EVM consists of a DMD, a DMD board (PCB) containing on-board DMD power
circuits, DMD mounting hardware when necessary, and a high pin count (HPC) FPGA mezzanine connector
(FMC) cable for connections to the DLPC910 board.
Figure 3-1- block diagram outlining the major components of the DLPLCRC910EVM System Hardware.
DLP6500FLQ
DLP9000X
DLP9000XUV
DLPC910 Power
Management
DLPLCRC910EVM
Board
DLPLCR65FLQEVM
DLPLCR90XEVM
DLPLCR90XUVEVM
Solid state memory
Connectors
Other
TI DLP chipset
Apps FPGA
DMD EVM
DLPC910 EVM
FPGA Board
GPIF
Figure 3-1. DLPLCRC910EVM Hardware Components
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3.3 DLPLCRC910EVM Board
The DLPLCRC910EVM contains the electronics capable of controlling supported DMDs. The EVMs offer several
interface options, USB, I2C, a trigger input, and HPC FMC connectors to connect a supported DMD EVM board
and an input board. Figure 3-2 shows the EVM block diagram of the DLPLCRC910EVM.
DLPC910
SPI
Flash
USB
I2C
DLPLCR65FLQEVM
DLPLCR90XEVM
DLPLCR90XUVEVM
Trigger In
JTAG
12 V
POWER MANAGEMENT UNIT
HPC FMC
Connector
D2-CALIBRATION
D3-INIT DONE
DLPC_CFG_FCSZ
DLPC_CFG_DIN
3.3 V
DLPC_CFG_DOUT
ConnectorsSolid state memory
Other
TI DLP chipset TI Component
SPI Flash
Programming
Connector
SW1
D4- +12 VDC
D6-POWERGOOD
D1-HEARTBEAT
2.5 V 1.8 V 1.0 V
HPC FMC
Connector
HPC FMC
Connector
Apps FPGA
FPGA BOARD
D7-EPC2_FINISHED
USB GPIO
GPIF
SCL0/SDA0
Figure 3-2. DLP LightCrafter DLPC910 EVM Block Diagram
The DLPLCRC910EVM major components are:
• DLPC910 Digital DMD Controller
• USB 2.0 interface
• Power Management Unit to supply power supplies to support the DLPC910 subsystem
• HPC FMC Connectors - one for a supported DMD EVM board and two for an attached FPGA or other front
end board
• DLPC910 configuration SPI Flash memory
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3.4 Other Items Needed for Operation
The DLPLCRC910EVM is a flexible evaluation module which, when coupled to one of the supported DLP DMD
EVMs and an APPS FPGA board enables the sending of customer created patterns to the DLPC910 Controller,
and then to the attached DMD for display. The DLP LightCrafter DLPC910 EVM and the supported DMD EVMs
are offered for purchase separately so that customers can determine which elements customers wish to piece
together for an application evaluation system.
The following items are not included with the EVM and need to be purchased separately if needed for customer
evaluation:
• Supported DMD EVM board [DLPLCR65FLQEVM, DLPLCR90XEVM, or DLPLCR90XUVEVM]
• APPS FPGA board - example: AMD Xilinx VC-707 Evaluation Board (with separate power supply).
• Power supply - see Section 7.1 External Power Supply Requirements for details
• USB cable: A to Micro-B USB cable
• Illumination module or source
• Illumination and projection optics
3.5 DLPLCRC910EVM Connections
Figure 3-3 depicts the switches and connectors with their respective locations. Note: DMD EVM board, APPS
FPGA board, power supply (and cable), and USB cable are NOT included with the module.
SW2
J5
SW3
J10
J19
J20
J21
J15 J14 J6 J4 J2
J1
SW1
J7
SW4
J3
J16
J13
J17
J18
J22J12
J11
J9
J8
J501 J500
Figure 3-3. DLPLCRC910EVM Connectors (Top View)
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Table 3-1. DLPLCRC910EVM Connector Reference
Connector
Reference EVM Function Description or Use
SW1 Apps FPGA Reset Switch Momentary contact switch to reset the Apps FPGA GUI code running on the attached
AMD Xilinx VC-707 EVM. When released, the Apps FPGA boots from reset.
SW2 8 Position Apps FPGA Options
dip switch
Used for selecting Apps FPGA options:
• SW2_0: MIRROR FLOAT - Mirror Float Enable (Default not enabled = switch OFF)
• SW2_1: LOAD4_ENZ - Load 4 enable switch. (Default not enabled = switch OFF)
• SW2_2: COMP_DATA - Compliment Data (Default not enabled = switch ON)
• SW2_3: NS_FLIP - Top to bottom flip (Default = not enabled switch ON)
• SW2_4: Not Used (Default = switch ON)
• SW2_5: Not Used (Default = switch ON)
• SW2_6: Not Used (Default = switch ON)
• SW2_7: WDT_ENZ - Watchdog timer enable (Default not enabled = switch ON)
By default, positions 1 and 2 are in the switch "OFF" position [logic 1].
Note
The inputs connected to SW2 are pulled high through a pullup resistor
when in the "OFF" position [logic 1] and pulled low when in the "ON"
position [logic 0]. Positions 0 and 1 are not enabled when the switch is
"OFF" [logic 1] and positions 2, 3, and 7 are not enabled when "ON" [logic
0].
SW3 DMD Park
Turning this switch off issues PWR_FLOAT and parks the DMD and stops the
DLPC910 logic.
Note
Turn this switch off before disabling power with SW4 and turn this switch
on before enabling power with SW4.
Once SW3 is turned off a full power cycle using SW4 is required to
restore operation.
SW4 Power Enable Switch
Enables Power on the DLPLCRC910EVM.
Note
Turn on SW3 (PWR_FLOAT - DMD Park) before enabling power and turn
off SW3 before disabling power.
J1 Micro USB B Connector Connect USB cable from PC running DLPC910 GUI.
J2 External I2C PMBUS I2C connector.
J3 Apps FPGA Test Points 0 - 7
Apps FPGA connected test points:
• GND: Pin 1
• APPS_TSTPT7: Pin 2 -Apps FPGA DLPC910 Trigger (input)
• APPS_TSTPT6: Pin 3 - debounced SW5 push button (output)
• APPS_TSTPT5: Pin 4 - data enable from apps loader (output)
• APPS_TSTPT4: Pin 5 - load busy from apps loader (output)
• APPS_TSTPT3: Pin 6 - mirror settling busy from apps loader (output)
• APPS_TSTPT2: Pin 7 - trigger from the apps loader (output)
• APPS_TSTPT1: Pin 8 - mirror reset busy from apps loader (output)
• APPS_TSTPT0: Pin 9 - mirror reset active signal (output)
• GND: Pin 10
J4 External PMBUS PMBUS connector for TI development and test only.
J5 Prom address select Prom address select for USB firmware load [default address 001 - not populated;
address 011 - populated].
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Table 3-1. DLPLCRC910EVM Connector Reference (continued)
Connector
Reference EVM Function Description or Use
J6 USB GPIO B0 - B7
USB GPIO Header:
• GND: Pin 1
• USB GPIO B7: Pin 2
• USB GPIO B6: Pin 3
• USB GPIO B5: Pin 4
• USB GPIO B4: Pin 5
• USB GPIO B3: Pin 6
• USB GPIO B2: Pin 7
• USB GPIO B1: Pin 8
• USB GPIO B0: Pin 9
• GND: Pin 10
These pins are available for customer definition or future use.
J7 DCLKIN Speed Selection Pin 1
SPEED_SEL_1 used in conjunction with J11 (SPEED_SEL_0) to select 400 or 480
MHz operation. Routed to Apps FPGA.
Configurations:
• 400 MHz: J7 and J11 jumpered - DLP6500FLQ, DLP9000X, or DLP9000XUV
(default)
• 480 MHz: J7 jumpered and J11 not jumpered - DLP9000X and DLP9000XUV only
Note
The DLPLCR65FLQEVM does NOT run at 480 MHz.
J8 DMD EVM Board HPC FMC
Connector Used to connect a DLPLCR65FLQEVM, DLPLCR90XEVM, or DLPLCR90XUVEVM.
J9 DLPC910 Test Points 8 - 15
DLPC910 connected test points:
• GND: Pin 1
• DLPC_TSTPT8: Pin 2
• DLPC_TSTPT9: Pin 3
• DLPC_TSTPT10: Pin 4
• DLPC_TSTPT11: Pin 5
• DLPC_TSTPT12: Pin 6
• DLPC_TSTPT13: Pin 7
• DLPC_TSTPT14: Pin 8
• DLPC_TSTPT15: Pin 9
• GND: Pin 10
Reserved for TI internal testing and debug.
J10 DLPC910 I2C Address Selector
Jumper
Selects the DLPC910 I2C Address:
• 0x36: Not jumpered (default)
• 0x34: Jumpered
Note
If installed, then use the DLPC910 Status/Control Registers Settings
page to change the I2C address to operate correctly.
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Table 3-1. DLPLCRC910EVM Connector Reference (continued)
Connector
Reference EVM Function Description or Use
J11 DCLKIN Speed Selection Pin 0
SPEED_SEL_0 used in conjunction with J7 (SPEED_SEL_1) to select 400 or 480
MHz operation. Routed to Apps FPGA.
Configurations:
• 400 MHz: J7 and J11 jumpered - DLP6500FLQ, DLP9000X, or DLP9000XUV
(default)
• 480 MHz: J7 jumpered and J11 not jumpered - DLP9000X and DLP9000XUV only
Note
The DLPLCR65FLQEVM does not run at 480 MHz.
Although the DLP9000X and DLP9000XUV run at 400 MHz, only 480
MHz operation has been fully validated.
J12 VSP Enable (no longer used) This jumper is no longer used.
J13 DLPC910 Test Points 0 - 7
DLPC910 connected test points:
• GND: Pin 1
• DLPC_TSTPT0: Pin 2
• DLPC_TSTPT1: Pin 3
• DLPC_TSTPT2: Pin 4
• DLPC_TSTPT3: Pin 5
• DLPC_TSTPT4: Pin 6
• DLPC_TSTPT5: Pin 7
• DLPC_TSTPT6: Pin 8
• DLPC_TSTPT7: Pin 9
• GND: Pin 10
Reserved for TI internal testing and debug.
J14 +12 VDC 6-Pin Power Connector
(Alternate) EVM power alternate input. [Pin 1,2,3 = GND, Pin 4,5,6 = +12 VDC, ] See Section 7.1.
J15 +12 VDC Power input EVM power input. [Pin 1 = +12 VDC, Pin 2,3 = GND] See Section 7.1.
J16 REV_SEL_0
DLPR910 Configuration Prom Revision Selection Jumper. REV_SEL_1 is held low.
• Not jumpered = 0 (default)
• Jumpered = 1 - Not Used
J17 JTAG Connector JTAG header for connecting a JTAG programmer to the DLPR910.
J18 Flash Configuration Connector SPI Flash programming connector.
J19, J20, J21 +12 VDC external Fan
Connectors 2-pin +12 VDC fan connectors [Pin 1 = GND, Pin 2 = +12 VDC]
J22 Apps FPGA Reset Jumper
Jumper 22 prevents SW1 from pulling the Apps FPGA on the attached AMD Xilinx
VC-707 EVM into reset.
• Not jumpered = Allows SW1 to pull the Apps FPGA into reset (default)
• Jumpered = Prevent SW1 from pulling Apps FPGA into reset
J500 Apps FPGA FMC connector 1 DLPC910 to Apps FPGA and USB parallel interface to the Apps FPGA 400 pin FMC
connector.
J501 Apps FPGA FMC connector 2 DLPC910 to the Apps FPGA 400 pin FMC connector.
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3.6 DLP LightCrafter DLPC910 LEDs
DLP LightCrafter DLPC910 EVM LEDs (Top View - Upper Left) and DLP LightCrafter DLPC910 EVM LEDs (Top
View - Lower Left) depicts the LEDs with their respective locations:
D5 D4 D3 D2 D1D6
Figure 3-4. DLP LightCrafter DLPC910 EVM LEDs
(Top View - Upper Left)
D7
Figure 3-5. DLP LightCrafter DLPC910 EVM LEDs
(Top View - Lower Left)
Table 3-2. DLP LightCrafter DLPC910 EVM LED Reference
Connector
Reference EVM Function Description or Use
D1 Heartbeat LED [Flashing] Flashes when DLPC910 controller is running
D2 Calibration Active Illuminates while calibration is active
D3 DLPC910 Done DLPC910 Initialization complete
D4 12 V Power +12 VDC is present on the input connector
D6 Power Good All voltages are present and stable
D7 ECP2 Finished DLPC910 configuration via SPI Flash complete
Note
D5 is a protection Zener diode for the +12 VDC input and is not an LED.
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3.7 Apps FPGA Trigger Input
On the DLPLCRC910EVM the trigger input for the DLPC910 is mediated through the Apps FPGA.
Connecting header J3 APPS_TSTPT7 (Pin 2) to J3 APPS_TSTPT6 (Pin 3) allows the use of SW5 on the AMD
Xilinx VC-707 board (lower right corner) to advance patterns when pressed.
Figure 3-6. J3 Apps FPGA Test Point Header
Figure 3-7. VC-707 SW5
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3.8 DLPLCRC910EVM HPC FMC Cables
DMD EVMs supported by the DLPLCRC910EVM come supplied with a 300 mm Samtec™ 400-pin HPC FMC
cable [SAMTEC HDR-169468-01]. HPC FMC Cable (Front and Back) shows the front and back of the cable. The
cable is keyed and can only be installed one way on the DLPLCRC910EVM and on the DMD EVM. As shows
the left end is the DLPLCRC910EVM end and the right end is the DMD EVM end.
Use of the cable is optional. The EVM can be connected directly to the DLP LightCrafter DLPC910 EVM J8 HPC
FMC connector.
Figure 3-8. HPC FMC Cable (Front and Back)
Use caution when bending the flex cable to not exceed bending guidelines provided by the cable manufacturer.
3.9 DLPLCRC910EVM and DMD EVM Assembly
The DLPC910 EVM requires a compatible DMD EVM such as the DLPLCR65FLQEVM, DLPLCR90XEVM, or
DLPLCR90XUVEVM.
• The DMD EVM male HPC FMC connector can be connected directly to the DLPLCRC910EVM female HPC
FMC connector
• The 300 mm Samtec HPC FMC ribbon cable provided with the DMD EVMs can be used to provide more
flexibility in the positioning of the DMD board relative to the DLPLCRC910EVM board. Attach the HPC FMC
male connector end of the cable to the female HPC FMC connector on the DLPLCRC910EVM board and the
HPC FMC female end of the cable to the male HPC FMC connector on the DMD EVM board.
Figure 3-9. DLPLCRC910EVM Female HPC FMC Connector
Figure 3-10. DLPLCR65FLQEVM Male HPC FMC Connector
Figure 3-11. DLPLCR90XEVM Male HPC FMC Connector
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Figure 3-12. Samtec 300 mm HPC FMC Extension cable (Front and Back)
Figure 3-13. Assembled DLPLCRC910EVM with
DLPLCR65FLQEVM (without cable)
Figure 3-14. Assembled DLPLCRC910EVM with
DLPLCR90XEVM or DLPLCR90XUVEVM (without
cable)
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Figure 3-15. Assembled DLPLCRC910EVM with
DLPLCR65FLQEVM (with cable) Figure 3-16. Assembled DLPLCRC910EVM with
DLPLCR90XEVM or DLPLCR90XUVEVM (with
cable)
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3.10 Connecting an Apps FPGA Board to the DLPLCRC910EVM
The DLPLCRC910EVM requires a compatible Apps board, such as the AMD Xilinx VC-707 board or similar to
send control and pixel data to the DLPLCRC910EVM.
If using the AMD VC-707 board, set SW2- 1 ON and SW11-4 ON as shown in AMD VC-707 Board Dip Switch
Settings.
SW2
SW11
Figure 3-17. AMD VC-707 Board Dip Switch Settings
• The APPS female HPC FMC connectors connect directly to the DLPLCRC910EVM male HPC FMC
connectors
– Line up the HPC FMC male connectors on the DLPLCRC910EVM with the HPC FMC female connectors
on the Apps FPGA board.
Note
Verify that the connectors are lined up correctly before applying pressure to connect the boards.
– Firmly apply pressure to the boards to allow the connectors to fully mate. After the initial application of
pressure, apply pressure at one end and then the other until the connectors are fully seated.
Figure 3-18. DLPLCRC910EVM Male HPC FMC Connectors (for Apps FPGA Board)
Figure 3-19. AMD Xilinx VC-707 Female HPC FMC Cable Connectors
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Figure 3-20. Assembled DLPLCRC910EVM with AMD Xilinx VC-707 board (without cables)
Figure 3-21. Fully Assembled DLPLCRC910EVM -
AMD Xilinx VC-707 - DLPLCR65FLQEVM (without
cables) Figure 3-22. Fully Assembled DLPLCRC910EVM
- AMD Xilinx VC-707 - DLPLCR90XEVM or
DLPLCR90XUVEVM (without cables)
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The 300 mm Samtec HPC FMC ribbon cables are an alternative for these connections. Two cables are needed.
The board and cable connectors are keyed.
• Attach the HPC FMC female connector end of the cables to the male HPC FMC connectors on the
DLPLCRC910EVM board.
• Attach the HPC FMC male connector end of the cables to the female HPC FMC connectors on the Apps
FPGA board .
Figure 3-23. Assembled DLPLCRC910EVM with AMD Xilinx VC-707 board (with cables)
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Figure 3-24. Fully Assembled DLPLCRC910EVM
- AMD Xilinx VC-707 - DLPLCR65FLQEVM (with
cables)
Figure 3-25. Fully Assembled DLPLCRC910EVM
- AMD Xilinx VC-707 - DLPLCR90XEVM or
DLPLCR90XUVEVM (with cables)
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