Signal Path and Control Switches
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Setup Procedure:
1. Verify the output mode control switches, S1[1:5], match the states shown in Table 1 to reflect the
default output clock interfaces configured on the EVM.
Table 1. Default Clock Output Modes
SW Position/Name SW State Default Clock Output Modes
S1[2] / CLKoutB_A_EN OFF Bank A outputs enabled
S1[4] / CLKoutB_B_EN OFF Bank B outputs enabled
S1[5] / REFout_EN ON REFout (CMOS) enabled
2. Connect a 4 to 6 V power supply to VCC_EXT and GND terminals of the power block labeled J2. This
powers the on-board LDO regulator to supply 3.3 V to the VCC and VCCO rails of the IC. Both VCC &
VCCO status LEDs should be lit green when ON.
3. Set the desired clock input using the input selection control switches, S1[6:7], as seen in Table 2. The
onboard 25 MHz crystal (Y1) can be selected, so an external clock source is not required. A differential
clock source can be connected to SMAs labeled CLKin0/0* or CLKin1/1*. By default, these differential
inputs are AC coupled and terminated near the device with 100 Ωdifferential. To configure the EVM for
a single-ended input, refer to the Clock Inputs section.
Table 2. Input Selection
Selected Input Default Input Mode S1[6] CLKin_Sel1 State S1[7] CLKin_Sel0 State
CLKin0/0* Differential clock OFF OFF
CLKin1/1* Differential clock OFF ON
OSCin 25 MHz XTAL onboard ON Don't care
4. Connect and measure any clock output SMA labeled CLKoutA#/A#*, CLKoutB#/B#*, or REFout to an
oscilloscope or other test instrument using SMA cable(s). The output clock will be a level-
translated/buffered copy of the selected clock input or crystal oscillator. Note: All output clocks are DC-
coupled to the SMA connectors.
Note: Any active output trace(s) without proper load termination can cause signal reflections on the
board, which can couple onto nearby outputs and degrade signal quality and measurement accuracy.
To minimize these effects, be sure to properly terminate any unused output trace with a 50 ΩSMA
load, or else disconnect any unused output trace from the device output pin by removing the series 0 Ω
resistor. An unused output or output bank may also be disabled using the output mode control switch.
4 Signal Path and Control Switches
The LMK00338 supports single-ended or differential clocks on CLKin0 and CLKin1. A third input, OSCin,
has an integrated crystal oscillator interface that supports a fundamental mode, AT-cut crystal or an
external single-ended clock. To achieve the maximum operating frequency and lowest additive jitter, it is
recommended to use a differential input clock with high slew rate (>3 V/ns) on either CLKin0 or CLKin1
port.
The device provides up to 8 HCSL outputs with pin-selectable output enable (HCSL, or Hi-Z). An
additional output, REFout, has a fixed LVCMOS buffer with output enable input.
All control pins are configured with the control DIP switch, S1. The input selection logic is shown in
Table 2. The output enable selection logic for Bank A and Bank B are shown in Table 1. The REFout
enable logic is shown in Table 3.
Table 3. REF out Enable Selection
REFout Enable Mode S1[5] REFout_EN State
Disabled/Hi-Z OFF
Enabled ON
4LMK00338EVM User Guide SNAU155–November 2013
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