Texas Instruments LMK00338EVM User manual

LMK00338EVM
User's Guide
Literature Number: SNAU155
November 2013

User's Guide
SNAU155–November 2013
LMK00338EVM User Guide
This user guide describes how to set up and operate the LMK00338 evaluation module (EVM). The
LMK00338 is a 400 MHz, 8-output HCSL clock buffer intended for high frequency, low additive jitter clock
distribution and level translation. The EVM allows the user to verify the functionality and performance
specifications of the device. Refer to the LMK00338 datasheet for the functional description and
specifications.
Topic ........................................................................................................................... Page
1 General Description ............................................................................................ 3
2 Features ............................................................................................................. 3
3 Quick Setup ....................................................................................................... 3
4 Signal Path and Control Switches ......................................................................... 4
5 Power Supplies ................................................................................................... 5
6 Clock Inputs ....................................................................................................... 6
7 Crystal Oscillator Interface ................................................................................... 7
8 Clock Outputs .................................................................................................... 7
9 Schematics ........................................................................................................ 8
10 Board Layout .................................................................................................... 11
11 Bill of Materials ................................................................................................. 13
All trademarks are the property of their respective owners.
2LMK00338EVM User Guide SNAU155–November 2013
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LMK0033x
EVALUATION
MODULE
CLKinX
CLKinX*
VCC_EXT
GND
Bank A Outputs
(DC Coupled HCSL)
REFout
(LVCMOS)
Bank B Outputs
(DC Coupled HCSL)
Bottom side:
25 MHz Crystal
(Default Input)
CLKoutBn
CLKoutBn*
CLKoutAn
CLKoutAn*
O-SCOPE
(50Ω inputs)
50Ω TERM
50Ω TERM
Note: Terminate unused
output traces (or disconnect
from output pin on PCB)
CLOCK
SOURCE
(OPTIONAL)
50Ω TERM
4 to 6 V
GND
POWER
SUPPLY
www.ti.com General Description
1 General Description
2 Features
• Low-noise clock fan-out via two banks of four HCSL outputs and one LVCMOS output
• 3:1 input multiplexer with two universal input buffers and one crystal oscillator interface
• DIP switch control of device configuration
• 3.3 V core and 3 independent 3.3 V/2.5 V output supplies (one per output bank) using external supply
inputs or optional LP3878-ADJ LDO or LMZ10500 switching regulator on board
• AC- or DC-coupled input & output interface with low-skew, controlled-impedance traces and edge SMA
connectors
3 Quick Setup
To quickly set up and operate the board with basic equipment, refer to the setup procedure below and test
setup shown in Figure 1.
Figure 1. LMK00338 Evaluation Board Quick Start Setup
3
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Signal Path and Control Switches www.ti.com
Setup Procedure:
1. Verify the output mode control switches, S1[1:5], match the states shown in Table 1 to reflect the
default output clock interfaces configured on the EVM.
Table 1. Default Clock Output Modes
SW Position/Name SW State Default Clock Output Modes
S1[2] / CLKoutB_A_EN OFF Bank A outputs enabled
S1[4] / CLKoutB_B_EN OFF Bank B outputs enabled
S1[5] / REFout_EN ON REFout (CMOS) enabled
2. Connect a 4 to 6 V power supply to VCC_EXT and GND terminals of the power block labeled J2. This
powers the on-board LDO regulator to supply 3.3 V to the VCC and VCCO rails of the IC. Both VCC &
VCCO status LEDs should be lit green when ON.
3. Set the desired clock input using the input selection control switches, S1[6:7], as seen in Table 2. The
onboard 25 MHz crystal (Y1) can be selected, so an external clock source is not required. A differential
clock source can be connected to SMAs labeled CLKin0/0* or CLKin1/1*. By default, these differential
inputs are AC coupled and terminated near the device with 100 Ωdifferential. To configure the EVM for
a single-ended input, refer to the Clock Inputs section.
Table 2. Input Selection
Selected Input Default Input Mode S1[6] CLKin_Sel1 State S1[7] CLKin_Sel0 State
CLKin0/0* Differential clock OFF OFF
CLKin1/1* Differential clock OFF ON
OSCin 25 MHz XTAL onboard ON Don't care
4. Connect and measure any clock output SMA labeled CLKoutA#/A#*, CLKoutB#/B#*, or REFout to an
oscilloscope or other test instrument using SMA cable(s). The output clock will be a level-
translated/buffered copy of the selected clock input or crystal oscillator. Note: All output clocks are DC-
coupled to the SMA connectors.
Note: Any active output trace(s) without proper load termination can cause signal reflections on the
board, which can couple onto nearby outputs and degrade signal quality and measurement accuracy.
To minimize these effects, be sure to properly terminate any unused output trace with a 50 ΩSMA
load, or else disconnect any unused output trace from the device output pin by removing the series 0 Ω
resistor. An unused output or output bank may also be disabled using the output mode control switch.
4 Signal Path and Control Switches
The LMK00338 supports single-ended or differential clocks on CLKin0 and CLKin1. A third input, OSCin,
has an integrated crystal oscillator interface that supports a fundamental mode, AT-cut crystal or an
external single-ended clock. To achieve the maximum operating frequency and lowest additive jitter, it is
recommended to use a differential input clock with high slew rate (>3 V/ns) on either CLKin0 or CLKin1
port.
The device provides up to 8 HCSL outputs with pin-selectable output enable (HCSL, or Hi-Z). An
additional output, REFout, has a fixed LVCMOS buffer with output enable input.
All control pins are configured with the control DIP switch, S1. The input selection logic is shown in
Table 2. The output enable selection logic for Bank A and Bank B are shown in Table 1. The REFout
enable logic is shown in Table 3.
Table 3. REF out Enable Selection
REFout Enable Mode S1[5] REFout_EN State
Disabled/Hi-Z OFF
Enabled ON
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www.ti.com Power Supplies
5 Power Supplies
The power supply section on the EVM provides flexibility to power the device using the onboard
regulator(s) or direct supply input(s). A combination of 0 Ωresistor options allows the user to modify the
EVM power supply configuration, if desired.
By default, 3.3 V is supplied to both VCC and VCCO rails by the onboard LDO regulator, U3. To power
the regulator, connect a 4 V to 6 V input voltage and ground from an external power source to the terminal
block, J2, or SMA input labeled VCC_EXT.
To modify the EVM with a different power supply configuration, populate the resistor options as shown in
Table 4. Then, apply the appropriate voltage(s) to the EVM power input(s).
If the EVM is configured for dual direct supplies, connect the 3.3 V supply and ground to VCC_EXT and
the 2.5 V supply and ground to the SMA input labeled VCCO_EXT.
Decoupling capacitors and 0 Ωresistor footprints, which can accommodate ferrite beads, can be used to
isolate the EVM power input(s) from the device power pins.
Table 4. EVM Power Supply Configuration Options
LP3878 LDO LMZ10500 Single Dual
Regulator (U3) Switcher (U2) Direct Supply Direct Supplies
3.3 V (DEFAULT) 3.3 V 3.3 V 3.3 V & 2.5 V
VCC_EXT port Apply 4 V to 6 V Apply 4 V to 5.5 V Apply 3.3 V ± 5% Apply 3.3 V ± 5%
(J2 or SMA)
VCCO_EXT port Not used Not used Not used Apply 2.5 V ± 5%
(SMA)
U2 Vout Not used 3.3 V (VCC & VCCO) Not used Not used
U3 Vout 3.3 V (VCC & VCCO) Not used Not used Not used
R131 OPEN OPEN OPEN 0
R132 0 0 0 0
R134 OPEN 0 OPEN OPEN
R145 OPEN 0 OPEN OPEN
R153 OPEN OPEN 0 0
R155 0 OPEN OPEN OPEN
R156 0 OPEN OPEN OPEN
5.1 Independent Output Supply Voltages
On the bottom side of the EVM, resistor options provide flexibility to power each of the three individual
output supply pins (VCCOA, VCCOB, and VCCOC) from either VCC or VCCO rail. This is useful when 3.3
V and 2.5 V are both needed for separate output supplies.
The EVM power supply needs to be modified to get 2.5 V on the VCCO rail, either using the VCCO_EXT
input or LMZ10500 switcher, as seen in Table 4. To configure LMZ10500 with 2.5 V output, set R138 to
150k and R139 to 118k.
Note: When the LMZ10500 switcher is used to power the DUT and an ultra-low-noise clock source is
used, the higher output noise voltage of the switcher (compared to the LP3878-ADJ) can cause an slight
increase in the output phase noise floor at low offset frequencies as well as low-level spurs. The high
PSRR of the device helps to minimize supply-induced jitter.
5
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Clock Inputs www.ti.com
6 Clock Inputs
The SMA inputs labeled CLKin0 & CLKin0* and CLKin1 & CLKin1* can be configured to receive a
differential clock or single-ended clock. Best performance is achieved with a differential input clock, which
is the default configuration for both CLKin ports.
Both CLKin0 and CLKin1 paths include footprint options to provide the user with flexibility in configuring
the termination, biasing, and coupling for the device inputs.
6.1 Configuring CLKinX+ for a Single Ended Input
To configure an AC-coupled or DC-coupled single-ended clock input on CLKin0, follow the steps below.
CLKin1 can be modified similarly.
1. Remove R24 (100 Ωdifferential termination).
2. Terminate CLKin0 (driven input) by installing 51 Ωon R30.
3. Install 0.1 uF on C10 as a bypass capacitor.
4. Modify for AC or DC coupled input:
(a) AC-coupled input: Install 0 Ωon R23, so CLKin0* input pin is AC coupled to ground via C17.
(b) DC-coupled input:
(i) Replace R22 and R28 with 0 Ωto DC couple the input path.
(ii) Bias CLKin0*(non-driven input) with a reference voltage near the common-mode voltage of the
DC-coupled input signal (on CLKin0) using R21 and R23 to form a voltage divider from VCC.
For example, if CLKin0 will be driven by a single-ended, DC-coupled LVCMOS signal with a common-
mode voltage of 1.65 V, then 1 kΩresistors can be installed on R21 and R23 to bias CLKin0* to VCC/2.
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www.ti.com Crystal Oscillator Interface
7 Crystal Oscillator Interface
The LMK00338 has an integrated crystal oscillator interface (OSCin/OSCout) that supports a fundamental
mode, AT-cut crystal. If the crystal input is selected, the onboard XTAL on either footprint Y1 or Y2 will
start- up and the oscillator clock can be measured on any enabled output.
By default, a 25.000 MHz XTAL is populated on Y1, which uses a HC49 footprint on the bottom side of the
PCB. Alternatively, a 3.2 x 2.5 mm XTAL or 3.3 V XO (3.3 V CMOS or clipped sinewave) can be
populated on Y2, located on the top side. Only one XTAL footprint should be used at a time.
When using a XTAL, the external load capacitor values of C18 and C22 (CEXT) depend on the specified
load capacitance (CL) for the crystal, as well as the device’s OSCin input capacitance (CIN = 1 pF typical)
and the PCB stray capacitance (CSTRAY ~ 1 pF). The selected 25 MHz crystal is specified for CLof 18 pF.
Assuming equal external load capacitor values for optimum symmetry, CEXT can be calculated as follows:
• CEXT = (CL- CIN - CSTRAY)x2
• CEXT =(18pF-1pF-1pF)x2
• CEXT ~ 33 pF (nearest standard value)
To limit crystal power dissipation, a 1 kΩresistor is placed between the OSCout pin and the crystal.
7.1 Configuring OSCin for a Single Ended Input
To configure a single-ended clock input on OSCin, remove R34 and R37 to disconnect the crystal. Install
0.1 uF on C24 to provide an AC-coupled path from the SMA input labeled OSCin to the device input,
which has internal biasing. Note that the OSCin path includes a 51Ωtermination on R42.
8 Clock Outputs
By default, Bank A and B are configured as enabled HCSL outputs, source-terminated with 50 Ωresistors,
and DC coupled to the SMA connectors labeled CLKoutA#+ / CLKoutA#, or CLKoutB#+ / CLKoutB#–.
REFout is a LVCMOS output and is AC coupled to its SMA connector.
As noted before, active output traces should be properly terminated; otherwise any unused output pin can
be disconnected from the output trace by removing the 0 Ωseries resistor.
7
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Mod. Date:
File:
Sheet: of
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LMK00338EVMProject Title:
Designed for: Public Release
Assembly Variant:001
© Tex as Instruments 2013
Drawn By:
Engineer:
Not shown in title block
Julian Hagedorn
Texas Instruments and/or its licensors do not warrant the accuracy or completeness of this specification or any information contained therein. Texas Instruments and/or its licensors do
not warrant that this design will meet the specifications, will be suitable for your application or fit for any particular purpose, or will operate in an implementation. Texas Instruments and/or
its licensors do not warrant that the design is production worthy. You should completely validate and test your design implementation to confirm the system functionality for your
application.
Not in version controlSVN Rev:
SV601035Number: Rev: A
Revision History
Revision Notes
LMK00338 Evaluation Board
0
R153
DNP
0
R155
VCC_EXT
IN
4
ADJ 6
GND 3
NC
7
SD
8
DAP
9
OUT 5
BYP 1 NC
2
U3
LP3878SD-ADJ
10µF
C67
1µF
C68
0.01µF
C69
VCC
10µF
C72 10µF
C71
2200pF
C70
0.01µF
C73
51k
R157
2.00k
R158
866
R159
0
R156
0
R134
DNP
0
R145
DNP
1µF
C61
0.01µF
C62
VCCO
10µF
C60
0
R132
0
R131
DNP
270
R154
270
R133
1
2 3 4 5
VCC_EXT
1
2 3 4 5
VCCO_EXT
VCC
EN_REFout
2.0k
R140
2.0k
R141
2.0k
R142
2.0k
R143 2.0k
R135
3.9k
R150
DNP
3.9k
R146
DNP 3.9k
R147
DNP 3.9k
R148
DNP 3.9k
R149
DNP
CLKoutB_EN
CLKoutA_EN
CLKin_Sel1
CLKin_Sel0
Control Pin Switches and Header
VCC and VCCO Power Supplies
Default Switch Settings for Control Input Pins
S1[2] = 1'b ==> Output Bank B is Enabled
S1[4] = 1'b ==> Output Bank A is Enab led
S1[5] = 1'b ==> REFout is Enabled
S1[6:7] = 10'b ==> OSCin is Selected (25 MHz XTAL)
Switch States
0 = Switch Open / OFF (Control pin tied low via internal
pulldown)
1 = Switch Closed / ON (Control pin connected high to VCC)
A combination of 0 ohm resistor options allows flexibility in powering
the VCC and VCCO rails of the device using onboard LDO regulators
(U2, U3) or external supply(ies).
By default, one of the LDO regulators (U3) provides a low-noise 3.3 V
supply to both supply rails of the device. To power the device in single
supply operation from regulator U1, apply a single external input
voltage (4 V to 16 V) on VCC_EXT via the SMA input or terminal block
J2.
To power the device in single supply operation from an external 3.3 V
supply (bypass LDO regulators), open R131, R134, R145, R155,
R156, and install 0 ohms on R132 and R153. Then, apply 3.3 V to
VCC_EXT.
To power the device in split supply operation (3.3V, 2.5V) from both
onboard regulators (U3, U2), open R131, R132, and R153, and install
0 ohms on R134, R155, R156, and R156. Then, apply 4 V to 16 V on
VCC_EXT.
To power the device in split supply operation from external 3.3 V and
2.5 V supplies, open R132, R134, R145, R155, R156, and install 0
ohms on R131 and R153. Then, apply 3.3 V to VCC_EXT and 2.5 V
to VCCO_EXT.
10µF
C65
118k
R138
150k
R139
470pF
C63
10µF
C64
SV601035
A
PCB Number:
PCB Rev:
1
2
J2
1592820000
VCCO ON
12
D1
VCC ON
12
D2
H1
TCBS-6-01
H2
TCBS-6-01
H3
TCBS-6-01
H4
TCBS-6-01
1
2
3
4
5
6
13
14
15
16
7
12
8 9
10
11
S1
219-8MST
LDO_OUT
VCC EXT
VCC
VCCO EXT
SSW OUT
1 2
3 4
5 6
7 8
9 10
J1
HEADER_2X5
DNP
NC
9
PVIN 7
EN
1
PGND 6
VOUT 5
NC 10
VCON
2
VDD 8
NC 11
FB
3
SGND
4
U2
LM3218SEE/NOPB
DNP
Schematics www.ti.com
9 Schematics
Figure 2. Schematic Sheet #1
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Sheet Title:
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Mod. Date:
File:
Sheet: of
Bhttp://www.ti.com
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LMK00338EVMProject Title:
Designed fo r: Public Release
Assembly Variant:001
© Tex as Instruments 2013
Drawn By:
Engineer:
Not shown in title block
Julian Hagedorn
Texas Instruments and/or its licensors do not warrant the accuracy or completeness of this specification or any information contained therein. Texas Instruments and/or its licensors do
not warrant that this design will meet the specifications, will be suitable for your application or fit for any particular purpose, or will operate in an implementation. Te xas Instruments and/or
its licensors do not warrant that the design is production worthy. You should completely validate and test your design implementation to confirm the system functionality for your
application.
Not in version controlSVN Rev:
SV601035Number: Rev: A
CLKin1
SMA_C1_P
1
2 3 4 5
CLKin1-
DNP
DNP
1
2 3 4 5
CLKin1+
DNP
DNP
SMA_C1_N
U1_C1_P
U1_C1_N
1
2 3 4 5
CLKin0+
142-0701-806
1
2 3 4 5
CLKin0-
142-0701-806
SMA_C0_P
CLKin0
C0_P
C0_N
U1_C0_P
SMA_C0_N
U1_C0_N
CLKin+/CLKin- can accept a differential or single-ended input
clock. By default, CLKin is configured to accept a differential
clock expecting a 100 ohm differential load. The input is DC
coupled to the device.
Footprint options (0603 size) are included to achieve the
desired input termination, biasing, and coupling to the device.
XTAL Circuit
OSCin Single-Ended Clock Input
Only one XTAL footprint (Y1 or Y2) should be used at a time.
Y1 is HC49 SMD footprint, and Y2 is 3.2 x 2.5 mm SMD footprint.
If an external single-ended clock will be used to drive OSCin, then install
C24 with 0.1 uF and remove R34 and R37 to disconnect the XTAL.
CLKin_Sel0
CLKoutA_EN
CLKin_Sel1
CLKoutB_EN
Bank A Outputs
U1_A0_P
U1_A0_N
U1_A1_P
U1_A1_N
U1_A2_P
U1_A2_N
U1_A3_P
U1_A3_N
Bank B Outputs
U1_B0_P
U1_B0_N
U1_B1_P
U1_B1_N
U1_B2_P
U1_B2_N
U1_B3_P
U1_B3_N
REFout
A2_P
A1_N
A0_N
A0_P
A3_P
A3_N
A2_N
A1_P
B0_P
B0_N
B1_P
B1_N
B2_P
B2_N
B3_P
B3_N
10µF
C4
1µF
C5
10µF
C1
1µF
C2
0.1µF
C3
0.1µF
C6
VCCO
VCC
VCCO
VCC
C1_N
C1_P
REFout_EN Single-Ended Input
By default REFout_EN is driven by SW1 or J1.
If an external single-ended signal will be used
to drive REFout_EN remove R18 and place in
R19 spot.
0.1µF
0402 6.3V
C12
0.1µF
0402 6.3V
C7
100
R24
51
R26
DNP
VCC
0.1µF
0402
6.3V
C15
DNP
0
0402
R28
51
R30
DNP
51
R21
DNP
VCC
0.1µF
0402
6.3V
C10
DNP
0
0402
R22
51
R23
DNP
0.1µF
0402 6.3V
C14
0.1µF
0402 6.3V
C17
100
R31
51
R25
DNP
51
R32
DNP
VCC
VCC
0.1µF
0402
6.3V
C13
DNP
0.1µF
0402
6.3V
C19
DNP
0
0402
R27
0
0402
R33
51
R35
DNP
51
R29
DNP
25.000 MHz
18 pF
Y1
33pF
C22
33pF
C18 0
R34
0
R37
1
2 3 4 5
OSCin
DNP
DNP
51
R40
DNP
0
0402
R41
0.1µF
0402
6.3V
C24
DNP
51
R42
OSCinSMA_OSCin
1
2 3 4 5
REFout_EN
DNP
DNP
SMA_REFout_EN
0
0402
R19
DNP
0
0402
R18
49.9
R9
DNP
U1_REFout_EN
0.01µF
C8
0.01µF
C9
0.01µF C16
0.01µF C26
0.01µF
C27
0.01µF
C20
0.01µF
C21
0
0402
R45
0
0402
R46
0
0402
R47
0
0402
R48
0
0402
R49
0
0402
R50
0
0402
R51
0
0402
R52
0
0402
R1
0
0402
R2
0
0402
R3
0
0402
R4
0
0402
R5
0
0402
R6
0
0402
R7
0
0402
R8
U1_OSCin
1
2 3 4 5
REFout
142-0701-806
U1_REFout
51
R39
DNP
0
0402
R36
10pF
C25
DNP
0.1µF
0402 6.3V
C23REFout SMA_REFout
0
R129
0
R130
DNP
0
R123
0
R124
DNP
0
R128
0
R117
0
R118
DNP
0
R122
EN_REFout
49.9
R53
DNP 49.9
R60
DNPDNP DNP DNP DNP DNP DNP
49.9
R10
DNP 49.9
R17
DNPDNP DNP DNP DNP DNP DNP
CLKOUTB3 22
CLKOUTB2 23
CLKOUTB2 24
VCC
35
CLKOUTA0 1
CLKOUTA0 2
CLKOUTA1 4
CLKOUTA1 5
VCCOA 3
CLKOUTA2 7
CLKOUTA2 8
CLKOUTA3 9
CLKOUTA3 10
CLKOUTA_EN
11
VCC
12
OSCIN
13
OSCOUT
14
GND 20
CLKIN0
16
CLKIN0
17
CLKIN_SEL1
18
CLKOUTB_EN
19
GND 31
CLKOUTB3 21
CLKIN_SEL0
15
CLKOUTB1 26
CLKOUTB1 27
CLKOUTB0 29
CLKOUTB0 30
VCC
32
CLKIN1
33
DAP 41
VCCOA 6
VCCOB 25
VCCOB 28
CLKIN1
34
REFOUT 36
VCCOC 37
REFOUT_EN
38
VCC
39
GND 40
MUX
SYNC
VccoA
VccoC
VccoB
U1
LMK00338RTA GND1 GND2 GND3
GND
REF
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Figure 3. Schematic Sheet #2
9
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LMK00338EVMProject Title:
Designed fo r: Public Release
Assembly Variant:001
© Tex as Instruments 2013
Drawn By:
Engineer:
Not shown in title block
Julian Hagedorn
Texas Instruments and/or its licensors do not warrant the accuracy or completeness of this specification or any information contained therein. Texas Instruments and/or its licensors do
not warrant that this design will meet the specifications, will be suitable for your application or fit for any particular purpose, or will operate in an implementation. Te xas Instruments and/or
its licensors do not warrant that the design is production worthy. You should completely validate and test your design implementation to confirm the system functionality for your
application.
Not in version controlSVN Rev:
SV601035Number: Rev: A
1
2 3 4 5
CLKoutA0+
1
2 3 4 5
CLKoutA0-
1
2 3 4 5
CLKoutA1+
DNP
DNP
1
2 3 4 5
CLKoutA1-
DNP
DNP
1
2 3 4 5
CLKoutA2+
DNP
DNP
1
2 3 4 5
CLKoutA2-
DNP
DNP
1
2 3 4 5
CLKoutA3+
1
2 3 4 5
CLKoutA3-
1
2 3 4 5
CLKoutB0+
1
2 3 4 5
CLKoutB0-
1
2 3 4 5
CLKoutB1+
DNP
DNP
1
2 3 4 5
CLKoutB1-
DNP
DNP
1
2 3 4 5
CLKoutB2+
DNP
DNP
1
2 3 4 5
CLKoutB2-
DNP
DNP
1
2 3 4 5
CLKoutB3+
1
2 3 4 5
CLKoutB3-
Clock Output Interface Options (Termination/Biasing/Coupling)
SMA_B0_P
SMA_B0_N
SMA_B1_P
SMA_B1_N
SMA_B2_P
SMA_B2_N
SMA_B3_P
SMA_B3_N
SMA_A0_P
SMA_A0_N
SMA_A1_P
SMA_A1_N
SMA_A2_P
SMA_A2_N
SMA_A3_P
SMA_A3_N
B0_P
A0_N
Output Bank B Output Bank A
Each output should be DC coupled and drive a 50-ohm load at the destination. The 0 ohm series
resistor near the outputs can be replaced with 10-33 ohms to reduce ringing/overshoot.
Each output should be DC coupled and drive a 50-ohm load at the destination. The 0 ohm series
resistor near the outputs can be replaced with 10-33 ohms to reduce ringing/overshoot.
A0_P
B0_N
B1_P
B1_N
A1_P
A1_N
B2_P
B2_N
B3_P
B3_N
A2_P
A2_N
A3_P
A3_N
0
R228
0
R232
0
R234
0
R238
0
R240
0
R244
0
R246
0
R250
0
R229
0
R233
0
R235
0
R239
0
R241
0
R245
0
R247
0
R251
Schematics www.ti.com
Figure 4. Schematic Sheet #3
10 LMK00338EVM User Guide SNAU155–November 2013
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www.ti.com Board Layout
10 Board Layout
Figure 5. 3D PCB Print – Top (Not to Scale)
11
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Board Layout www.ti.com
Figure 6. 3D PCB Print – Bottom (Not to Scale)
12 LMK00338EVM User Guide SNAU155–November 2013
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www.ti.com Bill of Materials
11 Bill of Materials
Table 5. LMK00338EVM Bill of Materials
Designator Description Manufacturer Part Number Quantity
!PCB Printed Circuit Board Any SV601035 1
C1, C4, C60, C64, C65, C67, CAP, CERM, 10uF, 10 V, MuRata GRM21BR61A106KE19L 8
C71, C72 ±10%, X5R, 0805
C2, C5, C61, C68 CAP, CERM, 1uF, 16 V, TDK C1608X7R1C105K 4
±10%, X7R, 0603
C3, C6 CAP, CERM, 0.1uF, 16 V, TDK C1608X7R1C104K 2
±10%, X7R, 0603
C7, C12, C14, C17, C23 CAP, CERM, 0.1uF, 6.3 V, TDK C1005X5R0J104K 5
±10%, X5R, 0402
C8, C9, C16, C20, C21, C26, CAP, CERM, 0.01uF, 16 V, TDK C1005X7R1C103K 9
C27, C62, C69 ±10%, X7R, 0402
C18, C22 CAP, CERM, 33pF, 50 V, Kemet C0603C330J5GACTU 2
±5%, C0G/NP0, 0603
C63 CAP, CERM, 470pF, 50 V, TDK C1608X7R1H471K 1
±10%, X7R, 0603
C70 CAP, CERM, 2200pF, 100 V, AVX 06031C222JAT2A 1
±5%, X7R, 0603
C73 CAP, CERM, 0.01uF, 25 V, TDK C1608C0G1E103J 1
±5%, C0G/NP0, 0603
CLKin0+, CLKin0-, Connector, SMT, End launch Emerson Network Power 142-0701-806 13
CLKoutA0+, CLKoutA0-, SMA 50 ohm
CLKoutA3+, CLKoutA3-,
CLKoutB0+, CLKoutB0-,
CLKoutB3+, CLKoutB3-,
REFout, VCC_EXT,
VCCO_EXT
D1, D2 LED, Green, SMD Lumex SML-LX2832GC-TR 2
H1, H2, H3, H4 HEX STANDOFF SPACER, Richco Plastics TCBS-6-01 4
9.53 mm
J2 Terminal Block, Weidmuller 1592820000 1
10.76x17x11 mm, 2POS,
26-12AWG, TH
R1, R2, R3, R4, R5, R6, R7, RES, 0 Ω, 5%, 0.063W, 0402 Panasonic ERJ-2GE0R00X 44
R8, R18, R22, R27, R28,
R33, R36, R41, R45, R46,
R47, R48, R49, R50, R51,
R52, R117, R122, R123,
R128, R129, R228, R229,
R232, R233, R234, R235,
R238, R239, R240, R241,
R244, R245, R246, R247,
R250, R251
R24, R31 RES, 100 Ω, 1%, 0.063 W, Vishay-Dale CRCW0402100RFKED 2
0402
R34, R37, R132, R155, R156 RES, 0 Ω, 5%, 0.1 W, Vishay-Dale CRCW06030000Z0EA 5
0603
R42 RES, 51 Ω, 5%, 0.063 W, Vishay-Dale CRCW040251R0JNED 1
B0402
R133, R154 RES, 270 Ω, 5%, 0.1W, 0603 Vishay-Dale CRCW0603270RJNEA 2
R135, R140, R141, R142, RES, 2.0k Ω, 5%, 0.1 W, Vishay-Dale CRCW06032K00JNEA 5
R143 0603
R138 RES, 118k Ω, 1%, 0.1 W, Vishay-Dale CRCW0603118KFKEA 1
0603
R139 RES, 150k Ω, 1%, 0.1 W, Vishay-Dale CRCW0603150KFKEA 1
0603
13
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Bill of Materials www.ti.com
Table 5. LMK00338EVM Bill of Materials (continued)
Designator Description Manufacturer Part Number Quantity
R157 RES, 51k Ω, 5%, 0.1 W, Vishay-Dale CRCW060351K0JNEA 1
0603
R158 RES, 2.00k Ω, 1%, 0.1 W, Vishay-Dale CRCW06032K00FKEA 1
0603
R159 RES, 866 Ω, 1%, 0.1 W, Vishay-Dale CRCW0603866RFKEA 1
0603
S1 Switch, Slide, SPST 8 poles, CTS Electrocomponents 219-8MST 1
SMT
U1 LMK00338 3-GHz 8-Output Texas Instruments LMK00338RTA 1
Differential Clock Buffer/Level
Translator, RTA0040A
U3 Micropower 800 mA Low National Semiconductor LP3878SD-ADJ 1
Noise 'Ceramic Stable'
Adjustable Voltage Regulator
for 1V to 5V Applications, 8-
pin LLP
Y1 CRYSTAL 25.000 MHZ 18PF Abracon Corporation ABLS-25.000MHZ-B4-F-T 1
SMD
14 LMK00338EVM User Guide SNAU155–November 2013
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STANDARD TERMS AND CONDITIONS FOR EVALUATION MODULES
1. Delivery: TI delivers TI evaluation boards, kits, or modules, including any accompanying demonstration software, components, or
documentation (collectively, an “EVM” or “EVMs”) to the User (“User”) in accordance with the terms and conditions set forth herein.
Acceptance of the EVM is expressly subject to the following terms and conditions.
1.1 EVMs are intended solely for product or software developers for use in a research and development setting to facilitate feasibility
evaluation, experimentation, or scientific analysis of TI semiconductors products. EVMs have no direct function and are not
finished products. EVMs shall not be directly or indirectly assembled as a part or subassembly in any finished product. For
clarification, any software or software tools provided with the EVM (“Software”) shall not be subject to the terms and conditions
set forth herein but rather shall be subject to the applicable terms and conditions that accompany such Software
1.2 EVMs are not intended for consumer or household use. EVMs may not be sold, sublicensed, leased, rented, loaned, assigned,
or otherwise distributed for commercial purposes by Users, in whole or in part, or used in any finished product or production
system.
2Limited Warranty and Related Remedies/Disclaimers:
2.1 These terms and conditions do not apply to Software. The warranty, if any, for Software is covered in the applicable Software
License Agreement.
2.2 TI warrants that the TI EVM will conform to TI's published specifications for ninety (90) days after the date TI delivers such EVM
to User. Notwithstanding the foregoing, TI shall not be liable for any defects that are caused by neglect, misuse or mistreatment
by an entity other than TI, including improper installation or testing, or for any EVMs that have been altered or modified in any
way by an entity other than TI. Moreover, TI shall not be liable for any defects that result from User's design, specifications or
instructions for such EVMs. Testing and other quality control techniques are used to the extent TI deems necessary or as
mandated by government requirements. TI does not test all parameters of each EVM.
2.3 If any EVM fails to conform to the warranty set forth above, TI's sole liability shall be at its option to repair or replace such EVM,
or credit User's account for such EVM. TI's liability under this warranty shall be limited to EVMs that are returned during the
warranty period to the address designated by TI and that are determined by TI not to conform to such warranty. If TI elects to
repair or replace such EVM, TI shall have a reasonable time to repair such EVM or provide replacements. Repaired EVMs shall
be warranted for the remainder of the original warranty period. Replaced EVMs shall be warranted for a new full ninety (90) day
warranty period.
3Regulatory Notices:
3.1 United States
3.1.1 Notice applicable to EVMs not FCC-Approved:
This kit is designed to allow product developers to evaluate electronic components, circuitry, or software associated with the kit
to determine whether to incorporate such items in a finished product and software developers to write software applications for
use with the end product. This kit is not a finished product and when assembled may not be resold or otherwise marketed unless
all required FCC equipment authorizations are first obtained. Operation is subject to the condition that this product not cause
harmful interference to licensed radio stations and that this product accept harmful interference. Unless the assembled kit is
designed to operate under part 15, part 18 or part 95 of this chapter, the operator of the kit must operate under the authority of
an FCC license holder or must secure an experimental authorization under part 5 of this chapter.
3.1.2 For EVMs annotated as FCC – FEDERAL COMMUNICATIONS COMMISSION Part 15 Compliant:
CAUTION
This device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not
cause harmful interference, and (2) this device must accept any interference received, including interference that may cause
undesired operation.
Changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to
operate the equipment.
FCC Interference Statement for Class A EVM devices
NOTE: This equipment has been tested and found to comply with the limits for a Class A digital device, pursuant to part 15 of
the FCC Rules. These limits are designed to provide reasonable protection against harmful interference when the equipment is
operated in a commercial environment. This equipment generates, uses, and can radiate radio frequency energy and, if not
installed and used in accordance with the instruction manual, may cause harmful interference to radio communications.
Operation of this equipment in a residential area is likely to cause harmful interference in which case the user will be required to
correct the interference at his own expense.
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FCC Interference Statement for Class B EVM devices
NOTE: This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 of
the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential
installation. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordance
with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference
will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which
can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more
of the following measures:
•Reorient or relocate the receiving antenna.
•Increase the separation between the equipment and receiver.
•Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.
•Consult the dealer or an experienced radio/TV technician for help.
3.2 Canada
3.2.1 For EVMs issued with an Industry Canada Certificate of Conformance to RSS-210
Concerning EVMs Including Radio Transmitters:
This device complies with Industry Canada license-exempt RSS standard(s). Operation is subject to the following two conditions:
(1) this device may not cause interference, and (2) this device must accept any interference, including interference that may
cause undesired operation of the device.
Concernant les EVMs avec appareils radio:
Le présent appareil est conforme aux CNR d'Industrie Canada applicables aux appareils radio exempts de licence. L'exploitation
est autorisée aux deux conditions suivantes: (1) l'appareil ne doit pas produire de brouillage, et (2) l'utilisateur de l'appareil doit
accepter tout brouillage radioélectrique subi, même si le brouillage est susceptible d'en compromettre le fonctionnement.
Concerning EVMs Including Detachable Antennas:
Under Industry Canada regulations, this radio transmitter may only operate using an antenna of a type and maximum (or lesser)
gain approved for the transmitter by Industry Canada. To reduce potential radio interference to other users, the antenna type
and its gain should be so chosen that the equivalent isotropically radiated power (e.i.r.p.) is not more than that necessary for
successful communication. This radio transmitter has been approved by Industry Canada to operate with the antenna types
listed in the user guide with the maximum permissible gain and required antenna impedance for each antenna type indicated.
Antenna types not included in this list, having a gain greater than the maximum gain indicated for that type, are strictly prohibited
for use with this device.
Concernant les EVMs avec antennes détachables
Conformément à la réglementation d'Industrie Canada, le présent émetteur radio peut fonctionner avec une antenne d'un type et
d'un gain maximal (ou inférieur) approuvé pour l'émetteur par Industrie Canada. Dans le but de réduire les risques de brouillage
radioélectrique à l'intention des autres utilisateurs, il faut choisir le type d'antenne et son gain de sorte que la puissance isotrope
rayonnée équivalente (p.i.r.e.) ne dépasse pas l'intensité nécessaire à l'établissement d'une communication satisfaisante. Le
présent émetteur radio a été approuvé par Industrie Canada pour fonctionner avec les types d'antenne énumérés dans le
manuel d’usage et ayant un gain admissible maximal et l'impédance requise pour chaque type d'antenne. Les types d'antenne
non inclus dans cette liste, ou dont le gain est supérieur au gain maximal indiqué, sont strictement interdits pour l'exploitation de
l'émetteur
3.3 Japan
3.3.1 Notice for EVMs delivered in Japan: Please see http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_01.page 日本国内に
輸入される評価用キット、ボードについては、次のところをご覧ください。
http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_01.page
3.3.2 Notice for Users of EVMs Considered “Radio Frequency Products” in Japan: EVMs entering Japan may not be certified
by TI as conforming to Technical Regulations of Radio Law of Japan.
If User uses EVMs in Japan, not certified to Technical Regulations of Radio Law of Japan, User is required by Radio Law of
Japan to follow the instructions below with respect to EVMs:
1. Use EVMs in a shielded room or any other test facility as defined in the notification #173 issued by Ministry of Internal
Affairs and Communications on March 28, 2006, based on Sub-section 1.1 of Article 6 of the Ministry’s Rule for
Enforcement of Radio Law of Japan,
2. Use EVMs only after User obtains the license of Test Radio Station as provided in Radio Law of Japan with respect to
EVMs, or
3. Use of EVMs only after User obtains the Technical Regulations Conformity Certification as provided in Radio Law of Japan
with respect to EVMs. Also, do not transfer EVMs, unless User gives the same notice above to the transferee. Please note
that if User does not follow the instructions above, User will be subject to penalties of Radio Law of Japan.
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【無線電波を送信する製品の開発キットをお使いになる際の注意事項】 開発キットの中には技術基準適合証明を受けて
いないものがあります。 技術適合証明を受けていないもののご使用に際しては、電波法遵守のため、以下のいずれかの
措置を取っていただく必要がありますのでご注意ください。
1. 電波法施行規則第6条第1項第1号に基づく平成18年3月28日総務省告示第173号で定められた電波暗室等の試験設備でご使用
いただく。
2. 実験局の免許を取得後ご使用いただく。
3. 技術基準適合証明を取得後ご使用いただく。
なお、本製品は、上記の「ご使用にあたっての注意」を譲渡先、移転先に通知しない限り、譲渡、移転できないものとします。
上記を遵守頂けない場合は、電波法の罰則が適用される可能性があることをご留意ください。 日本テキサス・イ
ンスツルメンツ株式会社
東京都新宿区西新宿６丁目２４番１号
西新宿三井ビル
3.3.3 Notice for EVMs for Power Line Communication: Please see http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_02.page
電力線搬送波通信についての開発キットをお使いになる際の注意事項については、次のところをご覧くださ
い。http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_02.page
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4EVM Use Restrictions and Warnings:
4.1 EVMS ARE NOT FOR USE IN FUNCTIONAL SAFETY AND/OR SAFETY CRITICAL EVALUATIONS, INCLUDING BUT NOT
LIMITED TO EVALUATIONS OF LIFE SUPPORT APPLICATIONS.
4.2 User must read and apply the user guide and other available documentation provided by TI regarding the EVM prior to handling
or using the EVM, including without limitation any warning or restriction notices. The notices contain important safety information
related to, for example, temperatures and voltages.
4.3 Safety-Related Warnings and Restrictions:
4.3.1 User shall operate the EVM within TI’s recommended specifications and environmental considerations stated in the user
guide, other available documentation provided by TI, and any other applicable requirements and employ reasonable and
customary safeguards. Exceeding the specified performance ratings and specifications (including but not limited to input
and output voltage, current, power, and environmental ranges) for the EVM may cause personal injury or death, or
property damage. If there are questions concerning performance ratings and specifications, User should contact a TI
field representative prior to connecting interface electronics including input power and intended loads. Any loads applied
outside of the specified output range may also result in unintended and/or inaccurate operation and/or possible
permanent damage to the EVM and/or interface electronics. Please consult the EVM user guide prior to connecting any
load to the EVM output. If there is uncertainty as to the load specification, please contact a TI field representative.
During normal operation, even with the inputs and outputs kept within the specified allowable ranges, some circuit
components may have elevated case temperatures. These components include but are not limited to linear regulators,
switching transistors, pass transistors, current sense resistors, and heat sinks, which can be identified using the
information in the associated documentation. When working with the EVM, please be aware that the EVM may become
very warm.
4.3.2 EVMs are intended solely for use by technically qualified, professional electronics experts who are familiar with the
dangers and application risks associated with handling electrical mechanical components, systems, and subsystems.
User assumes all responsibility and liability for proper and safe handling and use of the EVM by User or its employees,
affiliates, contractors or designees. User assumes all responsibility and liability to ensure that any interfaces (electronic
and/or mechanical) between the EVM and any human body are designed with suitable isolation and means to safely
limit accessible leakage currents to minimize the risk of electrical shock hazard. User assumes all responsibility and
liability for any improper or unsafe handling or use of the EVM by User or its employees, affiliates, contractors or
designees.
4.4 User assumes all responsibility and liability to determine whether the EVM is subject to any applicable international, federal,
state, or local laws and regulations related to User’s handling and use of the EVM and, if applicable, User assumes all
responsibility and liability for compliance in all respects with such laws and regulations. User assumes all responsibility and
liability for proper disposal and recycling of the EVM consistent with all applicable international, federal, state, and local
requirements.
5. Accuracy of Information: To the extent TI provides information on the availability and function of EVMs, TI attempts to be as accurate
as possible. However, TI does not warrant the accuracy of EVM descriptions, EVM availability or other information on its websites as
accurate, complete, reliable, current, or error-free.
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6. Disclaimers:
6.1 EXCEPT AS SET FORTH ABOVE, EVMS AND ANY WRITTEN DESIGN MATERIALS PROVIDED WITH THE EVM (AND THE
DESIGN OF THE EVM ITSELF) ARE PROVIDED "AS IS" AND "WITH ALL FAULTS." TI DISCLAIMS ALL OTHER
WARRANTIES, EXPRESS OR IMPLIED, REGARDING SUCH ITEMS, INCLUDING BUT NOT LIMITED TO ANY IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF ANY
THIRD PARTY PATENTS, COPYRIGHTS, TRADE SECRETS OR OTHER INTELLECTUAL PROPERTY RIGHTS.
6.2 EXCEPT FOR THE LIMITED RIGHT TO USE THE EVM SET FORTH HEREIN, NOTHING IN THESE TERMS AND
CONDITIONS SHALL BE CONSTRUED AS GRANTING OR CONFERRING ANY RIGHTS BY LICENSE, PATENT, OR ANY
OTHER INDUSTRIAL OR INTELLECTUAL PROPERTY RIGHT OF TI, ITS SUPPLIERS/LICENSORS OR ANY OTHER THIRD
PARTY, TO USE THE EVM IN ANY FINISHED END-USER OR READY-TO-USE FINAL PRODUCT, OR FOR ANY
INVENTION, DISCOVERY OR IMPROVEMENT MADE, CONCEIVED OR ACQUIRED PRIOR TO OR AFTER DELIVERY OF
THE EVM.
7. USER'S INDEMNITY OBLIGATIONS AND REPRESENTATIONS. USER WILL DEFEND, INDEMNIFY AND HOLD TI, ITS
LICENSORS AND THEIR REPRESENTATIVES HARMLESS FROM AND AGAINST ANY AND ALL CLAIMS, DAMAGES, LOSSES,
EXPENSES, COSTS AND LIABILITIES (COLLECTIVELY, "CLAIMS") ARISING OUT OF OR IN CONNECTION WITH ANY
HANDLING OR USE OF THE EVM THAT IS NOT IN ACCORDANCE WITH THESE TERMS AND CONDITIONS. THIS OBLIGATION
SHALL APPLY WHETHER CLAIMS ARISE UNDER STATUTE, REGULATION, OR THE LAW OF TORT, CONTRACT OR ANY
OTHER LEGAL THEORY, AND EVEN IF THE EVM FAILS TO PERFORM AS DESCRIBED OR EXPECTED.
8. Limitations on Damages and Liability:
8.1 General Limitations. IN NO EVENT SHALL TI BE LIABLE FOR ANY SPECIAL, COLLATERAL, INDIRECT, PUNITIVE,
INCIDENTAL, CONSEQUENTIAL, OR EXEMPLARY DAMAGES IN CONNECTION WITH OR ARISING OUT OF THESE
TERMS ANDCONDITIONS OR THE USE OF THE EVMS PROVIDED HEREUNDER, REGARDLESS OF WHETHER TI HAS
BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. EXCLUDED DAMAGES INCLUDE, BUT ARE NOT LIMITED
TO, COST OF REMOVAL OR REINSTALLATION, ANCILLARY COSTS TO THE PROCUREMENT OF SUBSTITUTE GOODS
OR SERVICES, RETESTING, OUTSIDE COMPUTER TIME, LABOR COSTS, LOSS OF GOODWILL, LOSS OF PROFITS,
LOSS OF SAVINGS, LOSS OF USE, LOSS OF DATA, OR BUSINESS INTERRUPTION. NO CLAIM, SUIT OR ACTION SHALL
BE BROUGHT AGAINST TI MORE THAN ONE YEAR AFTER THE RELATED CAUSE OF ACTION HAS OCCURRED.
8.2 Specific Limitations. IN NO EVENT SHALL TI'S AGGREGATE LIABILITY FROM ANY WARRANTY OR OTHER OBLIGATION
ARISING OUT OF OR IN CONNECTION WITH THESE TERMS AND CONDITIONS, OR ANY USE OF ANY TI EVM
PROVIDED HEREUNDER, EXCEED THE TOTAL AMOUNT PAID TO TI FOR THE PARTICULAR UNITS SOLD UNDER
THESE TERMS AND CONDITIONS WITH RESPECT TO WHICH LOSSES OR DAMAGES ARE CLAIMED. THE EXISTENCE
OF MORE THAN ONE CLAIM AGAINST THE PARTICULAR UNITS SOLD TO USER UNDER THESE TERMS AND
CONDITIONS SHALL NOT ENLARGE OR EXTEND THIS LIMIT.
9. Return Policy. Except as otherwise provided, TI does not offer any refunds, returns, or exchanges. Furthermore, no return of EVM(s)
will be accepted if the package has been opened and no return of the EVM(s) will be accepted if they are damaged or otherwise not in
a resalable condition. If User feels it has been incorrectly charged for the EVM(s) it ordered or that delivery violates the applicable
order, User should contact TI. All refunds will be made in full within thirty (30) working days from the return of the components(s),
excluding any postage or packaging costs.
10. Governing Law: These terms and conditions shall be governed by and interpreted in accordance with the laws of the State of Texas,
without reference to conflict-of-laws principles. User agrees that non-exclusive jurisdiction for any dispute arising out of or relating to
these terms and conditions lies within courts located in the State of Texas and consents to venue in Dallas County, Texas.
Notwithstanding the foregoing, any judgment may be enforced in any United States or foreign court, and TI may seek injunctive relief
in any United States or foreign court.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2015, Texas Instruments Incorporated
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Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
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issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale
supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
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TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
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