Texas Instruments TPS7H5001-SP User manual

User’s Guide
TPS7H5001-SP Evaluation Module
ABSTRACT
This user's guide describes the characteristics, operation, and use of the TPS7H5001-SP Evaluation Module
(EVM). Setup to ensure proper operation of the device as well as a complete schematic diagram, printed-circuit
board layouts, and bill of materials are included in this document. Basic waveforms of operation are also shown.
Table of Contents
1 Introduction.............................................................................................................................................................................2
1.1 Features............................................................................................................................................................................. 2
1.2 Applications........................................................................................................................................................................2
2 EVM Setup and Quick Start Guide........................................................................................................................................ 3
3 EVM Connectors and Test Points..........................................................................................................................................5
4 PCB Layouts............................................................................................................................................................................7
5 Schematics..............................................................................................................................................................................9
6 Bill of Materials..................................................................................................................................................................... 12
List of Figures
Figure 2-1. Positive and Negative Terminal for J11..................................................................................................................... 3
Figure 2-2. TPS7H5001-SP Output............................................................................................................................................. 4
Figure 2-3. Duty Cycle Generation.............................................................................................................................................. 4
Figure 4-1. Top Overlay............................................................................................................................................................... 7
Figure 4-2. Top Solder................................................................................................................................................................. 7
Figure 4-3. Top Layer...................................................................................................................................................................7
Figure 4-4. Bottom Layer............................................................................................................................................................. 7
Figure 4-5. Bottom Solder............................................................................................................................................................8
Figure 4-6. Bottom Overlay..........................................................................................................................................................8
Figure 4-7. Drill Drawing.............................................................................................................................................................. 8
Figure 4-8. Board Dimensions..................................................................................................................................................... 8
Figure 5-1. TPS7H5001-SP Schematic (Page 1)........................................................................................................................ 9
Figure 5-2. TPS7H5001-SP Schematic (Page 2)...................................................................................................................... 10
Figure 5-3. TPS7H5001-SP Schematic (Page 3).......................................................................................................................11
List of Tables
Table 2-1. Default EVM Configuration......................................................................................................................................... 3
Table 2-2. TPS7H5001-SP Connections..................................................................................................................................... 3
Table 3-1. EVM Board Connections.............................................................................................................................................5
Table 3-2. J6 Connections and Configuration..............................................................................................................................6
Table 6-1. TPS7H5001-SP Bill of Materials............................................................................................................................... 12
Trademarks
All trademarks are the property of their respective owners.
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1 Introduction
This board enables the TPS7H5001-SP to be connected to other components needed to quickly prototype and
evaluate a complete power converter design. The TPS7H5001-SP is placed on an open test board similar
to the board used in the TPS7H5001-SP Lookahead Total Ionizing Dose (TID) Radiation Report. Adding test
points and voltage terminals is the only major change to the design that was needed to facilitate probing
the TPS7H5001-SP without additional hardware. Minor changes were made to the BOM for manufacturability
purposes.
1.1 Features
This EVM has the following features:
• Synchronous rectification outputs with adjustable dead time
• 0.613-V ±1% Voltage reference overtemperature, radiation, and line and load
• Adjustable slope compensation and soft start
• Configurable duty cycle limit
1.2 Applications
• Space satellite isolated power supplies
• Radiation hardened applications
• Space satellite payloads
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2 EVM Setup and Quick Start Guide
Default EVM Configuration lists the default configuration.
Table 2-1. Default EVM Configuration
Parameter Specification
Input Power Supply 4 V to 14V
Operating Temperature 25°C
Switching Frequency 500 kHz
The TPS7H5001-SP can be quickly turned on and run using the connections shown in TPS7H5001-SP
Connections.
Table 2-2. TPS7H5001-SP Connections
Terminal or Test Point Voltage Source
J11 (VIN) 4 to 14 V input at 10 mA, See Positive and Negative Terminal for J11 for
connections
TP9 (COMP) 1 V at < 10 mA (Input range can be –0.3 V to 3.3 V based on the
TPS7H5001-SP Radiation-Hardness-Assured Si and GaN Dual Output
Controller data sheet)
Positive and Negative Terminal for J11 shows which terminal is the positive and negative on J11. Connect the
positive input voltage to the positive terminal and GND to negative terminal.
Figure 2-1. Positive and Negative Terminal for J11
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The device should then turn on and operate in open loop mode as shown in TPS7H5001-SP Output.
TPS7H50011-SP Output shows the output of TPS7H5001-SP measured on J1–J4 with the quick start method.
Figure 2-2. TPS7H5001-SP Output
The operation of this mode is such that forcing the voltage on COMP will create an output on the TPS7H5001-
SP. The duty cycle varies based on the input voltage on COMP as well as the triangle waveform created by
the CS_LIM circuit, or any other waveform that the user decides to add to the CS_LIM pin. See Duty Cycle
Generation for signal generation waveforms.
Duty Cycle Generation shows waveforms for input and output signal generations for the TPS7H5001-SP based
on COMP voltage and CS_LIM pin voltage.
Figure 2-3. Duty Cycle Generation
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3 EVM Connectors and Test Points
Table 3-1 is a list of major connections on the board. For further information see the relevant section in the
TPS7H5001-SP Radiation-Hardness-Assured Si and GaN Dual Output Controller data sheet.
Table 3-1. EVM Board Connections
Test Point Connection Description
TP1, J1 OUTA Connected to the gate driver in the design. Components R5, C5 can be
used to test different R/C loads.
TP2, J2 OUTB Connected to the gate driver in the design. Components R6, C6 can be
used to test different R/C loads.
TP3, J3 SRA Connected to the gate driver in the design. Components R7, C7 can be
used to test different R/C loads.
TP4, J4 SRB Connected to the gate driver in the design. Components R8, C8 can be
used to test different R/C loads.
TP5, TP6 CS_LIM Input for current sense in the design. The CS_LIM circuit provides small
triangle waveform from OUTA, OUTB. Note that this can load OUTA,
OUTB causing a slow in the slew rate. If R9 and R10 are unpopulated,
CS_LIM can be force from TP5.
TP7 VIN Voltage input for the TPS7H5001-SP device
TP8 EN Enable pin for the TPS7H5001-SP device, currently pulled high to VLDO
TP9 COMP Error amplifier output for the TPS7H5001-SP, forcing this voltage runs the
TPS7H5001-SP in open loop.
TP10 REFCAP Internal reference for TPS7H5001-SP
TP11, TP12 SS In a closed loop design, this slowly increases converter output voltage
during start-up
TP13, TP15 SYNC Inputting a clock on this pin synchronizes the TPS7H5001-SP to a
frequency half of the input frequency
TP14 VLDO Internal voltage rail for device logic
TP20 VSENSE Voltage sense for the TPS7H5001-SP. Connected to converter output
voltage in the full design.
TP21 RSC Slope compensation selection resistor. Sets slope compensation slew rate
internal to the device.
TP22 HICC Configurability for the hiccup time of the converter. While grounded
through a resistor on the EVM, in a full design it is generally a capacitor.
TP23 FAULT A signal high on this node turns the TPS7H5001-SP off for any fault
condition needed
TP24 SP Configurability for the delay between the synchronous rectifiers and main
output
TP25 RT Frequency select for the TPS7H5001-SP. Change this to vary the
frequency of the converter.
TP26 PS Configurability for the delay between the main output and synchronous
rectifiers
TP27 LEB Configurability for the leading edge blanking time of the converter
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Table 3-2 describes and lists the connections and configuration for J6. Use J6 to switch between different DCL
connections to test different duty cycle limits. Pin 1 is noted by the dot next to the pin.
Table 3-2. J6 Connections and Configuration
Pin Connection Duty Cycle Limit Configuration Description
Pin 1 and Pin 2 100% DCL is connected high to VLDO
Pin 2 and Pin 3 50% DCL is connected low to AVSS
Floating 75% DCL is left floating
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4 PCB Layouts
Top Overlay through Board Dimensions show the EVM PCB layout images.
Figure 4-1. Top Overlay
Figure 4-2. Top Solder
Figure 4-3. Top Layer Figure 4-4. Bottom Layer
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Figure 4-5. Bottom Solder Figure 4-6. Bottom Overlay
Figure 4-7. Drill Drawing
Figure 4-8. Board Dimensions
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5 Schematics
Figure 5-1 through Figure 5-3 show the EVM schematics.
VIN
9
COMP 22
CS_ILIM
16
DCL 7
EN
8
FAULT
17
HICC
5
LEB
4
OUTA 10
OUTB 11
PS
2
REFCAP
18
RSC
19
RT
1
SP
3
SRA 13
SRB 12
SS 20
SYNC
6VLDO 15
VSENSE 21
AVSS 14
EP 23
TPS7H5001HKY-EM
U1
AGND AGND
SYNC
SYNC
TP13
AGND
VLDO TP14
AGND
135k
R31
AGND
1.00k
R14
10.0
R24
10.0
R26
20.0k
R15
49.9k
R39
1.00M
R35
30.0k
R40
49.9k
R30
49.9k
R29
10.0k
R9
10.0k
R10
4.70k
R41
5.90k
R27
3.90k
R25
470nF
C15
500pF
C10
20pF
C5
20pF
C17
1µF
C18
10nF
C16
191k
R33
VIN
VIN
TP7
VLDO
VIN
VLDO
0
R12
0
R11
DNP
PXIe-4145 (CH#0) F+
PXIe-4145 (CH#0) S+
PXIe-4145 (CH#0) S-
0
R16
DNP
AGND
AGND
AGND AGND
50V
1µF
C14
DNP
0
R4
PXIe-4112 (CH#1)
PXIe-4112 (CH#1) S+
PXIe-4112 (CH#1) S-
0
R1
100nF
25V
C9
REFCAP
REFCAP
REFCAP
TP10
OUTA OUTB
CS_ILIM
CS_ILIM
CS_ILIM
TP5
G
TP6
AGND
G
TP15 PXIe-4145 (CH#1) F+
PXIe-4145 (CH#1) S+
PXIe-4145 (CH#1) S-
0
R34
DNP
0
R37
DNP
100nF
25V
C19
DNP
SS
TP11
1
2
I_VIN
J5
IVIN_P
IVIN_N
150uF
C1
AGND
0.1uF
C4
10uF
C3
10uF
C2
G
TP12
AGND
VLDO
0
R19
DNP
0
R22
DNP
1.00M
R5
DNP
AGND
OUTA OUTB
OUTA
OUTB
20pF
C6
1.00M
R6
DNP
AGND
20pF
C7
1.00M
R7
DNP
AGND
SRA SRB
20pF
C8
1.00M
R8
DNP
AGND
SRA
SRB
AGND_SENSE
AGND_SENSE
1
2
3 4 5
J1
AGND
OUTA 1
2
3 4 5
J2
AGND
OUTB 1
2
3 4 5
J3
AGND
1
2
3 4 5
J4
AGND
SRA SRB
OUTA
TP1
EN
TP8
SRA
TP3
OUTB
TP2
SRB
TP4
20pF
C5
1.00M
R5
DDNNNNNNP
1.00M1.00M
R5R5
AGND
OUTA OUTB
20pF
C6
1.00M
R6
DDNNNNNNNP
1.00M1.00M
R6R6
AGND
20pF
C7
1.00M
R7
DDNNNNNNNP
1.00M1.00M
R7R7
AGND
SRA SRB
20pF
C8
1.00M
R8
DDNNNNNNNP
1.00M1.00M
R8R8
AGND
1
2
3 4 5
J1
AGND
OUTA 1
2
3 4 5
J2
AGND
OUTB 1
2
3 4 5
J3
AGND
1
2
3 4 5
J4
AGND
SRA SRB
OUTA
TP1
SRA
TP3
OUTB
TP2
SRB
TP4
PWM's Output and Loading
470nF
C15
AGND
50V
1µF
C14
DDDDDNNNNNNNPPP
REFCAP
REFCAP
TP10
REFCAP
AGND
20.0k
R15
10.0k
R9
10.0k
R10
500pF
C10
OUTA OUTB
CS_ILIM
CS_ILIM
TP5
GG
TP6
CS_ILIM
0
R44
0
R13
0
R17
0
R18
0
R20
COMP
TP9
E36311A-1 (+6V)
10nF
C12 DNP
1000pF
C11 DNP
10.0k
R21
DNP
0
R28
DNP
0
R42
0
R38
DIO_6B
DIO_7B
COMP
EN
HICC
FAULT
SP
PS
RT
SYNC
LEB
RSC DCL
VSENSE
SS
PXIe-4113 (CH#1) S+ 0
R3
FAULT
0
R2
PXIe-4113 (CPXPX H#1) S+HH 0
R3
FAULT
0
R2
FAULT
PXIe-4113 (CH#1) S- 0
R43
VSENSE
COMP
1.0k
R36
470nF
C13
DNP
HICC
AGND
1
2
3
J6
AGND
DCL
0
R32
VLDO
PXIe-4137 S-
PXIe-4137 S+
PXIe-4137 F+ DCL
470nF
C13
DDDDDNNNNNNPPP
HICC
AGND
HICC
0
R23
DNP
0
R45
R47
0
R46
PXIe-4113 (CH#1) F+
0
R118
1
2
J11
ED120/2DS
TP28
AGND
TP29TP30TP31
Figure 5-1. TPS7H5001-SP Schematic (Page 1)
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PXIe-5162_CH0
PXIe-5162_CH1
PXIe-5162_CH2
PXIe-5162_CH3
OUTA
OUTB
SRA
SRB
0
R48
VLDO
REFCAP
VIN
EN
HICC
FAULT
SP
RT
PS
SYNC
LEB
RSC
VLDO
COMP_BUFFER
VSENSE
SS_BUFFER
0
R60
0
R75
0
R54
0
R68
0
R78
0
R81
0
R84
0
R49
0
R55
0
R61
0
R69
0
R76
0
R79
0
R82
0
R85
0
R74
0
R77
0
R80
0
R83
PXIe-5110_CH0
PXIe-5110_CH1
0
R53
OUTA
SRA 0
R52
DNP
0
R59
OUTB
SRB 0
R58
DNP
DMM_Site1_1
DMM_Site1_2
DMM_Site1_3
AWG_CH1_to_SIte1
PXIe-5172-1_CH1_Site1
PXIe-5172-1_CH3_Site1
PXIe-5172-1_CH5_Site1
PXIe-5172-1_CH7_Site1
PXIe-5172-2_CH1_Site1
PXIe-5172-2_CH3_Site1
PXIe-5172-2_CH5_Site1
PXIe-5172-2_CH7_Site1
DMM_Site1_4
DMM_Site1_5
AWG_CH2_to_SIte1
PXIe-5172-1_CH0_Site1
PXIe-5172-1_CH2_Site1
PXIe-5172-1_CH4_Site1
PXIe-5172-1_CH6_Site1
PXIe-5172-2_CH0_Site1
PXIe-5172-2_CH2_Site1
PXIe-5172-2_CH4_Site1
PXIe-5172-2_CH6_Site1
1
2
3
4
5
OPA354AIDBVR
U5
100nF
25V
C26
DNP
0
R96
0
R86
0
R94
0
R97
DNP
4
1
2
SN74AHCT1G08DCKR
U2A
VCC
5GND 3
SN74AHCT1G08DCKR
U3B
4
1
2
SN74AHCT1G08DCKR
U3A
VCC
5GND 3
SN74AHCT1G08DCKR
U2B
AGND
AGND
AGND AGND
OUTA
SRA
OUTB
SRB
PXIe-5162_CH0
PXIe-5162_CH1
0
R63
0
R70
PXIe-5162_CH0
PXIe-5162_CH1
4
1
2
SN74AHCT1G08DCKR
U2AUU
VCC
5GND 3
SN74AHCT1G08DCKR
U3B
4
1
2
SN74AHCT1G08DCKR
U3A
VCC
5GND 3
SN74AHCT1G08DCKR
U2BUU
AGND
AGND
AGND AGND
OUTATT
SRARR
OUTB
SRB
0
R63
0
R70
PXIe-5162_CH0
PXIe-5162_CH1
Cross Conduction Trigger
In Case Cross Conduction inA, we send trigger to C H1 and we capture OUTA-CH0 and SRA-CH2
In Case Cross Conduction in B, we send trigger to C H0 and we capture OUTB-CH1 and SRB-CH3
COMP COMP_BUFFER
AGND
AGND
1
2
3
4
5
OPA35AA 4AIDBVR
U5
100nF
25V
C26
DDDDDNNNNNPPPPP
0
R96
0
R86
0
R94
0
R97
DDDDDDNNNNNNPPPPP
COMP COMP_BUFFER
AGND
AGND
COMP Buffer
Do we Need a HS Comparator to Adjust VIH??
PXIe-5110_CH0
PXIe-5110_CH1
0
R53
OUTATT
SRARR 0
R52
DDDDDDNNNNPPPP
0
R59
OUTB
SRB 0
R58
DDDDDDNNNNPPPP
PXIe-5110 (PWM Trigger Supported)
PXIe-5162_CH0
PXIe-5162_CH1
PXIe-5162_CH2
PXIe-5162_CH3
OUTATT
OUTB
SRARR
SRB
0
R74
0
R77
0
R80
0
R83
PXIe-5162_CH0
PXIe-5162_CH1
PXIe-5162 (HS Scope) or DPO7XXXX Series
0
R48
VLDO
REFCAP
VIN
EN
RSC
COMP_BUFFER
VSENSE
SS_BUFFER
0
R60
0
R75
0
R54
0
R68
0
R78
0
R81
0
R84
PXIe-5172-1_CH1_Site1
PXIe-5172-1_CH3_Site1
PXIe-5172-1_CH5_Site1
PXIe-5172-1_CH7_Site1
PXIe-5172-1_CH0_Site1
PXIe-5172-1_CH2_Site1
PXIe-5172-1_CH4_Site1
PXIe-5172-1_CH6_Site1
PXIe-5172 (General Purpose Up to 100MHz)
HICC
FAULT
SP
RT
PS
SYNC
LEB
VLDO 0
R49
0
R55
0
R61
0
R69
0
R76
0
R79
0
R82
0
R85
PXIe-5172-2_CH1_Site1
PXIe-5172-2_CH3_Site1
PXIe-5172-2_CH5_Site1
PXIe-5172-2_CH7_Site1
PXIe-5172-2_CH0_Site1
PXIe-5172-2_CH2_Site1
PXIe-5172-2_CH4_Site1
PXIe-5172-2_CH6_Site1
PXIe-5172 (General Purpose Up to 100MHz)
0
R57
DNP
OUTA
SRA 0
R51
DNP
0
R73
DNP
OUTB
SRB 0
R65
DNP
OUTA
OUTB
SRA
SRB
0
R50
DNP
0
R56
DNP
0
R64
DNP
0
R72
DNP
SYNC 0
R89
CS_ILIM 0
R92
AWAA G_CH1_to__ SIte1
AWAA G_CH2_to__ SIte1
SYNC 0
R89
CS_ILIM 0
R92
External CLK Syncronization
0
R87
0
R88
0
R90
0
R91
0
R93
VLDO
REFCAP
VIN
COMP_BUFFER
DMM_Site1_1
DMM_Site1_2
DMM_Site1_3
DMM_Site1_4
DMM_Site1_5
0
R87
0
R88
0
R90
0
R91
0
R93
VLDO
REFCAP
VIN
COMP_BUFFER
DMM
PXIe-5922_CH0_Site1
PXIe-5922_CH1_Site1
1
2
3
4
5
OPA354AIDBVR
U6
100nF
25V
C34
DNP
0
R106
0
R104
0
R105
0
R107
DNP
SS SS_BUFFER
AGND
AGND
1
2
3
4
5
OPA35AA 4AIDBVR
U6
100nF
25V
C34
DDDDDDNNNNNNNNPPPPP
0
R106
0
R104
0
R105
0
R107
DDDDDDNNNNNNPPPPP
SS SS_BUFFER
AGND
AGND
SS Buffer
SS_BUFFER
0
R102
0
R99
COMP_B_IN TP17 COMP_B_OUT
TP16
100nF
25V
C20
1µF
50V
C21
1nF
50V
C22
1µF
50V
C24
1nF
50V
C25
100nF
25V
C23
1µF
50V
C28
1nF
50V
C29
100nF
25V
C27
1µF
50V
C36
1nF
50V
C37
100nF
25V
C35
100nF
25V
C39
DNP
AGND
100nF
25V
C38
DNP
100nF
25V
C32
DNP
100nF
25V
C33
DNP
AGND
SS_B_IN TP19 SS_B_OUT
TP18
SS_BUFFER
COMP_BUFFER
PXIe-5922_CH0_Site1
PXIe-5922_CH1_Site1
0
R102
0
R99
SS_BUFFER
COMP_BUFFER
PXIe-5922 (High Presicion)
0
R62
0
R66
0
R67
0
R71
1 3
2
GND
10
R100
Heater
AGND
PXIe-4139-1 F+
PXIe-4139-1 S+
0
R103
0
R101
PXIe-4139-1 S-
0
R98
1 3
2
GND
10
R100
Heater
AGND
PXIe-4139-1 F+
PXPP Ie-4XX 139-1 S+
0
R103
0
R101
PXPP Ie-4XX 139-1 S-
0
R98
IN
3OUT 2
1
TAB 4
GND
LM1117MPX-5.0
U4
E36311A-1 (+25V)
AGND
10V
47uF
C31
AGND
+5V
+5V
+5V
+5V
0
R95
E36311A-1 (+25V) +5V
IN
3OUT 2
1
TATT B 4
GNDGG
LM1117MPX-5XX .0
U4UU
E36311A-1AA (+25V)
AGND
10V
47uF
C31
AGND
+5V
0
R95
E36311A-1AA (+25V) +5V
LDO
35V
100µF
C30
AGND
RSC
TP21
LEB
TP27
PS
TP26
RT
TP25
SP
TP24
FAULT
TP23
HICC
TP22
VSENSE
TP20
Figure 5-2. TPS7H5001-SP Schematic (Page 2)
Schematics www.ti.com
10 TPS7H5001-SP Evaluation Module SLVUBZ8 – JULY 2021
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1
3
5 6
4
2
7
9 10
8
1211
1413
1615
1817
2019
2221
2423
2625
2827
3029
3231
3433
3635
3837
4039
41 42
J8
DNP
1 3 5
6
4
2
7 9
10
8
12 11
14 13
16 15 18 17 20 19 22 21
24 23
26 25 28 27 30 29 32 31
34 33
36 35 38 37 40 39
41
42
J10
DNP
1
3
5 6
4
2
7
9 10
8
1211
1413
1615
1817
2019
2221
2423
2625
2827
3029
3231
3433
3635
3837
4039
41 42
J7
DNP
1 3 5
6
4
2
7 9
10
8
12 11
14 13
16 15 18 17 20 19 22 21
24 23
26 25 28 27 30 29 32 31
34 33
36 35 38 37 40 39
41
42
J9
DNP
DIO_6B
DIO_7B
PXIe-4112 (CH#1)
PXIe-4112 (CH#1) S+
PXIe-4112 (CH#1) S-
AGND
AGND
0
R109
0
R111
0
R108
DNP
0
R110
DNP
Bottom Side Pogos
PXIe-4139-1 F+
AGND
AGND EGND
PXIe-4139-1 S+
PXIe-4139-1 S-
PXIe-5162_CH0
PXIe-5162_CH1
PXIe-5162_CH2
PXIe-5162_CH3
PXIe-5110_CH0
PXIe-5110_CH1
PXIe-4145 (CH#0) F+
PXIe-4145 (CH#0) S+
PXIe-4145 (CH#0) S-
PXIe-4145 (CH#1) F+
PXIe-4145 (CH#1) S+
PXIe-4145 (CH#1) S-
1 3 5
6
4
2
7 9
10
8
1211
1413
1615 1817 2019 2221
2423
2625 2827 3029 3231
3433
3635 3837 4039
41
42
JJ10
DDDNNNPPP
Bottom Side Pogos
PXIe-4139-1 F+
AGND
AGND EGND
PXPP Ie-4XX 139-1 S+
PXPP Ie-4XX 139-1 S-
PXIe-5162_CH0
PXIe-5162_CH1
PXIe-5162_CH2
PXIe-5162_CH3
PXIe-5110_CH0
PXIe-5110_CH1
PXIe-4145 (CH#0) F+
PXPP Ie-4XX 145 (C45 H#HH 0) S+
PXPP Ie-4XX 145 (C45 H#HH 0) S-
PXIe-4145 (CH#1) F+
PXPP Ie-4XX 145 (C45 H#HH 1) S+
PXPP Ie-4XX 145 (C45 H#HH 1) S-
1
3
5 6
4
2
7
9 10
8
1211
1413
1615
1817
2019
2221
2423
2625
2827
3029
3231
3433
3635
3837
4039
41 42
J8
DDDDNNNPPP
DIO_6B
DIO_7B
0
R109
0
R111
Left Side Pogos
1
3
5 6
4
2
7
9 10
8
1211
1413
1615
1817
2019
2221
2423
2625
2827
3029
3231
3433
3635
3837
4039
41 42
J7
DDDDNNNPPP
0
R108
DDDDDDNNNNNNPPPPP
0
R110
DDDDDDNNNNNNPPPPP
Right Side Pogos
E36311A-1 (+6V)
DMM_Site1_1
DMM_Site1_2
DMM_Site1_3
AWG_CH1_to_SIte1
PXIe-5172-1_CH1_Site1
PXIe-5172-1_CH3_Site1
PXIe-5172-1_CH5_Site1
PXIe-5172-1_CH7_Site1
PXIe-5172-2_CH1_Site1
PXIe-5172-2_CH3_Site1
PXIe-5172-2_CH5_Site1
PXIe-5172-2_CH7_Site1
DMM_Site1_4
DMM_Site1_5
AWG_CH2_to_SIte1
PXIe-5172-1_CH0_Site1
PXIe-5172-1_CH2_Site1
PXIe-5172-1_CH4_Site1
PXIe-5172-1_CH6_Site1
PXIe-5172-2_CH0_Site1
PXIe-5172-2_CH2_Site1
PXIe-5172-2_CH4_Site1
PXIe-5172-2_CH6_Site1
1 3 5
6
4
2
7 9
10
8
1211
1413
1615 1817 2019 2221
2423
2625 2827 3029 3231
3433
3635 3837 4039
41
42
JJ9
DDDNNNNNPPP
PXIe-4112 (CH#1)
PXPP Ie-4XX 112 (C12 H#HH 1) S+
PXPP Ie-4XX 112 (C12 H#HH 1) S-
AGND
AGND
DMM_Site1_1
DMM_Site1_2
DMM_Site1_3
AWAA G_CH1_to__ SIte1
PXIe-5172-1_CH1_Site1
PXIe-5172-1_CH3_Site1
PXIe-5172-1_CH5_Site1
PXIe-5172-1_CH7_Site1
PXIe-5172-2_CH1_Site1
PXIe-5172-2_CH3_Site1
PXIe-5172-2_CH5_Site1
PXIe-5172-2_CH7_Site1
DMM_Site1_4
DMM_Site1_5
AWAA G_CH2_to__ SIte1
PXIe-5172-1_CH0_Site1
PXIe-5172-1_CH2_Site1
PXIe-5172-1_CH4_Site1
PXIe-5172-1_CH6_Site1
PXIe-5172-2_CH0_Site1
PXIe-5172-2_CH2_Site1
PXIe-5172-2_CH4_Site1
PXIe-5172-2_CH6_Site1
Upper Side Pogos
E36311A-1 (+25V)
PXIe-5922_CH0_Site1
PXIe-5922_CH1_Site1
PXIe-4113 (CH#1) F+
PXIe-4113 (CH#1) S+
PXIe-4113 (CH#1) S-
PGND
PGND AGND
EGND
PGND AGND
EGND
Local Star GND Connection
0
R112
DNP
0
R114
DNP
0
R113
DNP
0
R115
DNP
0
R117
DNP
0
R116
DNP
PXIe-4137 S-
PXIe-4137 S+
PXIe-4137 F+
Label Assembly Note
ZZ1
This Assembly Note is for PCB labels only
Assembly Note
ZZ2
These assemblies are ESD sensitive, ESD precautions shall be observed.
Assembly Note
ZZ3
These assemblies must be clean and free from flux a nd all contaminants. Use of no clean flux is not ac ceptable.
Assembly Note
ZZ4
These assemblies must comply with workmanship stand ards IPC-A-610 Class 2, unless otherwise specified.
LOGO
PCB
Texas Instruments
NA
A
PCB Number:
PCB Rev:
Size: 0.65" x 0.20 "
PCB Label
LBL1
THT-14-423-10
CE Mark
LOGO
PCB
FCC disclaimer
LOGO
PCB
WEEE logo
1
H1
NY PMS 440 0025 PH
1
H2
NY PMS 440 0025 PH
1
H3
NY PMS 440 0025 PH
1
H4
NY PMS 440 0025 PH
H5
1902C
H6
1902C
H7
1902C
H8
1902C
FID2
DNP
FID1
DNP
FID3
DNP
Figure 5-3. TPS7H5001-SP Schematic (Page 3)
www.ti.com Schematics
SLVUBZ8 – JULY 2021
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6 Bill of Materials
TPS7H5001-SP Bill of Materials lists the EVM bill of materials (BOM).
Table 6-1. TPS7H5001-SP Bill of Materials
Designator Quantity Value Description Package Reference Part Number Manufacturer
!PCB1 1 Printed Circuit Board NA Any
C1 1 150µF Molded Tantalum Polymer Capacitor 20V
2917 (7343 Metric) 50mOhm @ 100kHz
2917 T521D157M020ATE050 Kemet
C2, C3 2 10uF CAP, CERM, 10 uF, 50 V, ±10%, X5R, 1206 1206 GRM31CR61H106KA12L MuRata
C4 1 0.1uF CAP, CERM, 0.1 uF, 50 V, ±5%, X7R, 1206 1206 12065C104JAT2A AVX
C5, C6, C7, C8, C17 5 20pF CAP, CERM, 20 pF, 100 V, ±5%, C0G/NP0, 0805 0805 08051A200JAT2A AVX
C9, C20, C23, C27, C35 5 0.1uF CAP, CERM, 0.1 uF, 25 V, ±10%, X7R, 0805 0805 C0805C104K3RACTU Kemet
C10 1 500pF CAP, CERM, 500 pF, 50 V,±2%, C0G/NP0, 0805 0805 08055A501GAT2A AVX
C15 1 0.47uF CAP, CERM, 0.47 uF, 50 V, ±10%, X7R, AEC-Q200
Grade 1, 0805
0805 GCM21BR71H474KA55L MuRata
C16 1 0.01uF CAP, CERM, 0.01 uF, 50 V, ±5%, X7R, 0805 0805 08055C103JAT2A AVX
C18 1 1uF CAP, CERM, 1 uF, 50 V, ±10%, X7R, 0805 0805 08055C105KAT2A AVX
C21, C24, C28, C36 4 1uF CAP, CERM, 1 uF, 50 V, ±10%, X7R, 0805 0805 885012207103 Wurth Elektronik
C22, C25, C29, C37 4 1000pF CAP, CERM, 1000 pF, 50 V, ±10%, X7R, 0805 0805 C0805C102K5RACTU Kemet
C30 1 100uF CAP, Tantalum Polymer, 100 µF, 35 V,±20%, 0.1
ohm, 7.3x6.1mm SMD
7.3x6.1mm TCN4107M035R0100 AVX
C31 1 47uF CAP, TA, 47 uF, 10 V, ±10%, 0.5 ohm, SMD 3528-21 TPSB476K010R0500 AVX
H1, H2, H3, H4 4 Machine Screw, Round, #4-40 x 1/4, Nylon, Philips
panhead
Screw NY PMS 440 0025 PH B&F Fastener Supply
H5, H6, H7, H8 4 Standoff, Hex, 0.5"L #4-40 Nylon Standoff 1902C Keystone
J1, J2, J3, J4 4 Compact Probe Tip Circuit Board Test Points, TH, 25
per
TH Scope Probe 131-5031-00 Tektronix
J5 1 Header, 100mil, 2x1, Tin, TH Header, 2 PIN, 100mil,
Tin
PEC02SAAN Sullins Connector
Solutions
J6 1 Header, 100mil, 3x1, Tin, TH Header, 3 PIN, 100mil,
Tin
PEC03SAAN Sullins Connector
Solutions
J11 1 Terminal Block, 5.08 mm, 2x1, Brass, TH 2x1 5.08 mm Terminal
Block
ED120/2DS On-Shore Technology
LBL1 1 Thermal Transfer Printable Labels, 0.650" W x
0.200" H - 10,000 per roll
PCB Label 0.650 x
0.200 inch
THT-14-423-10 Brady
Schematics www.ti.com
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Table 6-1. TPS7H5001-SP Bill of Materials (continued)
Designator Quantity Value Description Package Reference Part Number Manufacturer
R1, R2, R3, R12, R13, R17,
R18, R20, R32, R38, R42, R43,
R44, R48, R49, R53, R54, R55,
R59, R60, R61, R62, R63, R66,
R67, R68, R69, R70, R71, R74,
R75, R76, R77, R78, R79, R80,
R81, R82, R83, R84, R85, R87,
R88, R89, R90, R91, R92, R93,
R98, R99, R102, R103, R109,
R111
54 0 RES, 0, 5%, 0.125 W, 0603 0603 MCT06030Z0000ZP500 Vishay/Beyschlag
R4, R101 2 0 RES, 0, 5%, 1 W, AEC-Q200 Grade 0, 2512 2512 CRCW25120000Z0EG Vishay-Dale
R9, R10 2 10.0k RES, 10.0 k, 1%, 0.125 W, AEC-Q200 Grade 0,
0805
0805 CRCW080510K0FKEA Vishay-Dale
R14 1 1.00k RES, 1.00 k, 0.1%, 0.125 W, 0805 0805 RG2012P-102-B-T5 Susumu Co Ltd
R15 1 20.0k RES, 20.0 k, 0.1%, 0.125 W, 0805 0805 RG2012P-203-B-T5 Susumu Co Ltd
R24, R26 2 10.0 RES, 10.0, 0.1%, 0.1 W, 0805 0805 CRT0805-BY-10R0ELF Bourns
R25 1 3.90k RES, 3.90 k, 0.5%, 0.1 W, 0805 0805 RR1220P-392-D Susumu Co Ltd
R27 1 5.90k RES, 5.90 k, 1%, 0.125 W, AEC-Q200 Grade 0,
0805
0805 CRCW08055K90FKEA Vishay-Dale
R29, R30, R39 3 49.9k RES, 49.9 k, 0.1%, 0.125 W, 0805 0805 RG2012P-4992-B-T5 Susumu Co Ltd
R31 1 135k RES, 135 k, 0.1%, 0.125 W, 0805 0805 RT0805BRD07135KL Yageo America
R33 1 191k RES, 191 k, 1%, 0.125 W, AEC-Q200 Grade 0, 0805 0805 CRCW0805191KFKEA Vishay-Dale
R35 1 1.00Meg RES, 1.00 M, 0.5%, 0.1 W, 0805 0805 RR1220P-105-D Susumu Co Ltd
R36 1 1.0k RES, 1.0 k, 5%, 0.125 W, AEC-Q200 Grade 0, 0805 0805 CRCW08051K00JNEA Vishay-Dale
R40 1 30.0k RES, 30.0 k, 0.5%, 0.1 W, 0805 0805 RR1220P-303-D Susumu Co Ltd
R41 1 4.70k RES, 4.70 k, 1%, 0.5 W, AEC-Q200 Grade 0, 0805 0805 ERJ-P06F4701V Panasonic
R45, R46, R47, R86, R94, R95,
R96, R104, R105, R106, R118
11 0 RES, 0, 1%, 0.1 W, AEC-Q200 Grade 0, 0603 0603 RMCF0603ZT0R00 Stackpole Electronics
Inc
R100 1 10 RES, 10, 5%, 35 W, DDPAK DDPAK TDH35P10R0JE Ohmite
TP1, TP9, TP17, TP18, TP19 5 Test Point, Multipurpose, Purple, TH Purple Multipurpose
Testpoint
5129 Keystone
TP2, TP8, TP16 3 Test Point, Multipurpose, Grey, TH Grey Multipurpose
Testpoint
5128 Keystone
TP3 1 Test Point, Multipurpose, Brown, TH Brown Multipurpose
Testpoint
5125 Keystone
TP4, TP5 2 Test Point, Multipurpose, White, TH White Multipurpose
Testpoint
5012 Keystone
TP7 1 Test Point, Multipurpose, Red, TH Red Multipurpose
Testpoint
5010 Keystone
www.ti.com Schematics
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Table 6-1. TPS7H5001-SP Bill of Materials (continued)
Designator Quantity Value Description Package Reference Part Number Manufacturer
TP10 1 Test Point, Multipurpose, Blue, TH Blue Multipurpose
Testpoint
5127 Keystone
TP11, TP20, TP21, TP22,
TP23, TP24, TP25, TP26,
TP27
9 Test Point, Multipurpose, Orange, TH Orange Multipurpose
Testpoint
5013 Keystone
TP13, TP14 2 Test Point, Miniature, SMT Test Point, Miniature,
SMT
5019 Keystone
TP28, TP29, TP30, TP31 4 Test Point, Miniature, Black, TH Black Miniature
Testpoint
5001 Keystone
U1 1 Radiation-Hardness-Assured Si and GaN Dual
Output Controller
CFP22 TPS7H5001HKY-EM Texas Instruments
U2, U3 2 Single 2-Input Positive-AND Gate, DCK0005A,
LARGE T&R
DCK0005A SN74AHCT1G08DCKR Texas Instruments
U4 1 800mA Low-Dropout Linear Regulator, 4-pin
SOT-223
DCY0004A TLV1117-50DCY Texas Instruments
U5, U6 2 250 MHz, Rail-to-Rail I/O, CMOS Single Operational
Amplifier, 2.5 to 5.5 V, -40 to 125 degC, 5-pin SOT23
(DBV5), Green (RoHS & no Sb/Br)
DBV0005A OPA354AIDBVR Texas Instruments
C11 0 1000pF CAP, CERM, 1000 pF, 50 V, ±10%, C0G/NP0, 0805 0805 08055A102KAT2A AVX
C12 0 0.01uF CAP, CERM, 0.01 uF, 50 V, ±20%, X7R, 0805 0805 C0805C103M5RACTU Kemet
C13 0 0.47uF CAP, CERM, 0.47 uF, 50 V, ±10%, X7R, AEC-Q200
Grade 1, 0805
0805 GCM21BR71H474KA55L MuRata
C14 0 1uF CAP, CERM, 1 µF, 50 V,±5%, X7R, AEC-Q200
Grade 1, 1210
1210 C1210C105J5RACTU Kemet
C19, C32, C33, C38, C39 0 0.1uF CAP, CERM, 0.1 uF, 25 V, ±10%, X7R, 0805 0805 C0805C104K3RACTU Kemet
C26, C34 0 0.1uF CAP, CERM, 0.1 uF, 25 V, ±10%, X7R, 0603 0603 C0603X104K3RACTU Kemet
FID1, FID2, FID3 0 Fiducial mark. There is nothing to buy or mount. N/A N/A N/A
J7, J8, J9, J10 0 Header Mate, 2.54mm, 21x2 Pads to Mate with Mill-
Max_820-22-042-30-00
1101
820-22-042-30-001101_MA
TE
Mill-Max
R5, R6, R7, R8 0 1.00Meg RES, 1.00 M, 0.5%, 0.1 W, 0805 0805 RR1220P-105-D Susumu Co Ltd
R11, R16, R19, R22, R28, R34,
R37, R50, R51, R52, R56,
R57, R58, R64, R65, R72,
R73, R108, R110, R112, R113,
R114, R115, R116, R117
0 0 RES, 0, 5%, 0.125 W, 0603 0603 MCT06030Z0000ZP500 Vishay/Beyschlag
R21 0 10.0k RES, 10.0 k, 1%, 0.2 W, 0805 0805 MCU08050C1002FP500 Vishay/Beyschlag
R23, R97, R107 0 0 RES, 0, 1%, 0.1 W, AEC-Q200 Grade 0, 0603 0603 RMCF0603ZT0R00 Stackpole Electronics
Inc
Schematics www.ti.com
14 TPS7H5001-SP Evaluation Module SLVUBZ8 – JULY 2021
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STANDARD TERMS FOR EVALUATION MODULES
1. Delivery: TI delivers TI evaluation boards, kits, or modules, including any accompanying demonstration software, components, and/or
documentation which may be provided together or separately (collectively, an “EVM” or “EVMs”) to the User (“User”) in accordance
with the terms set forth herein. User's acceptance of the EVM is expressly subject to the following terms.
1.1 EVMs are intended solely for product or software developers for use in a research and development setting to facilitate feasibility
evaluation, experimentation, or scientific analysis of TI semiconductors products. EVMs have no direct function and are not
finished products. EVMs shall not be directly or indirectly assembled as a part or subassembly in any finished product. For
clarification, any software or software tools provided with the EVM (“Software”) shall not be subject to the terms and conditions
set forth herein but rather shall be subject to the applicable terms that accompany such Software
1.2 EVMs are not intended for consumer or household use. EVMs may not be sold, sublicensed, leased, rented, loaned, assigned,
or otherwise distributed for commercial purposes by Users, in whole or in part, or used in any finished product or production
system.
2Limited Warranty and Related Remedies/Disclaimers:
2.1 These terms do not apply to Software. The warranty, if any, for Software is covered in the applicable Software License
Agreement.
2.2 TI warrants that the TI EVM will conform to TI's published specifications for ninety (90) days after the date TI delivers such EVM
to User. Notwithstanding the foregoing, TI shall not be liable for a nonconforming EVM if (a) the nonconformity was caused by
neglect, misuse or mistreatment by an entity other than TI, including improper installation or testing, or for any EVMs that have
been altered or modified in any way by an entity other than TI, (b) the nonconformity resulted from User's design, specifications
or instructions for such EVMs or improper system design, or (c) User has not paid on time. Testing and other quality control
techniques are used to the extent TI deems necessary. TI does not test all parameters of each EVM.
User's claims against TI under this Section 2 are void if User fails to notify TI of any apparent defects in the EVMs within ten (10)
business days after delivery, or of any hidden defects with ten (10) business days after the defect has been detected.
2.3 TI's sole liability shall be at its option to repair or replace EVMs that fail to conform to the warranty set forth above, or credit
User's account for such EVM. TI's liability under this warranty shall be limited to EVMs that are returned during the warranty
period to the address designated by TI and that are determined by TI not to conform to such warranty. If TI elects to repair or
replace such EVM, TI shall have a reasonable time to repair such EVM or provide replacements. Repaired EVMs shall be
warranted for the remainder of the original warranty period. Replaced EVMs shall be warranted for a new full ninety (90) day
warranty period.
WARNING
Evaluation Kits are intended solely for use by technically qualified,
professional electronics experts who are familiar with the dangers
and application risks associated with handling electrical mechanical
components, systems, and subsystems.
User shall operate the Evaluation Kit within TI’s recommended
guidelines and any applicable legal or environmental requirements
as well as reasonable and customary safeguards. Failure to set up
and/or operate the Evaluation Kit within TI’s recommended
guidelines may result in personal injury or death or property
damage. Proper set up entails following TI’s instructions for
electrical ratings of interface circuits such as input, output and
electrical loads.
NOTE:
EXPOSURE TO ELECTROSTATIC DISCHARGE (ESD) MAY CAUSE DEGREDATION OR FAILURE OF THE EVALUATION
KIT; TI RECOMMENDS STORAGE OF THE EVALUATION KIT IN A PROTECTIVE ESD BAG.

www.ti.com
2
3Regulatory Notices:
3.1 United States
3.1.1 Notice applicable to EVMs not FCC-Approved:
FCC NOTICE: This kit is designed to allow product developers to evaluate electronic components, circuitry, or software
associated with the kit to determine whether to incorporate such items in a finished product and software developers to write
software applications for use with the end product. This kit is not a finished product and when assembled may not be resold or
otherwise marketed unless all required FCC equipment authorizations are first obtained. Operation is subject to the condition
that this product not cause harmful interference to licensed radio stations and that this product accept harmful interference.
Unless the assembled kit is designed to operate under part 15, part 18 or part 95 of this chapter, the operator of the kit must
operate under the authority of an FCC license holder or must secure an experimental authorization under part 5 of this chapter.
3.1.2 For EVMs annotated as FCC – FEDERAL COMMUNICATIONS COMMISSION Part 15 Compliant:
CAUTION
This device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not
cause harmful interference, and (2) this device must accept any interference received, including interference that may cause
undesired operation.
Changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to
operate the equipment.
FCC Interference Statement for Class A EVM devices
NOTE: This equipment has been tested and found to comply with the limits for a Class A digital device, pursuant to part 15 of
the FCC Rules. These limits are designed to provide reasonable protection against harmful interference when the equipment is
operated in a commercial environment. This equipment generates, uses, and can radiate radio frequency energy and, if not
installed and used in accordance with the instruction manual, may cause harmful interference to radio communications.
Operation of this equipment in a residential area is likely to cause harmful interference in which case the user will be required to
correct the interference at his own expense.
FCC Interference Statement for Class B EVM devices
NOTE: This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 of
the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential
installation. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordance
with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference
will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which
can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more
of the following measures:
•Reorient or relocate the receiving antenna.
•Increase the separation between the equipment and receiver.
•Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.
•Consult the dealer or an experienced radio/TV technician for help.
3.2 Canada
3.2.1 For EVMs issued with an Industry Canada Certificate of Conformance to RSS-210 or RSS-247
Concerning EVMs Including Radio Transmitters:
This device complies with Industry Canada license-exempt RSSs. Operation is subject to the following two conditions:
(1) this device may not cause interference, and (2) this device must accept any interference, including interference that may
cause undesired operation of the device.
Concernant les EVMs avec appareils radio:
Le présent appareil est conforme aux CNR d'Industrie Canada applicables aux appareils radio exempts de licence. L'exploitation
est autorisée aux deux conditions suivantes: (1) l'appareil ne doit pas produire de brouillage, et (2) l'utilisateur de l'appareil doit
accepter tout brouillage radioélectrique subi, même si le brouillage est susceptible d'en compromettre le fonctionnement.
Concerning EVMs Including Detachable Antennas:
Under Industry Canada regulations, this radio transmitter may only operate using an antenna of a type and maximum (or lesser)
gain approved for the transmitter by Industry Canada. To reduce potential radio interference to other users, the antenna type
and its gain should be so chosen that the equivalent isotropically radiated power (e.i.r.p.) is not more than that necessary for
successful communication. This radio transmitter has been approved by Industry Canada to operate with the antenna types
listed in the user guide with the maximum permissible gain and required antenna impedance for each antenna type indicated.
Antenna types not included in this list, having a gain greater than the maximum gain indicated for that type, are strictly prohibited
for use with this device.

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Concernant les EVMs avec antennes détachables
Conformément à la réglementation d'Industrie Canada, le présent émetteur radio peut fonctionner avec une antenne d'un type et
d'un gain maximal (ou inférieur) approuvé pour l'émetteur par Industrie Canada. Dans le but de réduire les risques de brouillage
radioélectrique à l'intention des autres utilisateurs, il faut choisir le type d'antenne et son gain de sorte que la puissance isotrope
rayonnée équivalente (p.i.r.e.) ne dépasse pas l'intensité nécessaire à l'établissement d'une communication satisfaisante. Le
présent émetteur radio a été approuvé par Industrie Canada pour fonctionner avec les types d'antenne énumérés dans le
manuel d’usage et ayant un gain admissible maximal et l'impédance requise pour chaque type d'antenne. Les types d'antenne
non inclus dans cette liste, ou dont le gain est supérieur au gain maximal indiqué, sont strictement interdits pour l'exploitation de
l'émetteur
3.3 Japan
3.3.1 Notice for EVMs delivered in Japan: Please see http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_01.page 日本国内に
輸入される評価用キット、ボードについては、次のところをご覧ください。
http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_01.page
3.3.2 Notice for Users of EVMs Considered “Radio Frequency Products” in Japan: EVMs entering Japan may not be certified
by TI as conforming to Technical Regulations of Radio Law of Japan.
If User uses EVMs in Japan, not certified to Technical Regulations of Radio Law of Japan, User is required to follow the
instructions set forth by Radio Law of Japan, which includes, but is not limited to, the instructions below with respect to EVMs
(which for the avoidance of doubt are stated strictly for convenience and should be verified by User):
1. Use EVMs in a shielded room or any other test facility as defined in the notification #173 issued by Ministry of Internal
Affairs and Communications on March 28, 2006, based on Sub-section 1.1 of Article 6 of the Ministry’s Rule for
Enforcement of Radio Law of Japan,
2. Use EVMs only after User obtains the license of Test Radio Station as provided in Radio Law of Japan with respect to
EVMs, or
3. Use of EVMs only after User obtains the Technical Regulations Conformity Certification as provided in Radio Law of Japan
with respect to EVMs. Also, do not transfer EVMs, unless User gives the same notice above to the transferee. Please note
that if User does not follow the instructions above, User will be subject to penalties of Radio Law of Japan.
【無線電波を送信する製品の開発キットをお使いになる際の注意事項】 開発キットの中には技術基準適合証明を受けて
いないものがあります。 技術適合証明を受けていないもののご使用に際しては、電波法遵守のため、以下のいずれかの
措置を取っていただく必要がありますのでご注意ください。
1. 電波法施行規則第6条第1項第1号に基づく平成18年3月28日総務省告示第173号で定められた電波暗室等の試験設備でご使用
いただく。
2. 実験局の免許を取得後ご使用いただく。
3. 技術基準適合証明を取得後ご使用いただく。
なお、本製品は、上記の「ご使用にあたっての注意」を譲渡先、移転先に通知しない限り、譲渡、移転できないものとします。
上記を遵守頂けない場合は、電波法の罰則が適用される可能性があることをご留意ください。 日本テキサス・イ
ンスツルメンツ株式会社
東京都新宿区西新宿６丁目２４番１号
西新宿三井ビル
3.3.3 Notice for EVMs for Power Line Communication: Please see http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_02.page
電力線搬送波通信についての開発キットをお使いになる際の注意事項については、次のところをご覧ください。http:/
/www.tij.co.jp/lsds/ti_ja/general/eStore/notice_02.page
3.4 European Union
3.4.1 For EVMs subject to EU Directive 2014/30/EU (Electromagnetic Compatibility Directive):
This is a class A product intended for use in environments other than domestic environments that are connected to a
low-voltage power-supply network that supplies buildings used for domestic purposes. In a domestic environment this
product may cause radio interference in which case the user may be required to take adequate measures.

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4EVM Use Restrictions and Warnings:
4.1 EVMS ARE NOT FOR USE IN FUNCTIONAL SAFETY AND/OR SAFETY CRITICAL EVALUATIONS, INCLUDING BUT NOT
LIMITED TO EVALUATIONS OF LIFE SUPPORT APPLICATIONS.
4.2 User must read and apply the user guide and other available documentation provided by TI regarding the EVM prior to handling
or using the EVM, including without limitation any warning or restriction notices. The notices contain important safety information
related to, for example, temperatures and voltages.
4.3 Safety-Related Warnings and Restrictions:
4.3.1 User shall operate the EVM within TI’s recommended specifications and environmental considerations stated in the user
guide, other available documentation provided by TI, and any other applicable requirements and employ reasonable and
customary safeguards. Exceeding the specified performance ratings and specifications (including but not limited to input
and output voltage, current, power, and environmental ranges) for the EVM may cause personal injury or death, or
property damage. If there are questions concerning performance ratings and specifications, User should contact a TI
field representative prior to connecting interface electronics including input power and intended loads. Any loads applied
outside of the specified output range may also result in unintended and/or inaccurate operation and/or possible
permanent damage to the EVM and/or interface electronics. Please consult the EVM user guide prior to connecting any
load to the EVM output. If there is uncertainty as to the load specification, please contact a TI field representative.
During normal operation, even with the inputs and outputs kept within the specified allowable ranges, some circuit
components may have elevated case temperatures. These components include but are not limited to linear regulators,
switching transistors, pass transistors, current sense resistors, and heat sinks, which can be identified using the
information in the associated documentation. When working with the EVM, please be aware that the EVM may become
very warm.
4.3.2 EVMs are intended solely for use by technically qualified, professional electronics experts who are familiar with the
dangers and application risks associated with handling electrical mechanical components, systems, and subsystems.
User assumes all responsibility and liability for proper and safe handling and use of the EVM by User or its employees,
affiliates, contractors or designees. User assumes all responsibility and liability to ensure that any interfaces (electronic
and/or mechanical) between the EVM and any human body are designed with suitable isolation and means to safely
limit accessible leakage currents to minimize the risk of electrical shock hazard. User assumes all responsibility and
liability for any improper or unsafe handling or use of the EVM by User or its employees, affiliates, contractors or
designees.
4.4 User assumes all responsibility and liability to determine whether the EVM is subject to any applicable international, federal,
state, or local laws and regulations related to User’s handling and use of the EVM and, if applicable, User assumes all
responsibility and liability for compliance in all respects with such laws and regulations. User assumes all responsibility and
liability for proper disposal and recycling of the EVM consistent with all applicable international, federal, state, and local
requirements.
5. Accuracy of Information: To the extent TI provides information on the availability and function of EVMs, TI attempts to be as accurate
as possible. However, TI does not warrant the accuracy of EVM descriptions, EVM availability or other information on its websites as
accurate, complete, reliable, current, or error-free.
6. Disclaimers:
6.1 EXCEPT AS SET FORTH ABOVE, EVMS AND ANY MATERIALS PROVIDED WITH THE EVM (INCLUDING, BUT NOT
LIMITED TO, REFERENCE DESIGNS AND THE DESIGN OF THE EVM ITSELF) ARE PROVIDED "AS IS" AND "WITH ALL
FAULTS." TI DISCLAIMS ALL OTHER WARRANTIES, EXPRESS OR IMPLIED, REGARDING SUCH ITEMS, INCLUDING BUT
NOT LIMITED TO ANY EPIDEMIC FAILURE WARRANTY OR IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS
FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF ANY THIRD PARTY PATENTS, COPYRIGHTS, TRADE
SECRETS OR OTHER INTELLECTUAL PROPERTY RIGHTS.
6.2 EXCEPT FOR THE LIMITED RIGHT TO USE THE EVM SET FORTH HEREIN, NOTHING IN THESE TERMS SHALL BE
CONSTRUED AS GRANTING OR CONFERRING ANY RIGHTS BY LICENSE, PATENT, OR ANY OTHER INDUSTRIAL OR
INTELLECTUAL PROPERTY RIGHT OF TI, ITS SUPPLIERS/LICENSORS OR ANY OTHER THIRD PARTY, TO USE THE
EVM IN ANY FINISHED END-USER OR READY-TO-USE FINAL PRODUCT, OR FOR ANY INVENTION, DISCOVERY OR
IMPROVEMENT, REGARDLESS OF WHEN MADE, CONCEIVED OR ACQUIRED.
7. USER'S INDEMNITY OBLIGATIONS AND REPRESENTATIONS. USER WILL DEFEND, INDEMNIFY AND HOLD TI, ITS
LICENSORS AND THEIR REPRESENTATIVES HARMLESS FROM AND AGAINST ANY AND ALL CLAIMS, DAMAGES, LOSSES,
EXPENSES, COSTS AND LIABILITIES (COLLECTIVELY, "CLAIMS") ARISING OUT OF OR IN CONNECTION WITH ANY
HANDLING OR USE OF THE EVM THAT IS NOT IN ACCORDANCE WITH THESE TERMS. THIS OBLIGATION SHALL APPLY
WHETHER CLAIMS ARISE UNDER STATUTE, REGULATION, OR THE LAW OF TORT, CONTRACT OR ANY OTHER LEGAL
THEORY, AND EVEN IF THE EVM FAILS TO PERFORM AS DESCRIBED OR EXPECTED.

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8. Limitations on Damages and Liability:
8.1 General Limitations. IN NO EVENT SHALL TI BE LIABLE FOR ANY SPECIAL, COLLATERAL, INDIRECT, PUNITIVE,
INCIDENTAL, CONSEQUENTIAL, OR EXEMPLARY DAMAGES IN CONNECTION WITH OR ARISING OUT OF THESE
TERMS OR THE USE OF THE EVMS , REGARDLESS OF WHETHER TI HAS BEEN ADVISED OF THE POSSIBILITY OF
SUCH DAMAGES. EXCLUDED DAMAGES INCLUDE, BUT ARE NOT LIMITED TO, COST OF REMOVAL OR
REINSTALLATION, ANCILLARY COSTS TO THE PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES, RETESTING,
OUTSIDE COMPUTER TIME, LABOR COSTS, LOSS OF GOODWILL, LOSS OF PROFITS, LOSS OF SAVINGS, LOSS OF
USE, LOSS OF DATA, OR BUSINESS INTERRUPTION. NO CLAIM, SUIT OR ACTION SHALL BE BROUGHT AGAINST TI
MORE THAN TWELVE (12) MONTHS AFTER THE EVENT THAT GAVE RISE TO THE CAUSE OF ACTION HAS
OCCURRED.
8.2 Specific Limitations. IN NO EVENT SHALL TI'S AGGREGATE LIABILITY FROM ANY USE OF AN EVM PROVIDED
HEREUNDER, INCLUDING FROM ANY WARRANTY, INDEMITY OR OTHER OBLIGATION ARISING OUT OF OR IN
CONNECTION WITH THESE TERMS, , EXCEED THE TOTAL AMOUNT PAID TO TI BY USER FOR THE PARTICULAR
EVM(S) AT ISSUE DURING THE PRIOR TWELVE (12) MONTHS WITH RESPECT TO WHICH LOSSES OR DAMAGES ARE
CLAIMED. THE EXISTENCE OF MORE THAN ONE CLAIM SHALL NOT ENLARGE OR EXTEND THIS LIMIT.
9. Return Policy. Except as otherwise provided, TI does not offer any refunds, returns, or exchanges. Furthermore, no return of EVM(s)
will be accepted if the package has been opened and no return of the EVM(s) will be accepted if they are damaged or otherwise not in
a resalable condition. If User feels it has been incorrectly charged for the EVM(s) it ordered or that delivery violates the applicable
order, User should contact TI. All refunds will be made in full within thirty (30) working days from the return of the components(s),
excluding any postage or packaging costs.
10. Governing Law: These terms and conditions shall be governed by and interpreted in accordance with the laws of the State of Texas,
without reference to conflict-of-laws principles. User agrees that non-exclusive jurisdiction for any dispute arising out of or relating to
these terms and conditions lies within courts located in the State of Texas and consents to venue in Dallas County, Texas.
Notwithstanding the foregoing, any judgment may be enforced in any United States or foreign court, and TI may seek injunctive relief
in any United States or foreign court.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2019, Texas Instruments Incorporated

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AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party
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TI’s products are provided subject to TI’s Terms of Sale (https:www.ti.com/legal/termsofsale.html) or other applicable terms available either
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applicable warranties or warranty disclaimers for TI products.IMPORTANT NOTICE
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Copyright © 2021, Texas Instruments Incorporated