Texas Instruments LP876242-Q1 User manual

User’s Guide
LP876242-Q1 Evaluation Module
ABSTRACT
The LP876242-Q1 Evaluation Module (EVM) highlights the performance and flexibility of the LP876242-Q1
power management integrated circuit (PMIC) for xWR radar applications. Use this document in conjunction with
the Scalable PMIC's GUI User's Guide SLVUBT8 and the LP876242-Q1 Four 8.8-MHz Buck Converters for
AWR and IWR MMICs SNVSC07.
Caution Caution Hot surface.
Contact may cause burns.
Do not touch!
Table of Contents
1 Introduction.............................................................................................................................................................................3
2 Getting Started........................................................................................................................................................................3
2.1 The GUI Tool...................................................................................................................................................................... 4
3 EVM Details............................................................................................................................................................................. 4
3.1 Terminal Blocks.................................................................................................................................................................. 4
3.2 Test Point Descriptions.......................................................................................................................................................4
3.3 Configuration Headers....................................................................................................................................................... 4
3.4 Connectors.........................................................................................................................................................................6
3.5 DIP Switches......................................................................................................................................................................7
3.6 EVM Control and GPIO......................................................................................................................................................8
4 Customization......................................................................................................................................................................... 9
4.1 Changing the Communication Interface.............................................................................................................................9
5 Schematic, Layout, and Bill of Materials............................................................................................................................ 10
6 Additional Resources...........................................................................................................................................................23
7 Revision History................................................................................................................................................................... 23
List of Figures
Figure 2-1. EVM Top View........................................................................................................................................................... 3
Figure 3-1. EVM Header J18....................................................................................................................................................... 5
Figure 3-2. EVM Bottom Side...................................................................................................................................................... 7
Figure 4-1. Interface Settings for I2C Communication................................................................................................................. 9
Figure 5-1. Main Schematic Page............................................................................................................................................. 10
Figure 5-2. MCU Schematic Page............................................................................................................................................. 11
Figure 5-3. Layout Top, Layer 1.................................................................................................................................................12
Figure 5-4. Layout Ground, Layer 2...........................................................................................................................................13
Figure 5-5. Layout Signal, Layer 3.............................................................................................................................................14
Figure 5-6. Layout Signal, Layer 4.............................................................................................................................................15
Figure 5-7. Layout Ground, Layer 5...........................................................................................................................................16
Figure 5-8. Layout Bottom, Layer 6........................................................................................................................................... 17
List of Tables
Table 3-1. Terminal Blocks...........................................................................................................................................................4
Table 3-2. Test Point Descriptions............................................................................................................................................... 4
Table 3-3. Header J18 Description.............................................................................................................................................. 5
Table 3-4. Header J33 VIO Voltage Select.................................................................................................................................. 6
Table 3-5. Header J24, 3.3V/5V, GPIO2/I2C/SPI.........................................................................................................................6
Table 3-6. DC Block..................................................................................................................................................................... 7
Table 3-7. DIP Switches...............................................................................................................................................................8
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Table 3-8. EVM LED Indicators....................................................................................................................................................8
Table 5-1. Bill of Materials..........................................................................................................................................................18
Trademarks
All trademarks are the property of their respective owners.
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1 Introduction
The LP876242-Q1 power management integrated circuit (PMIC) family is extremely flexible and scalable,
providing configurability at the device and system level. At the device level, a single PMIC provides four separate
step down converters (BUCK regulators). These BUCK regulators have been tested to conform with the radar
specification and are switched at 8.8 MHz switching frequency. The LP876242-Q1 evaluation module (EVM) is
both an evaluation and development tool. With the EVM both device level and system level configurability are
available through an easy to use graphical user interface (GUI) tool.
2 Getting Started
Only a power supply and the EVM are required to evaluate and test the LP876242-Q1 default configuration
under load conditions. To start evaluating the LP876242-Q1 follow the following steps.
1. Connect power to the EVM.
2. Connect the EVM to the host PC through the USB. In the event that the power is provided by the USB cable,
apply the appropriate jumper connection to connect +VBUS and VCCA see Table 3-5.
3. Launch the GUI and evaluate.
Terminal J7, labeled VCCA in Figure 2-1, can accept wire gauges up to 14 AWG. The voltage supplied must be
within the input range of the device, 2.8 V to 5.5 V. The power supply providing the input to VCCA is required to
supply 135 % of the output power. Once power has been supplied to VCCA, the GPIO4 / ENABLE jumper can
be used to power on the output rails. The default ON Request for the device is the ENABLE pin which is a level
sensitive input. Please refer to LP876242-Q1 data sheet for more details.
Figure 2-1 shows the top side of the LP876242Q1EVM.
Figure 2-1. EVM Top View
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2.1 The GUI Tool
Texas Instruments provides a GUI tool to enable, configure, and evaluate the various features of the LP876242-
Q1 with the EVM. Please refer to the GUI User's Guide SLVUBT8 for a more detailed description of this tool.
The GUI runs on most PC platforms and requires an available USB port. The EVM USB connector is type-C and
a type-A to type-C cable is provided with the EVM to connect to the host computer. The EVM enumerates as two
COM ports and one additional port for the device firmware updates. The GUI uses ACCtrl COM port which can
be found from the device manager of the operating system. The COM port can be changed from the GUI from
Options—Device Settings menu.
A tool for estimating the efficiency of LP876242-Q1 device is also available called PMIC Efficiency Estimator
Tool. The tool can be accessed here.
3 EVM Details
The following sections describe the various interfaces for measuring and controlling the configuration. Note: the
configurations are in coordination with the settings of the PMIC. It is important to understand that both the EVM
configuration and the settings of the PMIC must match. The communication interface can be easily changed
using the jumpers on J18 and J24. Please refer to the GUI User's Guide SLVUBT8 on how to update the PMIC
communication protocol.
3.1 Terminal Blocks
The terminal blocks are simple push and release terminals which can accommodate wire sizes up to 14 AWG.
Table 3-1 lists the terminal blocks found around the perimeter of the EVM. J7, VCCA, is the input voltage for the
regulators. The rest of the terminal blocks are for the BUCK outputs.
Table 3-1. Terminal Blocks
Terminal Designator Description
VCCA J7 All Regulator Input, 2.8 V to 5.5 V Range
BUCK1 J8 Buck 1 Output, 2 A Capable
BUCK2 J10 Buck 2 Output, 4 A Capable
BUCK3 J12 Buck 3 Output, 3 A Capable
BUCK4 J14 Buck 4 Output, 3 A Capable
3.2 Test Point Descriptions
Numerous test points are provided to access voltages and signals. Test points marked with _S are designed for
sensing voltages only and are not designed to carry large DC currents.
Table 3-2. Test Point Descriptions
Test Point Device Pin Description
TP1 VCCA_S VCCA voltage sense point. Routed from
close to the VCCA pin of the LP876242-Q1.
TP2, TP4, TP6, TP7, TP9, TP12, TP15 GND_S Ground sense points routed from various
locations.
TP3 VOUT_LDO_S Voltage sense point for the internal LDO
output voltage.
TP5 VIO_S VIO voltage sense routed from the VIO pin of
the LP876242-Q1.
TP8, TP10, TP11, TP13, TP14, TP16 GND Solid ground points. Are able to carry larger
DC currents.
J20,J21,J25,J26 FB_B1,FB_B2,FB_B3,FB_B4 Buck output voltage sense points.
3.3 Configuration Headers
There are four headers available to configure the EVM function. Header J18, as shown in the silk screen picture
in Figure 3-1, is used to configure the EVM to match the settings written to the LP876242-Q1 configuration
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registers. J33 is used to select the PMIC IO voltage, either 1.8 V or 3.3 V. The fifth header is J24 which allows
VCCA to be powered from the USB connection and the configuration of GPIO2, I2C2 or SPI.
Figure 3-1. EVM Header J18
Table 3-3. Header J18 Description
Option Pins Configuration Description
SPI_EN Open I2C Mode. The signal path for I2C communication between the MCU
and the PMIC is enabled.
Closed (Default) SPI mode. The signal path for SPI communication between the MCU
and the PMIC is enabled.
GPIO3, SDA2/SDO Open GPIO mode. GPIO2 from PMIC is connected to PM7 of the MCU
through a level translator.
GPIO3,SDA2/SDO: Closed
(Default)
I2C Mode (J18 VIO, I2C/SPI:
Open)
Q&A Watchdog mode. GPIO3
supports the Q&A Watchdog
when PMIC is in the Alternative
function and the I2C mode is
selected. This setting is also
done on connector J24 by closing
GPIO2 to SCL2/CS if I2C2 is
wanted to be used.
SPI mode (J18 VIO, I2C/SPI:
Closed)
SPI mode, Chip Select. GPIO2
and GPIO3 supports SPI
communication when the PMIC
is in the Alternative function.
This setting is also done on
connector J24 by closing GPIO2
to SCL2/CS if I2C2 is wanted to
be used.
GPIO6, nERR_MCU, GPIO7 Open (Default) GPIO mode. GPIO6 of the PMIC is connected to PP5 of the through
a level translator.
GPIO6, nERR_MCU Closed System error count down input signal from the MCU. VIO Select
must be 3.3 V. GPIO6 or GPIO7 supports the system error count
down from the MCU when the PMIC is in the Alternative function.
nERR_MCU, GPIO7 Closed
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Table 3-3. Header J18 Description (continued)
Option Pins Configuration Description
GPIO2, TRIG_WDG, GPIO4 Open (Default) GPIO mode. GPIO7 of the PMIC is connected to PH0 of the through
a level translator.
GPIO2, TRIG_WDG Closed Trigger signal for trigger mode watchdog. VIO Select must be 3.3 V.
GPIO7 or GPIO6 supports the trigger mode watchdog signal when
the PMIC is in the Alternative function.
TRIG_WDG, GPIO4 Closed
Table 3-4. Header J33 VIO Voltage Select
Configuration Description
Open Not Allowed
VIO Select, 3.3 V: Closed (Default) VIO is 3.3 V.
VIO Select, 1.8 V: Closed VIO is 1.8 V.
Table 3-5. Header J24, 3.3V/5V, GPIO2/I2C/SPI
Configuration Description
3.3V, VCCA: Closed 3.3 V from TLV733P-Q1 (U12) is connected to VCCA. The input for U12 is the 5 V from the
USB connection (VBUS). VBUS is not intended to support heavy load conditions. 2 W is the
maximum power which can be drawn from the USB. This header configuration is the normal
state of EVM.
EN_5V0, 3.3V, VCCA,5.0V: Open VBUS, and USB_3V3 are isolated. VCCA is powered from J7.
EN_5V0,3.3V: Closed 5V from USB port is enabled. 5V regulated supply can be used to power up VCCA.
VCCA, 5.0V: Closed 5 V from USB Port is connected to VCCA. This supply is not intended to support heavy load
conditions Do not draw more than 2 W from the USB.
SCL2/CS, GPIO2: Open GPIO mode. GPIO2 of the PMIC is connected to IO2 of the MCU.
SCL2/CS, GPIO2: Closed (Default) I2C mode (J18 SPI_EN: Open) Q&A Watchdog mode. GPIO2 and GPIO3
supports the Q&A Watchdog when the
PMIC is in Alternative function and the I2C
mode selected. This setting is also done
on connector J18 by closing GPIO3 to
SDA2/SDO if I2C2 is wanted to be used.
SPI mode (J18 SPI_EN: Closed) SPI mode, Chip Select. GPIO2 and GPIO3
supports SPI communication when the PMIC
is in the Alternative function. This setting
is also done on connector J18 by closing
GPIO3 to SDA2/SDO.
Note
The PMIC device can be configured for a power good level of 3.3 V or 5.0 V for the VCCA pin.
If VCCA_VMON feature is enabled please check that the input voltage is correct and use sense
connection to compensate IR voltage drop with heavy load currents. Align the 3.3V/5.0V jumper with
the PMIC configuration. The default PMIC configuration supports the whole recommended VCCA
voltage range.
3.4 Connectors
Four SMA (J3, J5, J6, J16) connectors are included in the EVM, one for each buck. These connectors can be
used for noise and ripple measurements and are DC filtered with 10 µF capacitors and terminated with 50 Ω
resistors. The location of the DC filtering capacitor can be changed to alter the measurement point to be either
after or before the second LC filtering stage. The default configuration is that each of the connectors take the
measurement after the filter. The corresponding DC capacitor footprints are marked on the bottom side of the
PCB as shown in Figure 3-2 and summarized in Table 3-6
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Figure 3-2. EVM Bottom Side
Table 3-6. DC Block
Measurement point BUCK1 BUCK2 BUCK3 BUCK4
After second LC stage
(Filtered) (default)
C15 C42 C59 C66
Before second LC stage
(Unfiltered)
C10 C36 C58 C65
Two load module connector footprints are provided, J1 and J2. These connectors are intended to be used
with PMICLOADBOARDEVM which is sold separately. The connector components are not populated and the
required connectors are shipped with PMICLOADBOARDEVM.
3.5 DIP Switches
There are three DIP switches S1, S2 and S3 on the back side of the PCB. S1 switch can be used for configuring
chip select for target device in multi PMIC/stacked use case. S2 and S3 switches allow the user to disconnect
the level shifter from the PMIC GPIOs or serial interfaces. The level shifter has pull-ups on the MCU side that
can cause unwanted high state on the GPIO signals if configured in high impedance state. See the Table 3-7 for
the descriptions of the switches.
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Table 3-7. DIP Switches
Switch Pin Signal line
S1 1-12 CS5
2-11 CS4
3-10 CS3
4-9 CS2
5-8 CS1
6-7 GPIO2
S2 1-16 SDA_I2C1/SDI_SPI
2-15 SCL_I2C1/SCK_SPI
3-14 SDA_I2C2/SDO_SPI
4-13 SCL_I2C2/CS_SPI
5-12 GPIO1
6-11 GPIO2
7-10 GPIO3
8-9 GPIO4
S3 1-16 GPIO5
2-15 GPIO6
3-14 GPIO7
4-13 GPIO8
5-12 GPIO9
6-11 GPIO10
7-10 Not connected
8-9 nINT
3.6 EVM Control and GPIO
The EVM has a built-in USB interface based on the MSP432E401Y (U3) to allow the GUI, from the host
computer, to communicate with the PMIC. The supply voltage required by the MSP432E401Y is generated
automatically by the TLV73333PQDRVRQ1 (U12) and TLV73318PQDRVRQ1 (U13) devices which provides 3.3
V and 1.8 V from USB power, +VBUS. These voltages are available for supplying VIO for the PMIC (selectable
from J33). Two SN74GTL2003 level shifters (U4, U6) are used in order to support the use case of the PMIC
VIO of 1.8 V (the MCU IO is 3.3 V). In addition to the level shifters, the TS3A5018RSVR (U8) switch is used
to apply the pullup voltages to the I2C lines only when the EVM is configured as controller (J17). Additional
TS3A5018RSVR (U9) switch is used for SPI enable/disable. The EVM has 4 LEDs to indicate board power, on
or off, and some pre-defined PMIC GPOs status. The signals are listed in Table 3-8.
Table 3-8. EVM LED Indicators
LED Designator Indication
D2 LED is on when nINT is low.
D3 LED is on when EN_DRV is high.
D4 LED is on when nRSTOUT is low.
D5 EVM USB power indicator.
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4 Customization
The EVM, in conjunction with GUI tool, provides various degrees of customization. A couple of examples are
provided here which can be generalized to a number of functions.
4.1 Changing the Communication Interface
The default settings for communication with the PMIC is SPI. Changing to I2C requires a removal of jumpers
from J18, J24 as highlighted in red in Figure 4-1. At J18, the jumper on SPI_EN connects the microcontroller to
the SPI bus to which the PMIC is connected. The SPI does not have a device ID and therefore the chip select is
used to determine which PMIC receives and responds to commands on the SPI bus.
Figure 4-1. Interface Settings for I2C Communication
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5 Schematic, Layout, and Bill of Materials
Figure 5-1. Main Schematic Page
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Figure 5-2. MCU Schematic Page
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Figure 5-3. Layout Top, Layer 1
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Figure 5-4. Layout Ground, Layer 2
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Figure 5-5. Layout Signal, Layer 3
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Figure 5-6. Layout Signal, Layer 4
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Figure 5-7. Layout Ground, Layer 5
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Figure 5-8. Layout Bottom, Layer 6
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Table 5-1. Bill of Materials
Item# Designator Part Number Quantity Value Manufacturer Description Package Reference
1 PCB BMC085A 1 Any Printed Circuit Board
2 C1, C2, C3, C4, C111,
C116
GCM21BR71A106KE
22L
6 10uF MuRata CAP, CERM, 10 uF,
10 V, +/- 10%, X7R,
0805
0805
3 C5, C6 NFM18HC105C1C3D 2 Murata 3 Terminals Low
ESL Chip Multilayer
Ceramic Capacitors
for Automotive
0603
4 C7, C9, C110, C112 GCM155C71A474KE
36D
4 0.47uF MuRata CAP, CERM, 0.47 uF,
10 V,+/- 10%, X7S,
0402
0402
5 C8, C28, C31, C54,
C57, C61, C64, C68,
C71, C73, C77, C82,
C83, C92, C97, C113,
C114, C115, C118,
C119, C121
GCM188R70J225KE2
2D
21 2.2uF MuRata CAP, CERM, 2.2 uF,
6.3 V, +/- 10%, X7R,
AEC-Q200 Grade 1,
0603
0603
6 C11, C12, C13, C14,
C22, C30, C53, C56,
C60, C63, C67, C70,
C72, C74, C98, C99,
C101, C102, C105,
C108, C109, C117,
C120
GCM155R71C104KA
55D
23 0.1uF MuRata CAP, CERM, 0.1 uF,
16 V, +/- 10%, X7R,
0402
0402
7 C15, C42, C59, C66 GCM188D70J106ME
36D
4 Murata Chip Multilayer
Ceramic Capacitors
for Automotive
0603
8 C16, C17, C21, C35,
C43, C44, C45, C48,
C76, C85, C86, C90
GCM21BD70J226ME
36L
12 22uF MuRata CAP, CERM, 22 uF,
6.3 V, +/- 20%, X7T,
AEC-Q200 Grade 1,
0805
0805
9 C29, C55, C62, C69 GCM21BR70J106KE2
2L
4 10uF MuRata CAP, CERM, 10 uF,
6.3 V, +/- 10%, X7R,
AEC-Q200 Grade 1,
0805
0805
10 C32, C33, C34, C106,
C107
GCM31CR71A226KE
02L
5 22uF MuRata CAP, CERM, 22 uF,
10 V, +/- 10%, X7R,
AEC-Q200 Grade 1,
1206
1206
11 C47 UUD1V151MNL1GS 1 150uF Nichicon CAP, AL, 150 uF, 35
V, +/- 20%, 0.17 ohm,
SMD
8x10
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Table 5-1. Bill of Materials (continued)
Item# Designator Part Number Quantity Value Manufacturer Description Package Reference
12 C100 C0603C332K5RACTU 1 3300pF Kemet CAP, CERM, 3300 pF,
50 V, +/- 10%, X7R,
0603
0603
13 C103, C104 GCM1555C1H120JA1
6J
2 12pF MuRata CAP, CERM, 12
pF, 50 V,+/- 5%,
C0G/NP0, AEC-Q200
Grade 1, 0402
0402
14 D1 NSR05T40P2T5G 1 onsemi Diode Schottky 40 V
500mA (DC) Surface
Mount SOD-923
SOD-923
15 D2, D3, D4, D5 LB Q39G-L2N2-35-1 4 Blue OSRAM LED, Blue, SMD BLUE 0603 LED
16 H1, H2, H3, H4 FC2058-440-A 4 Fascomp SPACER
17 H5, H6, H7, H8 9900 4 Keystone MACHINE SCREW
PAN PHILLIPS 4-40
18 J3, J5, J6, J16 SMA-J-P-H-ST-TH1 4 Samtec SMA Jack, Straight,
50 Ohm, Gold, TH
TH, 5-Leads, Body
7x7mm
19 J4, J33 61300311121 2 Wurth Elektronik Header, 2.54 mm,
3x1, Gold, TH
Header, 2.54mm, 3x1,
TH
20 J7, J8, J10, J12, J14 1792863 5 Phoenix Contact Terminal Block, 5mm,
2x1, R/A, TH
Terminal Block, 5mm,
2x1, R/A, TH
21 J18, J19, J22, J23,
J24, J27
TSW-110-07-G-S 6 Samtec Header, 100mil, 10x1,
Gold, TH
10x1 Header
22 J20, J21, J25, J26 TSW-102-07-G-S 4 Samtec Header, 100mil, 2x1,
Gold, TH
2x1 Header
23 J28, J29 ESQ-111-14-T-S 2 Samtec Conn Elevated Socket
SKT 11 POS 2.54mm
Solder ST Thru-Hole
Tube
HDR11
24 J30 ESQ-108-14-T-S 1 Samtec Board-To-Board
Connector, Vertical,
ESQ Series, 8
Contacts, Receptacle,
2.54 mm, Through
Hole
HDR8
25 J31 12401610E4#2A 1 Amphenol Canada Receptacle, 0.5mm,
USB TYPE C, R/A,
SMT
Receptacle, 0.5mm,
USB TYPE C, R/A,
SMT
26 J32 FTSH-105-01-F-DV-K 1 Samtec Header (Shrouded),
1.27mm, 5x2, Gold,
SMT
Header(Shrouded),
1.27mm, 5x2, SMT
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Table 5-1. Bill of Materials (continued)
Item# Designator Part Number Quantity Value Manufacturer Description Package Reference
27 L1, L5, L7, L8 TFM160810ALTA33N
NTAA
4 0.033uH TDK Fixed Inductor
0.033uH 30% 4.7A
9mOhm 0603
0603
28 L2, L3, L4, L6 TFM322512ALMAR47
MTAA
4 470nH TDK Inductor, Thin Film,
470 nH, 5.3 A,
0.021 ohm, AEC-
Q200 Grade 0, SMD
TDK Inductor
29 Q1 CSD13381F4 1 12V Texas Instruments MOSFET, N-CH, 12
V, 2.1 A, YJC0003A
(PICOSTAR-3)
YJC0003A
30 R1, R3, R4, R6, R7,
R11, R13, R15, R17,
R43, R64, R80
CRCW04020000Z0E
D
12 0 Vishay-Dale RES, 0, 5%, 0.063 W,
AEC-Q200 Grade 0,
0402
0402
31 R2, R5, R8, R19 RMCF0402FT49R9 4 49.9 Stackpole Electronics
Inc
RES, 49.9, 1%, 0.063
W, AEC-Q200 Grade
0, 0402
0402
32 R9, R10, R20, R21,
R22, R23, R24, R25,
R26, R27, R28, R29,
R30, R34, R35, R44,
R45, R46, R47, R48,
R49, R55, R56, R57,
R58, R59, R60, R61,
R62, R66, R73, R75,
R76, R79
CRCW040210K0JNE
D
34 10k Vishay-Dale RES, 10 k, 5%, 0.063
W, AEC-Q200 Grade
0, 0402
0402
33 R12, R14, R16, R69,
R78
CRCW04021K20JNE
D
5 1.2k Vishay-Dale RES, 1.2 k, 5%, 0.063
W, AEC-Q200 Grade
0, 0402
0402
34 R18 CRCW0402240RJNE
D
1 240 Vishay-Dale RES, 240, 5%, 0.063
W, AEC-Q200 Grade
0, 0402
0402
35 R31, R70, R71, R74,
R77
CRCW04021K00JNE
D
5 1.0k Vishay-Dale RES, 1.0 k, 5%, 0.063
W, AEC-Q200 Grade
0, 0402
0402
36 R50, R72 CRCW0402200KJNE
D
2 200k Vishay-Dale RES, 200 k, 5%,
0.063 W, AEC-Q200
Grade 0, 0402
0402
37 R51, R52 CRCW04021M00JNE
D
2 1.0Meg Vishay-Dale RES, 1.0 M, 5%,
0.063 W, AEC-Q200
Grade 0, 0402
0402
38 R53 CRCW0402374KFKE
D
1 374k Vishay-Dale RES, 374 k, 1%,
0.063 W, AEC-Q200
Grade 0, 0402
0402
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20 LP876242-Q1 Evaluation Module SLVUC20A – MARCH 2021 – REVISED AUGUST 2022
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