Texas Instruments ADS7066EVM-PDK User manual

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ADS7066EVM-PDK Evaluation Module
User's Guide
SBAU342A–February 2020–Revised June 2020
ADS7066EVM-PDK Evaluation Module
The ADS7066 Evaluation Module (EVM) Performance Demonstration Kit (PDK) allows users to evaluate
the functionality of Texas Instruments' ADS7066 16-bit, eight-channel programmable successive
approximation register (SAR) analog-to-digital converter (ADC). The ADS7066 device showcases eight
inputs, each configurable to an analog input, digital output, or digital input. The device supports an internal
reference as well as operation with an external reference. This user’s guide describes both the hardware
platform showcasing the ADS7066 device and the graphical user interface (GUI) software used to
configure the various modes of operation of this device. It includes complete circuit descriptions,
schematic diagrams, and a bill of materials. The EVM-PDK eases the evaluation of the ADS7066 device
with hardware, software, and computer connectivity through the universal serial bus (USB) interface.
Figure 1. ADS7066EVM-PDK Assembled
The following related documents are available through the Texas Instruments website at www.ti.com.
Table 1. Related Documentation
Device Literature Number
ADS7066 SBAS928
REF6025 SBOS708B
OPA325 SBOS637D
TPS78001 SBVS083E

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Contents
1 Introduction ................................................................................................................... 3
2 ADS7066EVM Overview.................................................................................................... 4
3 ADS7066 EVM Initial Setup ................................................................................................ 6
4 Input Signal-Conditioning Block on the ADS7066EVM ............................................................... 19
5 Bill of Materials, Printed Circuit Board Layout, and Schematics..................................................... 20
List of Figures
1 ADS7066EVM-PDK Assembled ........................................................................................... 1
2 Channel 1 to Channel 6 Hardware Block Diagram...................................................................... 3
3 ADS7066 EVM Board....................................................................................................... 4
4 ADS7066EVM Lined up With PAMBoard (Left View)................................................................... 6
5 Browser Extension and TI Cloud Agent Installation..................................................................... 7
6 Hardware Connected Successfully to GUI ............................................................................... 7
7 ADS7066 GUI Landing Page............................................................................................... 8
8 ADS7066 Device Configuration Tab Displaying Mode Configuration ................................................ 9
9 Digital Input or Output Configurations................................................................................... 10
10 Averaging Page ............................................................................................................ 11
11 CRC Function Polynomial................................................................................................. 11
12 ADS7066 Data Capture Tab.............................................................................................. 12
13 Analog IP Data Capture Tab Options ................................................................................... 13
14 Time Domain Display...................................................................................................... 14
15 FFT Display................................................................................................................. 15
16 Histogram Graph Display ................................................................................................. 16
17 Digital Input Page Display................................................................................................. 17
18 ADS7066 Register Map Page ............................................................................................ 18
19 Channel 0 Input Signal Conditioning Block............................................................................. 19
20 ADS7066 EVM PCB Top Layer ......................................................................................... 21
21 ADS7066 EVM PCB Ground Layer...................................................................................... 21
22 ADS7066 EVM PCB Power Plane Layer ............................................................................... 21
23 ADS7066 EVM PCB Bottom Layer ...................................................................................... 21
24 ADS7066 EVM Schematic Diagram ..................................................................................... 22
List of Tables
1 Related Documentation..................................................................................................... 1
2 Channel Connections ....................................................................................................... 5
3 Bill of Materials ............................................................................................................. 20
Trademarks
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All other trademarks are the property of their respective owners.

ADS7066
CS
SCLK
SDI
SDO
Host MCU
AVDD
5.0 V
DVDD
3.3 V
330 pF
GND
AINx/GPIOx
1 k
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1 Introduction
The ADS7066 EVM is a fully-assembled evaluation platform designed to highlight the ADS7066 features
and various modes of operation that make this device suitable for ultra-low-power, small-size sensor
monitor applications.
The accompanying Precision ADC Motherboard (PAMBoard) development kit is used as a USB-to-PC
GUI communication bridge. This kit also serves as an example implementation of a master microcontroller
(MCU) to communicate with the ADS7066 device through a serial-peripheral interface (SPI).
NOTE: The ADS7066 EVM requires an external master controller to evaluate the ADS7066 device.
The PAMBoard is controlled by commands received from the ADS7066 GUI, and returns data to the GUI
for display and analysis. If the PAMBoard is not used, the EVM plug-in module format allows for an
alternative external host to communicate with the ADS7066 by easily connecting through a pin header.
The ADS7066 device incorporates all required circuitry and components with the following features:
• ADS7066 small WCSP footprint, eight-channel ADC
• Analog input driving a circuit available on channel 0
• Onboard reference, REF6025, to provide low-noise 2.5-V voltage and set the full scale range
• External power-supply connection available to provide DVDD power supply instead of the USB power
• Adjustable linear regulator, TPS78001, to generate stable output voltage to AVDD from the 5-V USB
power from the PAMBoard
• SPI for communication and configuration of modes
Figure 2 shows the ADS7066EVM architecture, identifying the key components and blocks previously
listed.
Figure 2. Channel 1 to Channel 6 Hardware Block Diagram

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2 ADS7066EVM Overview
This section describes various onboard components that are used to interface the analog input, general-
purpose inputs/outputs (GPIOs), digital interface, and provide power supply to the ADS7066 device.
Figure 3 shows an ADS7066 board overview.
Figure 3. ADS7066 EVM Board

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2.1 Connector for Channels
The ADS7066 device is designed for easy interface to an external, analog single-ended source, or to
GPIOs through a 100-mil header. Connector J5 provides a connection to the device channels. Table 2
lists the channel connections. The ADS7066 channel AIN0 has a buffered operational amplifier, TLV9061,
to drive the analog input. This is further explained in Section 4. Channels AIN1 through AIN6 have a
resistor and capacitor filter circuit to condition the analog input, as Figure 2 shows. Channel 7 is hardware-
configured to demonstrate GPIO functionality. GPIO7 has a resistor and light-emitting diode (LED) to
visibly demonstrate and monitor digital output channel state.
Table 2. Channel Connections
J5 Connector Pin Description
J5:1 Single-ended analog input with buffer
J5:2 Single-ended analog input or GPIO for channel 1 of the ADC
J5:5 Single-ended analog input or GPIO for channel 2 of the ADC
J5:6 Single-ended analog input or GPIO for channel 3 of the ADC
J5:7 Single-ended analog input or GPIO for channel 4 of the ADC
J5:8 Single-ended analog input or GPIO for channel 5 of the ADC
J5:11 Single-ended analog input or GPIO for channel 6 of the ADC
J5:12 LED GPO for channel 7 of the ADC
J5:3 and J5:4; J5:9 and J5:10 EVM ground
2.2 Digital Interface
As noted in Section 1, the ADS7066 interfaces with the PAMBoard, which in turn communicates with the
computer over the USB. The two devices on the EVM that communicate over SPI are the ADS7066 ADC
(U3) and the electrically erasable programmable read-only memory (EEPROM) (U4). The EEPROM is
preprogrammed with the information required to configure and initialize the ADS7066 platform. Once the
hardware is initialized, the EEPROM is no longer used.
2.3 ADS7066 PAMBoard Interface
The ADS7066 supports the digital SPI and functional modes as detailed in the ADS7066 Small, 8-
Channel, 16-Bit SAR ADC With GPIOs Data Sheet. The PAMBoard is capable of operating at a 3.3-V
logic level and is directly connected to the digital I/O lines of the ADC.
2.4 Power Supplies
The device supports a wide range of operation on its analog supply. The AVDD can operate from 3 V to
5.5 V. The DVDD operates from 1.65 V to 5.5 V, independent of the AVDD supply. A voltage regulator
available on the PAMBoard is used to supply 5V to AVDD, the DVDD is also provided by the PAMBoard
at 3.3V. There is an unpopulated option to use a low-dropout (LDO) regulator, for the TPS78001 for
AVDD. There is an onboard option to use an external power supply for DVDD through J2.

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3 ADS7066 EVM Initial Setup
The instructions to set up the ADS7066 for evaluation follow:
3.1 EVM Plug-In Hardware Setup Instructions
The EVM and PAMboard come packaged separately. For correct functionality, the boards need to be
installed properly.
To install the EVM to the PAMboard, stack the ADS7066EVM-PDK board on the PAMBoard. Make sure
the 20-pin connector (J1, J3) on the ADS7066 is mapped to left connector on the PAMBoard, and the
EVM connector (J4, J2) is mapped to right connector on the PAMBoard. The silk screen on the ADS7066
must match with the PAMBoard. Figure 4 shows the correct installation. The board headers must be flush.
Make sure the USB is not plugged in during this installation.
Connect the PAMBoard micro USB data port to an available USB port on the PC.
Figure 4. ADS7066EVM Lined up With PAMBoard (Left View)

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3.2 The ADS7066 GUI Online and TI Cloud Agent Application Installation
The following steps describe the ADS7066 GUI software installation:
1. Plug in the included micro USB to USB cable to the PAMBoard and a USB port on the computer,
respectively.
2. On the ADS7066EVM-PDK landing page, the software is available through a web-based GUI.
Connecting to the GUI may require login to a user account for access.
3. First-time users may be prompted to download and install the browser extension for Firefox™ or
Chrome™ and the TI Cloud Agent Application as Figure 5 shows. Do so if need be, this is a one time
download.
4. Refresh the GUI, if need be, and the GUI should connect to the hardware. A green signal will be
displayed, and at the left bottom, Hardware Connected shows.
Figure 5. Browser Extension and TI Cloud Agent Installation
Figure 6. Hardware Connected Successfully to GUI

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3.3 ADS7066 GUI Description
3.3.1 GUI Description
Figure 7 shows the GUI landing. This page provides a high-level overview of the ADS7066 device. The left
corner (highlighted by the green rectangle) shows the tabs to navigate through the GUI: home, function
configurations, data capture, and register map. When the ADS7066 is stacked on the PAMBoard and
connected to the PC via the micro USB cable, the GUI detects the EVM module by reading the onboard
EEPROM. When detected and connected, the GUI indicates this status as Connected. At the bottom left
corner of the GUI, there is an option to connect and disconnect the hardware from the GUI.
Figure 7. ADS7066 GUI Landing Page

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3.3.2 Functional Configuration Tab
As Figure 8 shows, the ADS7066 device configuration tab has two sections. The left-most section lists the
multiple functions the user can configure. These options enable the user to navigate through the various
functions of the ADS7066 in a structure and clear manner. The main section displays the configuration
options for each function.
The Device Configurations available are: Mode Configuration, Channel Selection, Averager, and Cyclic
Redundancy Check (CRC)
3.3.2.1 Mode Configuration
The ADS7066 can operate in three sampling modes. The mode configuration tab (Figure 8) allows the
user to select the device mode of operation.
The ADS7066 device has the following sampling modes:
•Manual Mode: Allows the external host processor to directly request and control when data is
sampled. The host provides SPI frames to control conversions and the captured data are returned over
the SPI bus after each conversion.
•Auto-Sequence Mode: The host can configure the device to scan through the enabled analog input
channels. The host must provide continuous clocks (SCLK) to the device to scan through the channels
and to read the data from the device. The MUX automatically switches through the predetermined
channel sequence, and the data conversion results are sent through the data bus.
•On-the-Fly Mode: The first 5 bits of SDI select the first channel to be sampled before the CS rising
edge. There is no latency between channel selection and ADC output data since the ADC samples the
next channel on the rising edge of CS.
The device powers up in manual mode and can be configured into any of the functional modes by writing
the configuration registers for the desired mode.
Figure 8. ADS7066 Device Configuration Tab Displaying Mode Configuration

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3.3.2.2 Channel Selection
The channel selection configuration option allows the user to configure each of the 8 channels. The
default configuration is analog input, but through the drop-down options, each channel can be configured
as a digital input or output. If using Auto Sequence mode, individual channels can be selected to be
included in the sequence, by checking Select for Auto-Seq. The EVM hardware has channel 7 hardwired
as a digital output with an LED connected to channel 7 to visually display a high or low digital output state.
To configure for a digital pin, change the Pin-Config drop down and select Digital. A second drop down
option will appear in line with the channel, I/O Config. This drop down option allows to select Input or
Output functionality. If output functionality is selected, as shown for channel 7 in Figure 9, configuration
options will appear in line with the channel. User will be able to select the Pin Value as high or low, and
the Pin Type as open drain or push pull. The EVM has an LED connected to channel 7 to display this
functionality; changing the Pin Value on channel 7 will turn on or off the LED (D2)
Through this document, as an example, channel 0 to 5 will be selected as analog inputs, channel 6 as a
digital input, and channel 7 as a digital output.
Figure 9. Digital Input or Output Configurations

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3.3.2.3 Averaging Function
Within the averaging function page, as Figure 10 shows, the oversampling ratio can be selected through
the drop-down option. The oversampling ratio applies to all analog input channels enabled.
Figure 10. Averaging Page
3.3.2.4 Cyclic Redundancy Check (CRC)
The ADS7066 device supports CRC to check the integrity of data transfer. When CRC is enabled, an 8-bit
output is appended to the end of the data transfer. The polynomial is calculated on the CRC-8-ATM as
shown in the page.
Figure 11. CRC Function Polynomial

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3.3.3 Data Capture Tab
The data capture tab displays the conversion results of the sampled data of the enabled channels. As
Figure 12 shows, clicking the red Capture button commences a sample data set. This page also displays
the sampling mode configuration used to capture the data. There is also a checkmark option to repeatedly
capture the sample size selected. This tab features two pages to display both the analog input and the
digital inputs:
•Analog Inputs: The sample and conversion results for each enabled analog input is displayed in this
page. The results can be displayed in three methods: time domain, Fast Fourier transform (FFT), and
histogram.
•Digital Inputs: The enabled digital input channels are displayed in this page.
See Section 3.3.3.1 for more information on capturing data.
Figure 12. ADS7066 Data Capture Tab

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3.3.3.1 Analog Input Data Capture Features
This section describes the features available in the Analog IP data capture display of the GUI. This page
auto updates to reflect the inputs in Section 3.3.2.2 based on the channel-specific configuration and
displays the configuration.
The analog input page provides an interface to the conversion results of the analog input channels.
Analog data is captured, as shown in Figure 13, by clicking on the Capture Data button. The analog
inputs page also provides user options for the following:
• Number of samples per the enabled analog input channels
• A drop-down option for increasing the oversampling rate
• A drop-down option to change the SCLK frequency
• A drop-down option for entering the desired sampling rate
• A drop-down option for selecting input channel displayed when in manual mode. When in
Autosequence, all channel selected would be displayed simultaneously
The Analog IP also displays a table with helpful attributes of the sampled data. The minimum and
maximum sample code are displayed, followed by the peak-to-peak range of the sampled data. The
standard deviation in codes, noise-free bits (NFB), and the effective resolution are also automatically
displayed after every data capture.
Within the Analog IP page, the captured samples can be displayed in three different formats:
• Time Domain
• Fast Fourier Transform (FFT)
• Histogram
Figure 13. Analog IP Data Capture Tab Options

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3.3.3.1.1 Time Domain Display
The time domain graph displays the conversion results of an analog input channel of the sampled data
set. The data captured is displayed as code value vs sample number. The number of samples can be
increased in the Samples/Channel drop-down menu. The data can also be displayed in the volt equivalent
of sample captured instead of the code value, based in the AVDD.
When in manual mode, the graph can only display one analog input conversion results at a time; the drop-
down option Input Channel allows changing which channel is displayed. When the device is operating in
auto-sequence mode, all the analog input channels selected will be displayed on the graph.
The data can also be exported by clicking the last icon at the right corner of the graph display.
Figure 14. Time Domain Display

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3.3.3.1.2 FFT
The Analog IP can display the FFT of the data captured. This will only display data if the analog input is
AC.
The FFT tab displays a table with the fundamental frequency of the input, followed by the noise floor level,
SNR, SFDR, THD, and SINAD. The effective number of bits (ENOB) and the number harmonics shown is
also displayed in the table.
NOTE: This image was taken using a incomplete version of the GUI. The device and EVM can
perform to data sheet specifications. The latest GUI version available will show correct
performance results
Figure 15. FFT Display

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3.3.3.1.3 Histogram Graph Display
The conversion results can also be shown as a histogram through the histogram tab (shown in Figure 16)
within the Analog IP page.
Figure 16. Histogram Graph Display

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3.3.4 Digital Input Page
The digital input page displays the enabled digital input channels as configured in Figure 9. As an example
channel 6 was configured as a digital input. All digital input channels enabled will be displayed on this
page and indicate the present logic state, respectively.
Figure 17. Digital Input Page Display

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3.4 Register Map
Figure 18 shows the register map for the ADS7066 device. On the top right corner are options to read
registers individually or read all the registers, or write an individual register. Users can choose to have the
register values modified in the GUI to be written on the device instantaneously by selecting the Immediate
Write option or later using the Deferred Write drop-down option. In the field view, the registers are broken
down into the configurable bits it controls. When making changes in the Field View, the bit being changed
is highlighted in yellow in the register map.
The register settings can also be saved in an external file to be loaded back into the GUI through the File
→Save Registers menu selection. This allows for different setting configurations to be saved and easily
implemented into the GUI by loading it back through the File →Load Registers menu item.
The register configurations can also be saved as a comma-separated values (CSV) file containing the
register address and content as configured in the GUI. This allows the user to configure the device easily
through the GUI as desired, and then export the respective register addresses and content to reference
when creating firmware.
Figure 18. ADS7066 Register Map Page

ADS7066
CS
SCLK
SDI
SDO
Host MCU
AVDD
5.0 V
DVDD
3.3 V
680 pF
107 
GND
+
±
GND
0 
R20
AIN0
AVDD
OPA325
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4 Input Signal-Conditioning Block on the ADS7066EVM
For applications where the input signal requires additional conditioning before the ADC input, the
ADS7066EVM has an onboard signal-conditioning path on channel 0. The input signal header, J5 is
connected to the amplifier input, OPA325. By default, this signal-conditioning block is populated on the
evaluation board as a non-inverting buffer using the OPA325 device. The board has a provision to bypass
the operational amplifier (U5) based on the signal conditioning requirement. To bypass this block, remove
the R21 0-Ωresistor and populate R26. See Section 5.3 for more details.
Figure 19. Channel 0 Input Signal Conditioning Block

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5 Bill of Materials, Printed Circuit Board Layout, and Schematics
This section contains the ADS7066 bill of materials (BOM), printed circuit board (PCB) layout, and schematics.
5.1 Bill of Materials
Table 3 lists the bill of materials (BOM) for the ADS7066EVM.
Table 3. Bill of Materials
Designator Quantity Description Manufacturer Part Number Manufacturer
C2 1 CAP, CERM, 1 µF, 25 V, ±10%, X7R, 0603 C0603C105K3RACTU Kemet
C4 1 CAP, CERM, 10 µF, 10 V, ±20%, X7R, 0805 C0805C106M8RACTU Kemet
C5, 1 CAP, CERM, 47 µF, 10 V, ±20%, X5R, 0805 GRM21BR61A476ME15L MuRata
C6, C7, C8, C9 4 CAP, CERM, 1 µF, 6.3 V, ±20%, X7R, 0402 GRM155R70J105MA12D MuRata
C10, C11, C12, C13, C14,
C15 6 CAP, CERM, 330 pF, 50 V, ±1%, C0G/NP0, 0402 GRM1555C1H331FA01J MuRata
C16, C18 2 CAP, CERM, 0.1 µF, 25 V, ±10%, X5R, 0603 CL10A104KA8NNNC Samsung Electro-Mechanics
C17 1 CAP, CERM, 680 pF, 25 V, ±5%, C0G/NP0, 0402 GRM1555C1E681JA01D MuRata
D2 1 LED, Red, SMD LTST-C150CKT Lite-On
J1, J3 2 Receptacle, 2.54 mm, 10 × 2, Tin, TH SSQ-110-03-T-D Samtec
J5 1 Header, 100 mil, 6 × 2, Tin, TH PEC06DAAN Sullins Connector Solutions
J6 1 Header, 100 mil, 2x1, Tin, TH SSQ-110-03-T-D Samtec
R1, R6,R7 3 RES, 0, 5%, 0.1 W, 0603 RC0603JR-070RL Yageo
R4 1 RES, 0.22, 1%, 0.125 W, AEC-Q200 Grade 0, 0402 ERJ-2BQFR22X Panasonic
R5, R20, R21 3 RES, 0, 1%, 0.1 W, AEC-Q200 Grade 0, 0603 RMCF0603ZT0R00 Stackpole Electronics Inc
R9, R10, R11, R12, R13,
R14 6 RES, 1.00 kΩ, 1%, 0.1 W, 0402 ERJ-2RKF1001X Panasonic
R15, R16, R17, R18, R28 5 RES, 100 k, 1%, 0.063 W, AEC-Q200 Grade 0, 0402 CRCW0402100KFKED Vishay-Dale
R23, R24 2 RES, 10.0 kΩ, 1%, 0.063 W, 0402 RC0402FR-0710KL Yageo America
R25 1 RES, 2.20 kΩ, 1%, 0.1 W, 0603 RC0603FR-072K2L Yageo
R27 1 RES, 1.00 M, 1%, 0.1 W, 0402 ERJ-2RKF1004X Panasonic
R29 1 RES, 49.9, 1%, 0.063 W, AEC-Q200 Grade 0, 0402 CRCW040249R9FKED Vishay-Dale
TP4, TP5 2 Test Point, Multipurpose, Black, TH 5011 Keystone
U2 1 5 ppm/C High-Precision Voltage Reference with Integrated High-Bandwidth
Buffer, DGK0008A (VSSOP-8) REF6025IDGKR Texas Instruments
U3 1 Small, 8-Channel, 12-bit ADC with I2C Interface, GPIOs and CRC,
RTE0016C_WF (WQFN-16) ADS7066RTE Texas Instruments
U4 1 I2C BUS EEPROM (2-Wire), TSSOP-B8 BR24G32FVT-3AGE2 Texas Instruments
U5 1 CMOS Amplifier 1 Circuit Rail-to-Rail SOT-23-5 OPA325IDBVR Texas Instruments