Texas Instruments LMX2571EPEVM User manual

User’s Guide
LMX2571EPEVM Evaluation Instructions
ABSTRACT
The LMX2571EPEVM is designed to evaluate the performance of LMX2571-EP. This board consists of a
LMX2571-EP device.
The LMX2571-EP is a low-power, high-performance, wideband RF synthesizer that can generate any frequency
from 10 MHz to 1344 MHz. This synthesizer can also be used with an external VCO. The device runs from a
single 3.3-V supply and has integrated LDOs that eliminate the need for onboard low noise LDOs.
Except for the following components, this board is able to support extended temperature range testing.
• LED
• uWIRE socket
• Header and short
• Ribbon cable
Table of Contents
1 LMX2571EPEVM Evaluation Module.....................................................................................................................................3
1.1 Evaluation Module Contents.............................................................................................................................................. 3
1.2 Installing the EVM Software............................................................................................................................................... 3
1.3 Resources.......................................................................................................................................................................... 3
2 Setup........................................................................................................................................................................................4
2.1 Connection Diagram.......................................................................................................................................................... 4
2.2 Power Supply..................................................................................................................................................................... 4
2.3 Reference Clock.................................................................................................................................................................4
2.4 RF Output...........................................................................................................................................................................4
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2.5 Programming......................................................................................................................................................................4
2.6 Evaluation Software........................................................................................................................................................... 4
2.7 EVM Strap Options............................................................................................................................................................ 5
3 Typical Measurement..............................................................................................................................................................6
3.1 Default Configuration......................................................................................................................................................... 6
3.2 Additional Tests.................................................................................................................................................................. 7
4 Schematic................................................................................................................................................................................9
5 Board Construction.............................................................................................................................................................. 10
5.1 PCB Layer Stack-Up........................................................................................................................................................ 10
5.2 PCB Layout...................................................................................................................................................................... 10
6 Bill of Materials..................................................................................................................................................................... 13
7 Troubleshooting Guide.........................................................................................................................................................14
A Using Different Reference Clock........................................................................................................................................ 15
B Reference PRO..................................................................................................................................................................... 16
B.1 Output Frequency Selection............................................................................................................................................ 16
B.2 Output Format Selection..................................................................................................................................................16
B.3 Typical Output Characteristics......................................................................................................................................... 17
B.4 Firmware Update............................................................................................................................................................. 17
List of Figures
Figure 2-1. Connection Diagram..................................................................................................................................................4
Figure 2-2. Select Device in TICS Pro.........................................................................................................................................5
Figure 2-3. EVM Default Mode.................................................................................................................................................... 5
Figure 2-4. J11 Header................................................................................................................................................................ 5
Figure 2-5. J12 Header................................................................................................................................................................5
Figure 3-1. Loop Filter................................................................................................................................................................. 6
Figure 3-2. Default Output........................................................................................................................................................... 6
Figure 3-3. FSK PIN Mode Setting.............................................................................................................................................. 7
Figure 3-4. FSK PIN Mode.......................................................................................................................................................... 7
Figure 3-5. Readback Setting...................................................................................................................................................... 8
Figure 3-6. Register Readback....................................................................................................................................................8
Figure 4-1. LMX2571EPEVM Schematic.....................................................................................................................................9
Figure 5-1. PCB Layer Stack-Up............................................................................................................................................... 10
Figure 5-2. Top Layer.................................................................................................................................................................10
Figure 5-3. GND Layer...............................................................................................................................................................11
Figure 5-4. Signal GND Layer....................................................................................................................................................11
Figure 5-5. Bottom Layer........................................................................................................................................................... 12
Figure 7-1. Troubleshooting Guide............................................................................................................................................ 14
Figure A-1. Single-ended Input..................................................................................................................................................15
Figure A-2. Differential Input......................................................................................................................................................15
Figure A-3. Crystal Oscillator Input............................................................................................................................................15
Figure B-1. Output Termination Schematic................................................................................................................................17
Figure B-2. Default Output Phase Nosie................................................................................................................................... 17
Figure B-3. Default Output Waveform........................................................................................................................................17
Figure B-4. Firmware Requirement........................................................................................................................................... 18
Figure B-5. Firmware Loader.....................................................................................................................................................18
Figure B-6. BSL Button..............................................................................................................................................................18
Figure B-7. Update Firmware.................................................................................................................................................... 18
Figure B-8. Firmware Update Completed.................................................................................................................................. 19
Figure B-9. USB Communications.............................................................................................................................................19
List of Tables
Table 3-1. Loop Filter Configuration.............................................................................................................................................6
Table 3-2. FSK PIN Mode Example............................................................................................................................................. 7
Table 6-1. LMX2571EPEVM Bill of Materials.............................................................................................................................13
Table B-1. Reference PRO Output Frequency Selection...........................................................................................................16
Table B-2. Reference PRO Output Format Selection................................................................................................................ 16
Table B-3. Output Termination Configuration.............................................................................................................................16
Trademarks
All trademarks are the property of their respective owners.
Trademarks www.ti.com
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1 LMX2571EPEVM Evaluation Module
1.1 Evaluation Module Contents
The following is included in the package:
• One LMX2571EPEVM board (HSDC115-001).
• One Reference PRO board (SV601349).
• One USB cable.
• One 10-pin ribbon cable.
1.2 Installing the EVM Software
The evaluation requires the following hardware and software:
• A DC power supply
• A spectrum analyzer or a signal analyzer
• A PC running Windows 7 or more recent version
• An oscilloscope (optional)
• A high quality signal generator
• Texas Instruments Clocks and Synthesizers TICS Pro software
• Texas Instruments PLLatinum Simulator Tool (optional)
1.3 Resources
Related evaluation and development resources include:
•LMX2571-EP data sheet
•TICS Pro software
•PLLatinum Simulator Tool (PLL Sim)
•Reference PRO design file
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2 Setup
2.1 Connection Diagram
Figure 2-1. Connection Diagram
2.2 Power Supply
Apply 3.3 V to the J9 header. The acceptable supply voltage range is 3.2 V to 3.4 V. The maximum current
consumption in the most extreme configuration must not exceed 100 mA.
2.3 Reference Clock
Connect OSCINP SMA connector with one of the outputs from Reference PRO. The EVM is configured for
single-ended input with OSCIN_P pin connected to OSCINP SMA connector and OSCIN_N pin floating. If
required, the EVM can be modified to operate with different clock source in different configuration, see Appendix
A for details.
Terminate the unused output of the Reference PRO board with a 50-Ω resistor or SMA load. By default, the
output clock from Reference PRO is a 100-MHz LVPECL clock. Appendix B has the details of Reference PRO.
2.4 RF Output
Connect RFOUTRX SMA connector to a signal analyzer. Output frequency is 480 MHz and the amplitude is
about +1 dBm.
By default the evaluation software, TICS Pro, has RFOUTTX power down. This SMA connectors could be left
open.
2.5 Programming
Connect ribbon cable from Reference PRO to LMX2571EPEVM.
Connect USB cable from a PC to USB port in Reference PRO. This provides power supply to Reference PRO
board and communication with TICS Pro. A firmware update may be required, see Appendix B for details.
2.6 Evaluation Software
Download and install TICS Pro to a PC. Run the software and follow the following steps to get started.
Setup www.ti.com
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1. Go to Select Device → PLL + VCO → LMX2571 → LMX2571EP.
Figure 2-2. Select Device in TICS Pro
2. Go to Default Configuration → EVM Default Mode.
Figure 2-3. EVM Default Mode
2.7 EVM Strap Options
2.7.1 J11 Header
Pin 2 of J11 is connected to the VCPEXT pin. In synthesizer mode, put a short to the 3.3-V position. Put the
short to the 5-V position in PLL mode and provide a 5-V supply to the reserved pads for the 5-V SMA connector.
Figure 2-4. J11 Header
2.7.2 J12 Header
Pin 2 of J12 is connected to the CE pin. Put a short to the HW position, this will connect the CE pin to 3V3
through resistor R38. If the short is placed in the SW position, the status of CE pin is configurable through TICS
Pro.
Figure 2-5. J12 Header
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3 Typical Measurement
3.1 Default Configuration
3.1.1 Loop Filter
The parameters for the loop filter are shown in Table 3-1.
Table 3-1. Loop Filter Configuration
PARAMETER VALUE
VCO frequency Designed for 4.8 GHz, but works
over the whole frequency range
VCO gain 56 MHz/V
Effective charge pump gain 2500 µA
Phase detector frequency 80 MHz
Loop bandwidth 205 kHz
Phase margin 40 degrees
C1_LF 390 pF
C2_LF 4.7 nF
R2_LF 680 Ω
R3_LF = R4_LF (Internal) 800 Ω
C3_LF (Internal) 50 pF
C4_LF (Internal) 100 pF
Figure 3-1. Loop Filter
3.1.2 Typical Output
1. Follow Section 2 to set up the evaluation.
2. Click Write All Registers to write all the registers to LMX2571-EP. The default output is 480 MHz.
Figure 3-2. Default Output
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3.2 Additional Tests
3.2.1 FSK Modulation
Direct digital FSK modulation is supported in LMX2571. FSK PIN mode supports discrete 2-, 4-, or 8-level FSK
modulation while other FSK modes support arbitrary level FSK modulation. Table 3-2 is an FSK PIN mode
example.
Table 3-2. FSK PIN Mode Example
PARAMETER EXAMPLE VALUE
Phase detector frequency 80 MHz
CHDIV1 Divided by 4
CHDIV2 Divided by 1
PLL_DEN 224
Prescalar 2
Frequency deviation ±600 Hz; ±1800 Hz
Continue to toggle the FSK_D[1:0] and FSK_DV pins, the output is a discrete 4-level FSK modulated signal.
Figure 3-3. FSK PIN Mode Setting
Figure 3-4. FSK PIN Mode
3.2.2 Register Readback
To read back the written register values, use the following steps:
1. From the TICS Pro, set SDO_LD_SEL to Lock detect output.
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Figure 3-5. Readback Setting
2. Click the Register Name that you want to read back.
3. Click the Read Register button to read back the register value.
Figure 3-6. Register Readback
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4 Schematic
Figure 4-1. LMX2571EPEVM Schematic
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5 Board Construction
5.1 PCB Layer Stack-Up
The board is made on FR4 for the Prepreg and Core Layers. The top layer is 1 oz copper.
Figure 5-1. PCB Layer Stack-Up
5.2 PCB Layout
Figure 5-2. Top Layer
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Figure 5-3. GND Layer
Figure 5-4. Signal GND Layer
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Figure 5-5. Bottom Layer
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6 Bill of Materials
Table 6-1. LMX2571EPEVM Bill of Materials
DESIGNATOR QTY DESCRIPTION PART NUMBER MANUFACTURER
C1 1 CAP, CERM, 2.2 µF, 10 V, +/- 10%,
X5R, 0603
C0603C225K8PACTU Kemet
C1LF 1 CAP, CERM, 390 pF, 50 V, +/- 5%,
C0G/NP0, 0603
C0603C391J5GACTU Kemet
C2, C3, C4, C5, C6, C8,
C11, C23, C25
9 CAP, CERM, 0.1 µF, 16 V, +/- 10%,
X7R, 0603
885012206046 Wurth Elektronik
C2LF 1 CAP, CERM, 4700 pF, 50 V, +/- 10%,
X7R, 0603
885012206087 Wurth Elektronik
C7, C9, C10, C24, C26 5 CAP, CERM, 1 µF, 16 V, +/- 10%, X7R,
0603
885012206052 Wurth Elektronik
C14, C17 2 CAP, CERM, 1000 pF, 50 V,+/- 10%,
X7R, 0603
885012206083 Wurth Elektronik
D1 1 LED, Green, SMD LTST-C190GKT Lite-On
J1, J2, J4 3 Connector, End launch SMA, 50 ohm,
SMT
142-0701-851 Cinch Connectivity
J7 1 Header (shrouded), 100mil, 5x2, Gold,
SMT
52601-S10-8LF FCI
J8 1 Header, 100mil, 4x2, Gold, SMT 0015910080 Molex
J9 1 Header, 100mil, 2x1, Gold, TH TSW-102-07-G-S Samtec
J11, J12 2 Header, 100mil, 3x1, Gold, TH TSW-103-07-G-S Samtec
R1, R2, R3, R5, R6, R7,
R8, R20, R21
9 RES, 0, 5%, 0.1 W, AEC-Q200 Grade
0, 0603
CRCW06030000Z0EA Vishay-Dale
R2LF 1 RES, 680, 5%, 0.1 W, AEC-Q200
Grade 0, 0603
CRCW0603680RJNEA Vishay-Dale
R4, R10, R11, R13, R14 5 RES, 330, 5%, 0.1 W, AEC-Q200
Grade 0, 0603
CRCW0603330RJNEA Vishay-Dale
R9, R12 2 RES, 18, 5%, 0.1 W, AEC-Q200
Grade 0, 0603
CRCW060318R0JNEA Vishay-Dale
R26 1 RES, 49.9, 1%, 0.1 W, AEC-Q200
Grade 0, 0603
CRCW060349R9FKEA Vishay-Dale
R28, R29, R30, R31, R32,
R33, R34, R35, R36, R37,
R38
11 RES, 33, 5%, 0.1 W, AEC-Q200
Grade 0, 0603
CRCW060333R0JNEA Vishay-Dale
U1 1 LMX2571-EP Low Power Synthesizer
with FSK Modulation
LMX2571-EP Texas Instruments
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7 Troubleshooting Guide
If the EVM does not work as expected, use the Figure 7-1 to identify potential root causes. Consider the
following:
• Do not make modifications to the EVM or change the default settings until AFTER it is verified to be working.
• Register read back requires the correct software setup, See Section 3.2.2 for details.
• The POR current of the LMX2571EPEVM is approximately 30 mA.
• The power-down current of the LMX2571EPEVM is approximately 3 mA.
Figure 7-1. Troubleshooting Guide
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A Using Different Reference Clock
There are different options to provide a reference clock to LMX2571EPEVM. By default, the EVM is configured
for an external single-ended clock.
Figure A-1. Single-ended Input
Figure A-2. Differential Input
Figure A-3. Crystal Oscillator Input
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B Reference PRO
The Reference PRO board is used to program the LMX2571EPEVM and at the same time, provide a clean
reference clock to LMX2571EPEVM. The board has several control pins dedicated for control of output format,
output frequency, and output enable control. These control pins are configurable through the jumpers by
strapping the center pin to Vdd position or GND position. Connections from the Vdd position to the device
supply or from the GND position to the ground plane are connected by 1.5-kΩ resistors. By default, the board
is configured for 100-MHz LVPECL output. The power supply to Reference PRO is obtained from the PC that is
connecting to Reference PRO through the USB interface.
B.1 Output Frequency Selection
Jumpers FS1 and FS0 are used to set the output frequency.
Table B-1. Reference PRO Output Frequency Selection
FS1 FS0 OUTPUT FREQUENCY (MHz)
GND GND 100
GND NC 312.5
GND Vdd 125
NC GND 106.25
NC NC 156.25
NC Vdd 212.5
Vdd GND 62.5
B.2 Output Format Selection
The OE pin is used to enable or disable the output.
The OS pin is used to bias internal drivers and change the output format.
Table B-2. Reference PRO Output Format Selection
OE OS OUTPUT FORMAT
GND Don't Care Disabled
Vdd GND LVPECL
Vdd NC LVDS
Vdd Vdd HCSL
It is imperative to match the output termination passive components as shown in Table B-3.
Table B-3. Output Termination Configuration
OUTPUT FORMAT COUPLING COMPONENT VALUE
LVPECL
AC (Default configuration)
R15, R28 0 Ω
R26, R29 150 Ω
C24, C25 0.01 µF
R27, R30, R31 DNP
DC(1) R15, R28, C24, C25 0 Ω
R26, R27, R29, R30, R31 DNP
LVDS(2)
AC
R25, R27, R28, R30 0 Ω
R31 100 Ω
C24, C25 0.01 µF
R26, R29 DNP
DC
R25, R27, R28, R30, C24, C25 0 Ω
R31 100 Ω
R26, R29 DNP
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Table B-3. Output Termination Configuration (continued)
OUTPUT FORMAT COUPLING COMPONENT VALUE
HCSL
AC
R25, R28 0 Ω
R26, R29 50 Ω
C24, C25 0.01 µF
R27, R30, R31 DNP
DC
R25, R28, C24, C25 0 Ω
R26, R29 50 Ω
R27, R30, R31 DNP
(1) 50-Ω to VCC – 2-V termination is required on receiver.
(2) 100-Ω differential termination (R31) is provided onboard. Removing this termination is possible if the differential termination is available
on the receiver.
Figure B-1. Output Termination Schematic
B.3 Typical Output Characteristics
Figure B-2. Default Output Phase Nosie Figure B-3. Default Output Waveform
B.4 Firmware Update
Usually when the Reference PRO board is used at the first time, TICS Pro will request for a firmware update.
Simply follow the pop-up instructions to complete the update. This is necessary to ensure that the USB
connection between the PC and the Reference PRO board is properly setup, otherwise the programming to
LMX2571EPEVM will not be successful.
1. When you see this message, click the OK button.
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Figure B-4. Firmware Requirement
2. Next, follow the on-screen procedure.
Figure B-5. Firmware Loader
3. The BSL button is located next to the USB connector.
Figure B-6. BSL Button
4. Follow the on-screen procedure until the below screen is pop-up.
Figure B-7. Update Firmware
5. Click the Upgrade Firmware button, the firmware will be upgrading. Click the Close button after the upgrade
is complete.
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Figure B-8. Firmware Update Completed
6. Check the USB connection in TICS Pro by clicking USB communications → Interface. Make sure the USB
Connected button is now green.
Figure B-9. USB Communications
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STANDARD TERMS FOR EVALUATION MODULES
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evaluation, experimentation, or scientific analysis of TI semiconductors products. EVMs have no direct function and are not
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clarification, any software or software tools provided with the EVM (“Software”) shall not be subject to the terms and conditions
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or otherwise distributed for commercial purposes by Users, in whole or in part, or used in any finished product or production
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2Limited Warranty and Related Remedies/Disclaimers:
2.1 These terms do not apply to Software. The warranty, if any, for Software is covered in the applicable Software License
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2.2 TI warrants that the TI EVM will conform to TI's published specifications for ninety (90) days after the date TI delivers such EVM
to User. Notwithstanding the foregoing, TI shall not be liable for a nonconforming EVM if (a) the nonconformity was caused by
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warranty period.
WARNING
Evaluation Kits are intended solely for use by technically qualified,
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and application risks associated with handling electrical mechanical
components, systems, and subsystems.
User shall operate the Evaluation Kit within TI’s recommended
guidelines and any applicable legal or environmental requirements
as well as reasonable and customary safeguards. Failure to set up
and/or operate the Evaluation Kit within TI’s recommended
guidelines may result in personal injury or death or property
damage. Proper set up entails following TI’s instructions for
electrical ratings of interface circuits such as input, output and
electrical loads.
NOTE:
EXPOSURE TO ELECTROSTATIC DISCHARGE (ESD) MAY CAUSE DEGREDATION OR FAILURE OF THE EVALUATION
KIT; TI RECOMMENDS STORAGE OF THE EVALUATION KIT IN A PROTECTIVE ESD BAG.