Texas Instruments LSF010XEVM-001 User manual

User's Guide
SDLU003A–July 2014–Revised June 2015
LSF010XEVM-001
This document is the user's guide for the LSF010XEVM-001 Evaluation Module (EVM). The EVM allows
for evaluation of the different ways that the LSF devices can be used to translate voltages between 1 V
and 5.5 V.
Contents
1 About This Manual........................................................................................................... 2
2 Information About Cautions and Warnings............................................................................... 2
3 Items Required for Operation .............................................................................................. 2
4 Introduction ................................................................................................................... 2
5 Setup .......................................................................................................................... 3
5.1 General Rules for Good Signal Integrity......................................................................... 3
6 Schematic..................................................................................................................... 6
6.1 Board Schematics and Pin Layout ............................................................................... 6
7 PCB Board Layout ......................................................................................................... 10
8 Bill of Materials (BOM)..................................................................................................... 11
List of Figures
1 EVM Board ................................................................................................................... 3
2 Pull-up Resistors on VAPU and VBPU (200kΩintegrated within LSF0204 device)................................ 4
3 Open Collector Input Control Circuit ...................................................................................... 5
4 LSF0101 Schematic......................................................................................................... 6
5 LSF0102 Schematic......................................................................................................... 7
6 LSF0108 Schematic......................................................................................................... 8
7 LSF0204 Schematic......................................................................................................... 9
8 PCB Layer 1 (Top Layer).................................................................................................. 10
9 PCB (Bottom Layer)........................................................................................................ 10
10 BOM.......................................................................................................................... 11
List of Tables
1 LSF0101 ...................................................................................................................... 6
2 LSF0102 ...................................................................................................................... 7
3 LSF0108 ...................................................................................................................... 8
4 LSF0204 ...................................................................................................................... 9
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About This Manual www.ti.com
1 About This Manual
This user’s guide describes the LSF010XEVM-001. This guide contains an introduction, setup instructions,
the EVM schematic, top and bottom printed-circuit-board (PCB) layouts, and a bill of materials (BOM).
2 Information About Cautions and Warnings
The information in a caution or a warning is provided for your protection. Read each caution and warning
carefully.
CAUTION
This EVM contains components that can potentially be damaged by
electrostatic discharge. Always transport and store the EVM in its supplied ESD
bag when not in use. Handle using an antistatic wristband. Operate on an
antistatic work surface. For more information on proper handling, see the
Electrostatic Discharge (ESD) application note (SSYA008).
3 Items Required for Operation
• Volt meter
• Oscilloscope
• Square wave signal source
4 Introduction
The LSF010XEVM-001 is an EVM board that contains 4 LSF voltage clamp translators: 1bit, 2-bit, 4-bit,
and 8 bit. These translators are bi-directional and only the LSF0204 requires a control pin. They can
accept voltages up to 5.5 V on the inputs and the output will be equal to the VrefA voltage. Once the
output reaches the VrefA level it can then be pulled to any other level between VrefA and 5.5 V. When
using multi-bit LSF devices you can have many different levels of voltage translation on the same part.
They can translate at medium to high speeds up to 100 MHz and cover these common voltage nodes and
anything in between (1 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V, and 5 V). These devices act like a switch when
the input is between GND and Vref A and will have FET switch type characteristics such as speeds up to
200 MHz when translating down. Then the I/Os can be pulled up to any voltage between VrefA and 5.5 V.
The maximum speed will then be limited by the size of the pull-up resistor and speeds up to 100 MHz can
be achieved when translating up.
The LSF010XEVM-001 EVM allows simplified evaluation and prototyping without the need for full board
development. This EVM provides peripheral header style pads for probing and signal connection to each
device pin and can be plugged into any prototype board with DIP header spacing. The boards are scored
so they can easily be broken apart.
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www.ti.com Setup
Figure 1. EVM Board
5 Setup
This section describes the setup and connections of the EVM boards and describes how to set up the
boards for voltage translations in either up or down direction.
5.1 General Rules for Good Signal Integrity
Ensure that Vref_A , Vref_B and GND are all connected and configured properly. There should be a
bypass capacitor on Vref_B (0.1 µF). When connecting signals, minimize the connection length and keep
GND leads short when probing. This will ensure minimal capacitive, resistive and inductive loading caused
by the connection and connector. For more device information please see the LSF0101, LSF0102,
LSF0204, and LSF0108 device datasheet.
5.1.1 VCC and GND Connections
Vref_B is considered VCC or device power. It will need to be 0.8 V greater than Vref_A. Vref_A will be the
lowest voltage that the part can translate down to.
GND is connected to pin 1 of P2 (LSF0101), Pin 1 of P4 (LSF0102), Pin 1 of P6 (LSF0108), and Pin 1 of
P8 (LSF0204). See connector pin locations in Figure 1 .
5.1.2 Translation Connections
On each board there will be a VAPU and a VBPU connection. These are the pull-up voltages that
correspond to the voltage being translated. These pull-up voltages must be between or equal to VrefA and
VrefB.
Some of the I/O pins on the LSF0108 will not have pull-up resistors. This will allow the use of different
pull-up resistor values and voltages on the A or B side. The A and B pins can be pulled to different levels
on each pin demonstrating that the part can translate many different voltage levels at the same time. (The
pull-up resistors installed on the boards are 301 Ω)
The following are examples of how the parts can be set up:
Each of these tests can be performed on any of the boards.
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Setup www.ti.com
NOTE: The LSF0101 and LSF0102 have all their pins connected to pull-up resistors on the EVM.
The A and B pins without pull-up resistors on the LSF0108 are the only pins that can be
pulled down.
Test examples
There can be multiple types of tests performed on each board. The drawing shows A as the input and B
as the output; however, it can work either direction. The output on Aside or Bside will be limited to VrefA
for a high level. Either side can then be pulled to any level between VrefA and 5.5 V. This allows up
translation, down translation or any combination. The signals can go in both directions without the need for
a direction pin.
Example 1 no pull-up
With no pull-up on either side (don’t connect VAPU or VBPU), you will be able to translate down to VrefA
going either direction. The input can be 0 V to 5.5 V and the output will be 0 V to VrefA. Either A-side or
B-side can be the input. This method can be used for down translation.
Example 2 with pull-up
By connecting VAPU or VBPU, you can pull the A or B side to any level between VrefA and 5.5 V. This
method can be used for up translation. By connecting the outputs to multiple pull-up levels you are able to
translate to a variety of different voltage nodes using a single part. Testing the part using multiple pull-up
voltages can only be done on the LSF0108 or LSF0204. The first four I/O’s will be tied to the same pull-up
voltage on the EVM. (VAPU or VBPU) The remaining I/Os can be connected to external pullup resistors
and different pull-up voltages.
Example 3 with pull-down
A pull-down to GND can also be used which will give the output value of Vref_A. This is sometimes used
to help with noise. If VREFA is the voltage that you are translating to then the pull-up can be tied to
VREFA for another way to reduce noise.
Example 4 with open drain part (Figure 3)
This configuration allows you to control the input level with Vref. Using an open drain part on the input side
will allow VrefA to control the input level. VBPU will control the output level of the LSF. Do not connect
anything to VAPU. You can put in a 0 V to 5 V signal into the open drain part, a 2 V signal on Vref, and a
3.3 V signal on VBPU.
This will then translate from 5 V to 2 V on Abus and then to 3.3 V on B bus.
Figure 2. Pull-up Resistors on VAPU and VBPU (200kΩintegrated within LSF0204 device)
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Figure 3. Open Collector Input Control Circuit
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Schematic www.ti.com
6 Schematic
The circuit diagrams in Figure 4 to Figure 7 show the schematics for the LSF010XEVM-001:
6.1 Board Schematics and Pin Layout
Figure 4. LSF0101 Schematic
Table 1. LSF0101
P1 Pin Out P2 Pin Out
1 Power pin 1 GND
(Connect high-
side supply here)
2 Vref_A 2 Vref_B
3 VAPU A side pull- 3 VBPU B side pull-up
up
4 A1 signal 4 B1 signal
5 NC 5 NC
6 NC 6 NC
7 NC 7 NC
8 NC 8 NC
9 NC 9 NC
10 NC 10 NC
11 NC 11 NC
12 NC 12 NC
13 NC 13 NC
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Figure 5. LSF0102 Schematic
Table 2. LSF0102
P3 Pin out P4
1 Power pin (Connect 1 GND
high-side supply here)
2 Vref_A 2 Vref_B
3 VAPU A side pull-up 3 VBPU B side pull-up
4 A1 signal 4 B1 signal
5 A2 signal 5 B2 signal
6 NC 6 NC
7 NC 7 NC
8 NC 8 NC
9 NC 9 NC
10 NC 10 NC
11 NC 11 NC
12 NC 12 NC
13 NC 13 NC
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Schematic www.ti.com
Figure 6. LSF0108 Schematic
Table 3. LSF0108
P5 Pin Out P6 Pin Out
1 Power pin (Connect high-side 1 GND
supply here)
2 Vref_A 2 Vref_B
3 VAPU A side pull-up 3 VBPU B side pull-up
4 A1 signal 4 B1 signal
5 A2 signal 5 B2 signal
6 A3 signal 6 B3 signal
7 A4 signal 7 B4 signal
8 A5 signal 8 A5 signal
9 A6 signal 9 A6 signal
10 A7 signal 10 A7 signal
11 A8 signal 11 A8 signal
12 NC 12 NC
13 NC 13 NC
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Figure 7. LSF0204 Schematic
Table 4. LSF0204
P5 Pin Out P6 Pin Out
1 Power pin (Connect high-side 1 GND
supply here)
2 Vref_A 2 Power pin (Connect high-side
supply here)
3 VAPU A side pull-up 3 VBPU B side pull-up
4 A1 signal 4 B1 signal
5 A2 signal 5 B2 signal
6 A3 signal 6 B3 signal
7 A4 signal 7 B4 signal
8 NC 8 EN pin
9 NC 9 NC
10 NC 10 NC
11 NC 11 NC
12 NC 12 NC
13 NC 13 NC
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PCB Board Layout www.ti.com
7 PCB Board Layout
Figure 8 and Figure 9 illustrate the PCB layout.
Figure 8. PCB Layer 1 (Top Layer)
Figure 9. PCB (Bottom Layer)
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