Texas Instruments MSP430FR58 Series User manual

MSP430FR58xx, MSP430FR59xx, and
MSP430FR6xx Family
User's Guide
Literature Number: SLAU367P
October 2012–Revised April 2020

2SLAU367P–October 2012–Revised April 2020
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Contents
Contents
Preface....................................................................................................................................... 45
1 System Resets, Interrupts, and Operating Modes, System Control Module (SYS)....................... 47
1.1 System Control Module (SYS) Introduction ............................................................................ 48
1.2 System Reset and Initialization........................................................................................... 48
1.2.1 Device Initial Conditions After System Reset.................................................................. 50
1.3 Interrupts .................................................................................................................... 50
1.3.1 (Non)Maskable Interrupts (NMIs) ............................................................................... 51
1.3.2 SNMI Timing ....................................................................................................... 51
1.3.3 Maskable Interrupts............................................................................................... 51
1.3.4 Interrupt Processing............................................................................................... 52
1.3.5 Interrupt Nesting................................................................................................... 53
1.3.6 Interrupt Vectors................................................................................................... 53
1.3.7 SYS Interrupt Vector Generators................................................................................ 54
1.4 Operating Modes........................................................................................................... 56
1.4.1 Low-Power Modes and Clock Requests ....................................................................... 58
1.4.2 Entering and Exiting Low-Power Modes LPM0 Through LPM4............................................. 59
1.4.3 Low-Power Modes LPM3.5 and LPM4.5 (LPMx.5) ........................................................... 59
1.5 Principles for Low-Power Applications .................................................................................. 61
1.6 Connection of Unused Pins............................................................................................... 62
1.7 Reset Pin (RST/NMI) Configuration ..................................................................................... 62
1.8 Configuring JTAG Pins .................................................................................................... 62
1.9 Vacant Memory Space .................................................................................................... 63
1.10 Boot Code................................................................................................................... 63
1.11 Bootloader (BSL)........................................................................................................... 63
1.12 JTAG Mailbox (JMB) System ............................................................................................ 63
1.12.1 JMB Configuration ............................................................................................... 64
1.12.2 JMBOUT0 and JMBOUT1 Outgoing Mailbox................................................................. 64
1.12.3 JMBIN0 and JMBIN1 Incoming Mailbox....................................................................... 64
1.12.4 JMB NMI Usage.................................................................................................. 64
1.13 JTAG and SBW Lock Mechanism Using the Electronic Fuse........................................................ 64
1.13.1 JTAG and SBW Lock Without Password ..................................................................... 65
1.13.2 JTAG and SBW Lock With Password ......................................................................... 65
1.14 Device Descriptor Table................................................................................................... 65
1.14.1 Identifying Device Type.......................................................................................... 66
1.14.2 TLV Descriptors .................................................................................................. 67
1.14.3 Calibration Values................................................................................................ 68
1.15 SFR Registers .............................................................................................................. 72
1.15.1 SFRIE1 Register ................................................................................................. 73
1.15.2 SFRIFG1 Register ............................................................................................... 74
1.15.3 SFRRPCR Register.............................................................................................. 75
1.16 SYS Registers .............................................................................................................. 76
1.16.1 SYSCTL Register ................................................................................................ 77
1.16.2 SYSJMBC Register.............................................................................................. 78
1.16.3 SYSJMBI0 Register.............................................................................................. 79
1.16.4 SYSJMBI1 Register.............................................................................................. 79

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1.16.5 SYSJMBO0 Register ............................................................................................ 80
1.16.6 SYSJMBO1 Register ............................................................................................ 80
1.16.7 SYSUNIV Register............................................................................................... 81
1.16.8 SYSSNIV Register ............................................................................................... 81
1.16.9 SYSRSTIV Register ............................................................................................. 82
2 Power Management Module (PMM) and Supply Voltage Supervisor (SVS)................................. 83
2.1 Power Management Module (PMM) Introduction ...................................................................... 84
2.2 PMM Operation............................................................................................................. 85
2.2.1 VCORE and the Regulator .......................................................................................... 85
2.2.2 Supply Voltage Supervisor....................................................................................... 85
2.2.3 Supply Voltage Supervisor - Power-Up ........................................................................ 86
2.2.4 LPM3.5 and LPM4.5.............................................................................................. 86
2.2.5 Brownout Reset (BOR)........................................................................................... 86
2.2.6 RST/NMI............................................................................................................ 87
2.2.7 PMM Interrupts .................................................................................................... 87
2.2.8 Port I/O Control.................................................................................................... 87
2.3 PMM Registers ............................................................................................................. 88
2.3.1 PMMCTL0 Register (offset = 00h) [reset = 9640h] ........................................................... 89
2.3.2 PMMCTL1 Register (offset = 02h) [reset = 9600h] ........................................................... 90
2.3.3 PMMIFG Register (offset = 0Ah) [reset = 0000h]............................................................. 91
2.3.4 PM5CTL0 Register (offset = 10h) [reset = 0001h]............................................................ 92
3 Clock System (CS) Module .................................................................................................. 93
3.1 Clock System Introduction ................................................................................................ 94
3.2 Clock System Operation................................................................................................... 96
3.2.1 CS Module Features for Low-Power Applications ............................................................ 96
3.2.2 LFXT Oscillator .................................................................................................... 96
3.2.3 HFXT Oscillator.................................................................................................... 97
3.2.4 Internal Very-Low-Power Low-Frequency Oscillator (VLO).................................................. 98
3.2.5 Module Oscillator (MODOSC) ................................................................................... 98
3.2.6 Digitally Controlled Oscillator (DCO)............................................................................ 98
3.2.7 Operation From Low-Power Modes, Requested by Peripheral Modules .................................. 99
3.2.8 CS Module Fail-Safe Operation................................................................................ 100
3.2.9 Synchronization of Clock Signals.............................................................................. 102
3.3 MemoryMap Registers................................................................................................... 103
3.3.1 CTL0 Register (Offset = 0h) [reset = 9600h]................................................................. 104
3.3.2 CTL1 Register (Offset = 2h) [reset = Ch]..................................................................... 105
3.3.3 CTL2 Register (Offset = 4h) [reset = 33h].................................................................... 106
3.3.4 CTL3 Register (Offset = 6h) [reset = 33h].................................................................... 107
3.3.5 CTL4 Register (Offset = 8h) [reset = CDC9h] ............................................................... 108
3.3.6 CTL5 Register (Offset = Ah) [reset = 00C5h]................................................................ 110
3.3.7 CTL6 Register (Offset = Ch) [reset = 7h]..................................................................... 111
4 CPUX .............................................................................................................................. 112
4.1 MSP430X CPU (CPUX) Introduction................................................................................... 113
4.2 Interrupts................................................................................................................... 115
4.3 CPU Registers ............................................................................................................ 116
4.3.1 Program Counter (PC) .......................................................................................... 116
4.3.2 Stack Pointer (SP)............................................................................................... 116
4.3.3 Status Register (SR) ............................................................................................ 117
4.3.4 Constant Generator Registers (CG1 and CG2) ............................................................. 119
4.3.5 General-Purpose Registers (R4 to R15)...................................................................... 120
4.4 Addressing Modes........................................................................................................ 122
4.4.1 Register Mode.................................................................................................... 123
4.4.2 Indexed Mode .................................................................................................... 124

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4.4.3 Symbolic Mode................................................................................................... 130
4.4.4 Absolute Mode ................................................................................................... 135
4.4.5 Indirect Register Mode.......................................................................................... 137
4.4.6 Indirect Autoincrement Mode................................................................................... 138
4.4.7 Immediate Mode ................................................................................................. 139
4.5 MSP430 and MSP430X Instructions................................................................................... 141
4.5.1 MSP430 Instructions ............................................................................................ 141
4.5.2 MSP430X Extended Instructions .............................................................................. 146
4.6 Instruction Set Description............................................................................................... 157
4.6.1 Extended Instruction Binary Descriptions..................................................................... 158
4.6.2 MSP430 Instructions ............................................................................................ 160
4.6.3 Extended Instructions ........................................................................................... 212
4.6.4 Address Instructions............................................................................................. 255
5 32-Bit Hardware Multiplier (MPY32)..................................................................................... 270
5.1 32-Bit Hardware Multiplier (MPY32) Introduction..................................................................... 271
5.2 MPY32 Operation......................................................................................................... 273
5.2.1 Operand Registers............................................................................................... 274
5.2.2 Result Registers ................................................................................................. 275
5.2.3 Software Examples.............................................................................................. 276
5.2.4 Fractional Numbers.............................................................................................. 277
5.2.5 Putting It All Together ........................................................................................... 280
5.2.6 Indirect Addressing of Result Registers ...................................................................... 283
5.2.7 Using Interrupts .................................................................................................. 283
5.2.8 Using DMA........................................................................................................ 284
5.3 MPY32 Registers ......................................................................................................... 285
5.3.1 MPY32CTL0 Register........................................................................................... 287
6 FRAM Controller Overview................................................................................................. 288
6.1 FRAM Controller Overview.............................................................................................. 288
7 FRAM Controller (FRCTL) .................................................................................................. 289
7.1 FRAM Introduction........................................................................................................ 290
7.2 FRAM Organization....................................................................................................... 290
7.3 FRCTL Module Operation ............................................................................................... 290
7.4 Programming FRAM Devices ........................................................................................... 291
7.4.1 Programming FRAM With JTAG or Spy-Bi-Wire ............................................................ 291
7.4.2 Programming FRAM With the Bootloader (BSL) ............................................................ 291
7.4.3 Programming FRAM With a Custom Solution ............................................................... 291
7.5 Wait State Control ........................................................................................................ 291
7.5.1 Wait State and Cache Hit....................................................................................... 292
7.6 FRAM ECC ................................................................................................................ 292
7.7 FRAM Write Back ........................................................................................................ 292
7.8 FRAM Power Control..................................................................................................... 292
7.9 FRAM Cache.............................................................................................................. 293
7.10 FRCTL Registers ......................................................................................................... 294
7.10.1 FRCTL0 Register ............................................................................................... 295
7.10.2 GCCTL0 Register............................................................................................... 296
7.10.3 GCCTL1 Register............................................................................................... 297
8 FRAM Controller A (FRCTL_A) ........................................................................................... 298
8.1 FRAM Controller A (FRCTL_A) Introduction.......................................................................... 299
8.2 FRAM Controller A (FRCTL_A) Operation ............................................................................ 299
8.2.1 FRCTL_A Error Detection ...................................................................................... 299
8.2.2 Programming FRAM Memory Devices........................................................................ 300
8.2.3 Access Control................................................................................................... 300

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8.3 FRAM ECC ................................................................................................................ 302
8.4 FRAM Power Control..................................................................................................... 302
8.5 FRAM Cache.............................................................................................................. 303
8.6 FRCTL_A Registers...................................................................................................... 304
8.6.1 FRCTL0 Register (Offset = 0h) [reset = 9600h] ............................................................. 305
8.6.2 GCCTL0 Register (Offset = 4h) [reset = 4h] ................................................................. 307
8.6.3 GCCTL1 Register (Offset = 6h) [reset = 0h] ................................................................. 309
9 Memory Protection Unit (MPU) ........................................................................................... 311
9.1 Memory Protection Unit (MPU) Introduction .......................................................................... 312
9.2 MPU Segments ........................................................................................................... 313
9.2.1 Main Memory Segments........................................................................................ 313
9.2.2 IP Encapsulation Segment ..................................................................................... 314
9.2.3 Segment Border Setting ........................................................................................ 315
9.2.4 IP Encapsulation Border Settings.............................................................................. 316
9.2.5 Information Memory ............................................................................................. 317
9.3 MPU Access Management Settings.................................................................................... 317
9.4 MPU Violations............................................................................................................ 318
9.4.1 Interrupt Vector Table and Reset Vector ..................................................................... 318
9.4.2 Violation Handling ............................................................................................... 318
9.5 MPU Lock.................................................................................................................. 318
9.6 How to Enable MPU and IPE Segments .............................................................................. 318
9.6.1 IP Encapsulation (IPE) Instantiation Using IPE Signatures................................................ 319
9.6.2 IP Encapsulation Removal ..................................................................................... 320
9.7 MPU Registers............................................................................................................ 321
9.7.1 MPUCTL0 Register.............................................................................................. 322
9.7.2 MPUCTL1 Register.............................................................................................. 323
9.7.3 MPUSEGB2 Register ........................................................................................... 324
9.7.4 MPUSEGB1 Register ........................................................................................... 325
9.7.5 MPUSAM Register............................................................................................... 326
9.7.6 MPUIPC0 Register .............................................................................................. 328
9.7.7 MPUIPSEGB2 Register......................................................................................... 329
9.7.8 MPUIPSEGB1 Register......................................................................................... 330
10 RAM Controller (RAMCTL) ................................................................................................. 331
10.1 RAM Controller (RAMCTL) Introduction ............................................................................... 332
10.2 RAMCTL Operation....................................................................................................... 332
10.2.1 Considerations for Complete Power Down.................................................................. 332
10.2.2 DACCESSIE and DACCESSIFG Bits in RCCTL1 Register............................................... 332
10.3 RAMCTL Registers....................................................................................................... 334
10.3.1 CTL0 Register (Offset = 0h) [reset = 6900h]................................................................ 335
10.3.2 CTL1 Register (Offset = 2h) [reset = 0h] .................................................................... 337
11 DMA Controller................................................................................................................. 338
11.1 Direct Memory Access (DMA) Introduction............................................................................ 339
11.2 DMA Operation............................................................................................................ 341
11.2.1 DMA Addressing Modes....................................................................................... 341
11.2.2 DMA Transfer Modes .......................................................................................... 342
11.2.3 Initiating DMA Transfers ....................................................................................... 348
11.2.4 Halting Executing Instructions for DMA Transfers.......................................................... 349
11.2.5 Stopping DMA Transfers....................................................................................... 349
11.2.6 DMA Channel Priorities........................................................................................ 349
11.2.7 DMA Transfer Cycle Time..................................................................................... 350
11.2.8 Using DMA With System Interrupts .......................................................................... 350
11.2.9 DMA Controller Interrupts ..................................................................................... 350
11.2.10 Using the eUSCI_B I2C Module With the DMA Controller ............................................... 352

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11.2.11 Using ADC12 With the DMA Controller .................................................................... 352
11.3 DMA Registers............................................................................................................ 353
11.3.1 DMACTL0 Register............................................................................................. 355
11.3.2 DMACTL1 Register............................................................................................. 356
11.3.3 DMACTL2 Register............................................................................................. 357
11.3.4 DMACTL3 Register............................................................................................. 358
11.3.5 DMACTL4 Register............................................................................................. 359
11.3.6 DMAxCTL Register............................................................................................. 360
11.3.7 DMAxSA Register .............................................................................................. 362
11.3.8 DMAxDA Register .............................................................................................. 363
11.3.9 DMAxSZ Register............................................................................................... 364
11.3.10 DMAIV Register ............................................................................................... 365
12 Digital I/O......................................................................................................................... 366
12.1 Digital I/O Introduction ................................................................................................... 367
12.2 Digital I/O Operation...................................................................................................... 368
12.2.1 Input Registers (PxIN).......................................................................................... 368
12.2.2 Output Registers (PxOUT) .................................................................................... 368
12.2.3 Direction Registers (PxDIR)................................................................................... 368
12.2.4 Pullup or Pulldown Resistor Enable Registers (PxREN) .................................................. 368
12.2.5 Function Select Registers (PxSEL0, PxSEL1).............................................................. 369
12.2.6 Port Interrupts................................................................................................... 369
12.3 I/O Configuration.......................................................................................................... 371
12.3.1 Configuration After Reset...................................................................................... 371
12.3.2 Configuration of Unused Port Pins ........................................................................... 372
12.3.3 Configuration for LPMx.5 Low-Power Modes............................................................... 372
12.4 Digital I/O Registers ...................................................................................................... 374
12.4.1 PxIV Register.................................................................................................... 388
12.4.2 PxIN Register ................................................................................................... 389
12.4.3 PxOUT Register ................................................................................................ 389
12.4.4 PxDIR Register.................................................................................................. 389
12.4.5 PxREN Register ................................................................................................ 390
12.4.6 PxSEL0 Register................................................................................................ 390
12.4.7 PxSEL1 Register................................................................................................ 390
12.4.8 PxSELC Register ............................................................................................... 391
12.4.9 PxIES Register.................................................................................................. 391
12.4.10 PxIE Register .................................................................................................. 391
12.4.11 PxIFG Register ................................................................................................ 392
13 Capacitive Touch I/O......................................................................................................... 393
13.1 Capacitive Touch I/O Introduction...................................................................................... 394
13.2 Capacitive Touch I/O Operation ........................................................................................ 395
13.3 CapTouch Registers...................................................................................................... 396
13.3.1 CAPTIOxCTL Register (offset = 0Eh) [reset = 0000h]..................................................... 397
14 AES256 Accelerator .......................................................................................................... 398
14.1 AES Accelerator Introduction............................................................................................ 399
14.2 AES Accelerator Operation.............................................................................................. 400
14.2.1 Load the Key (128-Bit, 192-Bit, or 256-Bit Key Length) ................................................... 401
14.2.2 Load the Data (128-Bit State)................................................................................. 401
14.2.3 Read the Data (128-Bit State) ................................................................................ 402
14.2.4 Trigger an Encryption or Decryption ......................................................................... 402
14.2.5 Encryption ....................................................................................................... 403
14.2.6 Decryption ....................................................................................................... 404
14.2.7 Decryption Key Generation.................................................................................... 405

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14.2.8 AES Key Buffer ................................................................................................. 406
14.2.9 Using the AES Accelerator With Low-Power Modes....................................................... 406
14.2.10 AES Accelerator Interrupts................................................................................... 406
14.2.11 DMA Operation and Implementing Block Cipher Modes................................................. 406
14.3 AES Accelerator Registers .............................................................................................. 417
14.3.1 AESACTL0 Register............................................................................................ 418
14.3.2 AESACTL1 Register............................................................................................ 420
14.3.3 AESASTAT Register ........................................................................................... 421
14.3.4 AESAKEY Register............................................................................................. 422
14.3.5 AESADIN Register ............................................................................................. 423
14.3.6 AESADOUT Register .......................................................................................... 424
14.3.7 AESAXDIN Register............................................................................................ 425
14.3.8 AESAXIN Register.............................................................................................. 426
15 CRC Module..................................................................................................................... 427
15.1 Cyclic Redundancy Check (CRC) Module Introduction.............................................................. 428
15.2 CRC Standard and Bit Order............................................................................................ 428
15.3 CRC Checksum Generation............................................................................................. 429
15.3.1 CRC Implementation........................................................................................... 429
15.3.2 Assembler Examples........................................................................................... 430
15.4 CRC Registers ............................................................................................................ 432
15.4.1 CRCDI Register................................................................................................. 433
15.4.2 CRCDIRB Register............................................................................................. 433
15.4.3 CRCINIRES Register........................................................................................... 434
15.4.4 CRCRESR Register............................................................................................ 434
16 CRC32 Module.................................................................................................................. 435
16.1 Cyclic Redundancy Check (CRC32) Module Introduction........................................................... 436
16.2 CRC Checksum Generation............................................................................................. 436
16.2.1 CRC Standard and Bit Order.................................................................................. 437
16.2.2 CRC Implementation........................................................................................... 437
16.2.3 Assembler Examples........................................................................................... 437
16.3 CRC32 Register Descriptions........................................................................................... 439
16.3.1 CRC32 Registers ............................................................................................... 439
17 Low-Energy Accelerator (LEA) for Signal Processing ........................................................... 446
17.1 LEA Introduction .......................................................................................................... 447
17.2 LEA Operation............................................................................................................. 447
17.2.1 Use the LEA in Programs...................................................................................... 448
17.2.2 Where to Get the DSP Library................................................................................ 449
17.2.3 Where to Start................................................................................................... 449
17.3 LEA Registers............................................................................................................. 449
18 Ultrasonic Sensing Solution (USS, USS_A).......................................................................... 450
18.1 Introduction ................................................................................................................ 451
18.2 Operation of the USS Module........................................................................................... 452
18.2.1 Auto Mode and Register Mode ............................................................................... 454
18.2.2 Control Signals.................................................................................................. 455
18.3 Debug Features........................................................................................................... 457
19 Universal USS Power Supply (UUPS) .................................................................................. 458
19.1 Introduction ................................................................................................................ 459
19.2 USS Power-up Sequence ............................................................................................... 460
19.3 USS Power States........................................................................................................ 461
19.4 Interface to the ASQ (Acquisition Sequencer) ........................................................................ 463
19.4.1 Start New Measurements...................................................................................... 463
19.4.2 Stop Measurement Before Completion ..................................................................... 464

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19.4.3 USS Power State After Completion of Measurements .................................................... 465
19.4.4 UUPSCTL.USSPWRUP Bit and UUPSCTL.USS_BUSY Bit ............................................. 465
19.5 Interrupts................................................................................................................... 466
19.6 Debug Mode............................................................................................................... 466
19.7 UUPS Registers........................................................................................................... 467
19.7.1 UUPSIIDX Register (Offset = 0h) [reset = 0h].............................................................. 468
19.7.2 UUPSMIS Register (Offset = 2h) [reset = 0h]............................................................... 469
19.7.3 UUPSRIS Register (Offset = 4h) [reset = 0h]............................................................... 470
19.7.4 UUPSIMSC Register (Offset = 6h) [reset = 0h]............................................................. 471
19.7.5 UUPSICR Register (Offset = 8h) [reset = 0h]............................................................... 472
19.7.6 UUPSISR Register (Offset = Ah) [reset = 0h]............................................................... 473
19.7.7 UUPSDESCLO Register (Offset = Ch) [reset = 110h]..................................................... 474
19.7.8 UUPSDESCHI Register (Offset = Eh) [reset = BA10h].................................................... 475
19.7.9 UUPSCTL Register (Offset = 10h) [reset = 800h].......................................................... 476
20 High-Speed PLL (HSPLL)................................................................................................... 478
20.1 Introduction ................................................................................................................ 479
20.2 OSC Control Register (HSPLLUSSXTCTL)........................................................................... 480
20.2.1 OSCEN Bit....................................................................................................... 480
20.2.2 OSCTYPE Bit ................................................................................................... 480
20.2.3 OSCSTATE Bit ................................................................................................. 480
20.2.4 XTOUTOFF Bit.................................................................................................. 480
20.3 PLL Control (CTL) Register ............................................................................................. 481
20.3.1 PLLM[5:0] Bits................................................................................................... 481
20.3.2 PLLINFREQ Bit ................................................................................................ 481
20.3.3 PLL_LOCK Bit .................................................................................................. 481
20.3.4 USSXT Control Register....................................................................................... 481
20.4 Start-up Sequence of the USSXT Oscillator .......................................................................... 481
20.4.1 USSXT Start-up Behavior ..................................................................................... 482
20.5 Interrupts................................................................................................................... 482
20.6 HSPLL Registers.......................................................................................................... 483
20.6.1 HSPLLIIDX Register (Offset = 0h) [reset = 0h]............................................................. 484
20.6.2 HSPLLMIS Register (Offset = 2h) [reset = 0h] ............................................................. 485
20.6.3 HSPLLRIS Register (Offset = 4h) [reset = 0h].............................................................. 486
20.6.4 HSPLLIMSC Register (Offset = 6h) [reset = 0h]............................................................ 487
20.6.5 HSPLLICR Register (Offset = 8h) [reset = 0h].............................................................. 488
20.6.6 HSPLLISR Register (Offset = Ah) [reset = 0h] ............................................................. 489
20.6.7 HSPLLDESCLO Register (Offset = Ch) [reset = 110h].................................................... 490
20.6.8 HSPLLDESCHI Register (Offset = Eh) [reset = BD10h]................................................... 491
20.6.9 HSPLLCTL Register (Offset = 10h) [reset = 4000h] ....................................................... 492
20.6.10 HSPLLUSSXTLCTL Register (Offset = 12h) [reset = 100h]............................................. 494
21 Sequencer for Acquisition, Programmable Pulse Generator, and Physical Interface (SAPH,
SAPH_A).......................................................................................................................... 495
21.1 Introduction ................................................................................................................ 496
21.2 Programmable Pulse Generator (PPG or PPG_A) Block ........................................................... 497
21.2.1 Pulse Generation ............................................................................................... 498
21.2.2 Single Tone Generation........................................................................................ 498
21.2.3 Dual Tone Generation.......................................................................................... 499
21.2.4 Trill Tone Generation........................................................................................... 500
21.2.5 Multi Tone Generation ......................................................................................... 501
21.2.6 Excitation Pulse Frequency on PPG or PPG_A............................................................ 503
21.2.7 Extra Excitation Pulse Frequency on PPG_A............................................................... 503
21.2.8 Test Tone Generation.......................................................................................... 503
21.3 Physical Interface (PHY) Block ......................................................................................... 504

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21.3.1 Output Channels (CH0_OUT and CH1_OUT).............................................................. 504
21.3.2 Trim Registers for the Output Drivers and Termination Resistors ....................................... 505
21.3.3 Input Channels (CH0_IN and CH1_IN) ...................................................................... 506
21.3.4 External Bias (XPB0 and XPB1 on SAPH_A) .............................................................. 510
21.4 Acquisition Sequencer (ASQ)........................................................................................... 510
21.4.1 Time Counter ................................................................................................... 511
21.4.2 Six Time Mark Events ......................................................................................... 512
21.4.3 Triggering the ASQ............................................................................................. 512
21.4.4 Auto Mode and Register Mode ............................................................................... 513
21.5 Ultra-Low-Power Bias Mode............................................................................................. 514
21.6 Interrupts Triggers ....................................................................................................... 515
21.7 DMA Triggers ............................................................................................................. 515
21.8 SAPH and SAPH_A Registers.......................................................................................... 516
21.8.1 SAPHIIDX/SAPH_AIIDX Register (Offset = 0h) [reset = 0h].............................................. 518
21.8.2 SAPHMIS/SAPH_AMIS Register (Offset = 2h) [reset = 0h]............................................... 519
21.8.3 SAPHRIS/SAPH_ARIS Register (Offset = 4h) [reset = 0h] ............................................... 520
21.8.4 SAPHIMSC/SAPH_AIMSC Register (Offset = 6h) [reset = 0h]........................................... 521
21.8.5 SAPHICR/SAPH_AICR Register (Offset = 8h) [reset = 0h]............................................... 522
21.8.6 SAPHISR/SAPH_AISR Register (Offset = Ah) [reset = 0h]............................................... 523
21.8.7 SAPHDESCLO/SAPH_ADESCLO Register (Offset = Ch) [reset = 10h]................................ 524
21.8.8 SAPHDESCHI/SAPH_ADESCHI Register (Offset = Eh) [reset = 5553h]............................... 525
21.8.9 SAPHKEY/SAPH_AKEY Register (Offset = 10h) [reset = 0h]............................................ 526
21.8.10 SAPHOCTL0/SAPH_AOCTL0 Register (Offset = 12h) [reset = 0h].................................... 527
21.8.11 SAPHOCTL1/SAPH_AOCTL1 Register (Offset = 14h) [reset = 0h].................................... 528
21.8.12 SAPHOSEL/SAPH_AOSEL Register (Offset = 16h) [reset = 5h]....................................... 529
21.8.13 SAPHCH0PUT/SAPH_ACH0PUT Register (Offset = 20h) [reset = 0h]................................ 530
21.8.14 SAPHCH0PDT/SAPH_ACH0PDT Register (Offset = 22h) [reset = 0h]................................ 531
21.8.15 SAPHCH0TT/SAPH_ACH0TT Register (Offset = 24h) [reset = 0h].................................... 532
21.8.16 SAPHCH1PUT /SAPH_ACH1PUT Register (Offset = 26h) [reset = 0h]............................... 533
21.8.17 SAPHCH1PDT/SAPH_ACH1PDT Register (Offset = 28h) [reset = 0h]................................ 534
21.8.18 SAPHCH1TT/SAPH_ACH1TT Register (Offset = 2Ah) [reset = 0h] ................................... 535
21.8.19 SAPHMCNF/SAPH_AMCNF Register (Offset = 2Ch) [reset = 2h]..................................... 536
21.8.20 SAPHTACTL/SAPH_ATACTL Register (Offset = 2Eh) [reset = 0h].................................... 537
21.8.21 SAPHICTL0 /SAPH_AICTL0 Register (Offset = 30h) [reset = 90h].................................... 538
21.8.22 SAPHBCTL/SAPH_ABCTL Register (Offset = 34h) [reset = A1h]...................................... 540
21.8.23 SAPHPGC/SAPH_APGC Register (Offset = 40h) [reset = 0h] ......................................... 542
21.8.24 SAPHPGLPER/SAPH_APGLPER Register (Offset = 42h) [reset = 0h] ............................... 543
21.8.25 SAPHPGHPER/SAPH_APGHPER Register (Offset = 44h) [reset = 0h] .............................. 544
21.8.26 SAPHPGCTL/SAPH_APGCTL Register (Offset = 46h) [reset = 11h].................................. 545
21.8.27 SAPHPPGTRIG/SAPH_APPGTRIG Register (Offset = 48h) [reset = 0h]............................. 547
21.8.28 SAPH_AXPGCTL Register (Offset = 4Ah) [reset = 0h] .................................................. 548
21.8.29 SAPH_AXPGLPER Register (Offset = 4Ch) [reset = 0h]................................................ 549
21.8.30 SAPH_AXPGHPER Register (Offset = 4Eh) [reset = 0h]................................................ 550
21.8.31 SAPHASCTL0/SAPH_AASCTL0 Register (Offset = 60h) [reset = 0h]................................. 551
21.8.32 SAPHASCTL1/SAPH_AASCTL1 Register (Offset = 62h) [reset = 0h]................................. 553
21.8.33 SAPHASQTRIG/SAPH_AASQTRIG Register (Offset = 64h) [reset = 0h]............................. 555
21.8.34 SAPHAPOL/SAPH_AAPOL Register (Offset = 66h) [reset = 0h]....................................... 556
21.8.35 SAPHAPLEV /SAPH_AAPLEV Register (Offset = 68h) [reset = 0h]................................... 557
21.8.36 SAPHAPHIZ /SAPH_AAPHIZ Register (Offset = 6Ah) [reset = 0h] .................................... 558
21.8.37 SAPHATM_A/SAPH_AATM_A Register (Offset = 6Eh) [reset = 0h]................................... 559
21.8.38 SAPHATM_B/SAPH_AATM_B Register (Offset = 70h) [reset = 0h] ................................... 560
21.8.39 SAPHATM_C/SAPH_AATM_C Register (Offset = 72h) [reset = 0h]................................... 561
21.8.40 SAPHATM_D/SAPH_AATM_D Register (Offset = 74h) [reset = 0h]................................... 562

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21.8.41 SAPHATM_E/SAPH_AATM_E Register (Offset = 76h) [reset = 0h] ................................... 563
21.8.42 SAPHATM_F/SAPH_AATM_F Register (Offset = 78h) [reset = 0h] ................................... 564
21.8.43 SAPHTBCTL/SAPH_ATBCTL Register (Offset = 7Ah) [reset = 0h].................................... 565
21.8.44 SAPHATIMLO/SAPH_AATIMLO Register (Offset = 7Ch) [reset = 0h]................................. 566
21.8.45 SAPHATIMHI/SAPH_AATIMHI Register (Offset = 7Eh) [reset = 0h]................................... 567
22 Sigma-Delta High Speed (SDHS)......................................................................................... 568
22.1 Introduction ................................................................................................................ 569
22.2 SDHS Functional Operation............................................................................................. 569
22.2.1 Input Multiplexer ................................................................................................ 570
22.2.2 Third-Order Modulator ......................................................................................... 570
22.2.3 Digital Output.................................................................................................... 571
22.2.4 Data Transfer Controller (DTC) and Internal Data Buffer ................................................. 578
22.2.5 PGA Gain Control .............................................................................................. 580
22.2.6 SDHS Power and Conversion Control....................................................................... 582
22.2.7 TRIGEN Bit and SDHS_LOCK Bit............................................................................ 584
22.2.8 AUTOSSDIS (Auto Conversion Start Disable) Bit.......................................................... 588
22.2.9 INTDLY (Interrupt Delay) bits ................................................................................. 589
22.2.10 Total Sample Size............................................................................................. 590
22.2.11 Window Comparator.......................................................................................... 591
22.2.12 Conditions to Stop Data Conversion........................................................................ 592
22.3 Interrupts................................................................................................................... 594
22.3.1 IIDX, Interrupt Vector Generator.............................................................................. 594
22.4 Debug Mode............................................................................................................... 594
22.5 SDHS Registers........................................................................................................... 595
22.5.1 SDHSIIDX Register (Offset = 0h) [reset = 0h].............................................................. 596
22.5.2 SDHSMIS Register (Offset = 2h) [reset = 0h]............................................................... 597
22.5.3 SDHSRIS Register (Offset = 4h) [reset = 0h]............................................................... 598
22.5.4 SDHSIMSC Register (Offset = 6h) [reset = 0h]............................................................. 600
22.5.5 SDHSICR Register (Offset = 8h) [reset = 0h]............................................................... 601
22.5.6 SDHSISR Register (Offset = Ah) [reset = 0h]............................................................... 602
22.5.7 SDHSDESCLO Register (Offset = Ch) [reset = 110h]..................................................... 603
22.5.8 SDHSDESCHI Register (Offset = Eh) [reset = BB10h].................................................... 604
22.5.9 SDHSCTL0 Register (Offset = 10h) [reset = 8001h]....................................................... 605
22.5.10 SDHSCTL1 Register (Offset = 12h) [reset = 0h].......................................................... 607
22.5.11 SDHSCTL2 Register (Offset = 14h) [reset = 0h].......................................................... 608
22.5.12 SDHSCTL3 Register (Offset = 16h) [reset = 0h].......................................................... 609
22.5.13 SDHSCTL4 Register (Offset = 18h) [reset = 0h].......................................................... 610
22.5.14 SDHSCTL5 Register (Offset = 1Ah) [reset = 0h] ......................................................... 611
22.5.15 SDHSCTL6 Register (Offset = 1Ch) [reset = 19h]........................................................ 613
22.5.16 SDHSCTL7 Register (Offset = 1Eh) [reset = Fh] ......................................................... 614
22.5.17 SDHSDT Register (Offset = 22h) [reset = 0h]............................................................. 615
22.5.18 SDHSWINHITH Register (Offset = 24h) [reset = 0h]..................................................... 616
22.5.19 SDHSWINLOTH Register (Offset = 26h) [reset = 0h].................................................... 617
22.5.20 SDHSDTCDA Register (Offset = 28h) [reset = 0h]....................................................... 618
23 Metering Test Interface (MTIF)............................................................................................ 619
23.1 MTIF Introduction......................................................................................................... 620
23.2 MTIF Operation ........................................................................................................... 621
23.2.1 MTIF and RTC_C............................................................................................... 621
23.2.2 Initialization of the MTIF ....................................................................................... 622
23.2.3 Setting the Pulse Rate ......................................................................................... 622
23.2.4 Reading Pulse Counter ........................................................................................ 623
23.2.5 Synchronizing Pulse Generator Timing to Application..................................................... 623
23.2.6 Various Resets During MTIF Operation ..................................................................... 623

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23.2.7 PUC Reset During Register Access.......................................................................... 623
23.2.8 Enabling the Pulse Generator and the Pulse Counter..................................................... 624
23.3 MTIF Block Diagram...................................................................................................... 624
23.3.1 Test Interface Input............................................................................................. 624
23.4 MTIF Registers............................................................................................................ 625
23.4.1 MTIFPGCNF Register (Offset = 0h) [reset = 6970h]....................................................... 626
23.4.2 MTIFPGKVAL Register (Offset = 2h) [reset = 6900h] ..................................................... 627
23.4.3 MTIFPGCTL Register (Offset = 4h) [reset = 6900h]....................................................... 628
23.4.4 MTIFPGSR Register (Offset = 6h) [reset = 0h]............................................................. 629
23.4.5 MTIFPCCNF Register (Offset = 8h) [reset = 9600h]....................................................... 630
23.4.6 MTIFPCR Register (Offset = Ah) [reset = 0h]............................................................... 631
23.4.7 MTIFPCCTL Register (Offset = Ch) [reset = 0h] ........................................................... 632
23.4.8 MTIFPCSR Register (Offset = Eh) [reset = 0h]............................................................. 633
23.4.9 MTIFTPCTL Register (Offset = 10h) [reset = F00h] ....................................................... 634
24 Watchdog Timer (WDT_A).................................................................................................. 635
24.1 WDT_A Introduction...................................................................................................... 636
24.2 WDT_A Operation ........................................................................................................ 638
24.2.1 Watchdog Timer Counter (WDTCNT)........................................................................ 638
24.2.2 Watchdog Mode ................................................................................................ 638
24.2.3 Interval Timer Mode ............................................................................................ 638
24.2.4 Watchdog Timer Interrupts .................................................................................... 638
24.2.5 Fail-Safe Features.............................................................................................. 639
24.2.6 Operation in Low-Power Modes .............................................................................. 639
24.3 WDT_A Registers......................................................................................................... 640
24.3.1 WDTCTL Register .............................................................................................. 641
25 Timer_A........................................................................................................................... 642
25.1 Timer_A Introduction ..................................................................................................... 643
25.2 Timer_A Operation ....................................................................................................... 645
25.2.1 16-Bit Timer Counter........................................................................................... 645
25.2.2 Starting the Timer............................................................................................... 645
25.2.3 Timer Mode Control ............................................................................................ 646
25.2.4 Capture/Compare Blocks...................................................................................... 649
25.2.5 Output Unit ...................................................................................................... 651
25.2.6 Timer_A Interrupts.............................................................................................. 655
25.3 Timer_A Registers........................................................................................................ 657
25.3.1 TAxCTL Register ............................................................................................... 658
25.3.2 TAxR Register................................................................................................... 659
25.3.3 TAxCCTLn Register............................................................................................ 660
25.3.4 TAxCCRn Register ............................................................................................ 662
25.3.5 TAxIV Register.................................................................................................. 662
25.3.6 TAxEX0 Register ............................................................................................... 663
26 Timer_B........................................................................................................................... 664
26.1 Timer_B Introduction ..................................................................................................... 665
26.1.1 Similarities and Differences From Timer_A ................................................................. 665
26.2 Timer_B Operation ....................................................................................................... 667
26.2.1 16-Bit Timer Counter........................................................................................... 667
26.2.2 Starting the Timer............................................................................................... 667
26.2.3 Timer Mode Control ............................................................................................ 668
26.2.4 Capture/Compare Blocks...................................................................................... 671
26.2.5 Output Unit ...................................................................................................... 674
26.2.6 Timer_B Interrupts.............................................................................................. 678
26.3 Timer_B Registers........................................................................................................ 680
26.3.1 TBxCTL Register ............................................................................................... 681

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26.3.2 TBxR Register................................................................................................... 683
26.3.3 TBxCCTLn Register............................................................................................ 684
26.3.4 TBxCCRn Register ............................................................................................. 686
26.3.5 TBxIV Register.................................................................................................. 687
26.3.6 TBxEX0 Register ............................................................................................... 688
27 Real-Time Clock (RTC) Overview........................................................................................ 689
27.1 RTC Overview............................................................................................................. 689
28 Real-Time Clock B (RTC_B) ............................................................................................... 690
28.1 Real-Time Clock RTC_B Introduction.................................................................................. 691
28.2 RTC_B Operation......................................................................................................... 693
28.2.1 Real-Time Clock and Prescale Dividers..................................................................... 693
28.2.2 Real-Time Clock Alarm Function ............................................................................. 693
28.2.3 Reading or Writing Real-Time Clock Registers............................................................. 694
28.2.4 Real-Time Clock Interrupts.................................................................................... 694
28.2.5 Real-Time Clock Calibration .................................................................................. 696
28.2.6 Real-Time Clock Operation in LPM3.5 Low-Power Mode................................................. 697
28.3 RTC_B Registers ......................................................................................................... 698
28.3.1 RTCCTL0 Register ............................................................................................. 700
28.3.2 RTCCTL1 Register ............................................................................................. 701
28.3.3 RTCCTL2 Register ............................................................................................. 702
28.3.4 RTCCTL3 Register ............................................................................................. 702
28.3.5 RTCSEC Register – Hexadecimal Format .................................................................. 703
28.3.6 RTCSEC Register – BCD Format ............................................................................ 703
28.3.7 RTCMIN Register – Hexadecimal Format................................................................... 704
28.3.8 RTCMIN Register – BCD Format............................................................................. 704
28.3.9 RTCHOUR Register – Hexadecimal Format................................................................ 705
28.3.10 RTCHOUR Register – BCD Format ........................................................................ 705
28.3.11 RTCDOW Register............................................................................................ 706
28.3.12 RTCDAY Register – Hexadecimal Format................................................................. 706
28.3.13 RTCDAY Register – BCD Format........................................................................... 706
28.3.14 RTCMON Register – Hexadecimal Format................................................................ 707
28.3.15 RTCMON Register – BCD Format.......................................................................... 707
28.3.16 RTCYEAR Register – Hexadecimal Format............................................................... 708
28.3.17 RTCYEAR Register – BCD Format......................................................................... 708
28.3.18 RTCAMIN Register – Hexadecimal Format ............................................................... 709
28.3.19 RTCAMIN Register – BCD Format ......................................................................... 709
28.3.20 RTCAHOUR Register – Hexadecimal Format ............................................................ 710
28.3.21 RTCAHOUR Register – BCD Format ...................................................................... 710
28.3.22 RTCADOW Register.......................................................................................... 711
28.3.23 RTCADAY Register – Hexadecimal Format............................................................... 712
28.3.24 RTCADAY Register – BCD Format......................................................................... 712
28.3.25 RTCPS0CTL Register ........................................................................................ 713
28.3.26 RTCPS1CTL Register ........................................................................................ 714
28.3.27 RTCPS0 Register ............................................................................................. 715
28.3.28 RTCPS1 Register ............................................................................................. 715
28.3.29 RTCIV Register................................................................................................ 716
28.3.30 BIN2BCD Register ............................................................................................ 717
28.3.31 BCD2BIN Register ............................................................................................ 717
29 Real-Time Clock C (RTC_C) ............................................................................................... 718
29.1 Real-Time Clock (RTC_C) Introduction................................................................................ 719
29.2 RTC_C Operation......................................................................................................... 721
29.2.1 Calendar Mode.................................................................................................. 721

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29.2.2 Real-Time Clock and Prescale Dividers .................................................................... 721
29.2.3 Real-Time Clock Alarm Function ............................................................................ 721
29.2.4 Real-Time Clock Protection ................................................................................... 722
29.2.5 Reading or Writing Real-Time Clock Registers............................................................ 723
29.2.6 Real-Time Clock Interrupts.................................................................................... 723
29.2.7 Real-Time Clock Calibration for Crystal Offset Error....................................................... 725
29.2.8 Real-Time Clock Compensation for Crystal Temperature Drift........................................... 726
29.2.9 Real-Time Clock Operation in LPM3.5 Low-Power Mode................................................. 728
29.3 RTC_C Operation - Device-Dependent Features .................................................................... 729
29.3.1 Counter Mode................................................................................................... 729
29.3.2 Real-Time Clock Event/Tamper Detection With Time Stamp............................................. 732
29.4 RTC_C Registers......................................................................................................... 734
29.4.1 RTCCTL0_L Register .......................................................................................... 737
29.4.2 RTCCTL0_H Register.......................................................................................... 738
29.4.3 RTCCTL1 Register ............................................................................................. 739
29.4.4 RTCCTL3 Register ............................................................................................. 740
29.4.5 RTCOCAL Register ............................................................................................ 740
29.4.6 RTCTCMP Register ............................................................................................ 741
29.4.7 RTCNT1 Register............................................................................................... 742
29.4.8 RTCNT2 Register............................................................................................... 742
29.4.9 RTCNT3 Register............................................................................................... 742
29.4.10 RTCNT4 Register ............................................................................................. 742
29.4.11 RTCSEC Register – Calendar Mode With Hexadecimal Format ....................................... 743
29.4.12 RTCSEC Register – Calendar Mode With BCD Format................................................. 743
29.4.13 RTCMIN Register – Calendar Mode With Hexadecimal Format........................................ 744
29.4.14 RTCMIN Register – Calendar Mode With BCD Format.................................................. 744
29.4.15 RTCHOUR Register – Calendar Mode With Hexadecimal Format..................................... 745
29.4.16 RTCHOUR Register – Calendar Mode With BCD Format............................................... 745
29.4.17 RTCDOW Register – Calendar Mode ...................................................................... 746
29.4.18 RTCDAY Register – Calendar Mode With Hexadecimal Format ....................................... 746
29.4.19 RTCDAY Register – Calendar Mode With BCD Format................................................. 746
29.4.20 RTCMON Register – Calendar Mode With Hexadecimal Format ...................................... 747
29.4.21 RTCMON Register – Calendar Mode With BCD Format ................................................ 747
29.4.22 RTCYEAR Register – Calendar Mode With Hexadecimal Format ..................................... 748
29.4.23 RTCYEAR Register – Calendar Mode With BCD Format ............................................... 748
29.4.24 RTCAMIN Register – Calendar Mode With Hexadecimal Format...................................... 749
29.4.25 RTCAMIN Register – Calendar Mode With BCD Format................................................ 749
29.4.26 RTCAHOUR Register......................................................................................... 750
29.4.27 RTCAHOUR Register – Calendar Mode With BCD Format............................................. 750
29.4.28 RTCADOW Register – Calendar Mode .................................................................... 751
29.4.29 RTCADAY Register – Calendar Mode With Hexadecimal Format ..................................... 752
29.4.30 RTCADAY Register – Calendar Mode With BCD Format ............................................... 752
29.4.31 RTCPS0CTL Register ........................................................................................ 753
29.4.32 RTCPS1CTL Register ........................................................................................ 754
29.4.33 RTCPS0 Register ............................................................................................. 756
29.4.34 RTCPS1 Register ............................................................................................. 756
29.4.35 RTCIV Register................................................................................................ 757
29.4.36 BIN2BCD Register ............................................................................................ 758
29.4.37 BCD2BIN Register ............................................................................................ 758
29.4.38 RTCSECBAKx Register – Hexadecimal Format.......................................................... 759
29.4.39 RTCSECBAKx Register – BCD Format.................................................................... 759
29.4.40 RTCMINBAKx Register – Hexadecimal Format........................................................... 760
29.4.41 RTCMINBAKx Register – BCD Format .................................................................... 760

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29.4.42 RTCHOURBAKx Register – Hexadecimal Format........................................................ 761
29.4.43 RTCHOURBAKx Register – BCD Format ................................................................. 761
29.4.44 RTCDAYBAKx Register – Hexadecimal Format.......................................................... 762
29.4.45 RTCDAYBAKx Register – BCD Format.................................................................... 762
29.4.46 RTCMONBAKx Register – Hexadecimal Format ......................................................... 763
29.4.47 RTCMONBAKx Register – BCD Format ................................................................... 763
29.4.48 RTCYEARBAKx Register – Hexadecimal Format ........................................................ 764
29.4.49 RTCYEARBAKx Register – BCD Format.................................................................. 764
29.4.50 RTCTCCTL0 Register ........................................................................................ 765
29.4.51 RTCTCCTL1 Register ........................................................................................ 765
29.4.52 RTCCAPxCTL Register ...................................................................................... 766
30 Enhanced Universal Serial Communication Interface (eUSCI) – UART Mode............................ 767
30.1 Enhanced Universal Serial Communication Interface A (eUSCI_A) Overview................................... 768
30.2 eUSCI_A Introduction – UART Mode .................................................................................. 768
30.3 eUSCI_A Operation – UART Mode .................................................................................... 770
30.3.1 eUSCI_A Initialization and Reset............................................................................. 770
30.3.2 Character Format............................................................................................... 770
30.3.3 Asynchronous Communication Format ...................................................................... 770
30.3.4 Automatic Baud-Rate Detection .............................................................................. 773
30.3.5 IrDA Encoding and Decoding ................................................................................. 774
30.3.6 Automatic Error Detection ..................................................................................... 775
30.3.7 eUSCI_A Receive Enable ..................................................................................... 776
30.3.8 eUSCI_A Transmit Enable .................................................................................... 776
30.3.9 UART Baud-Rate Generation................................................................................. 777
30.3.10 Setting a Baud Rate .......................................................................................... 779
30.3.11 Transmit Bit Timing - Error calculation ..................................................................... 780
30.3.12 Receive Bit Timing – Error Calculation..................................................................... 780
30.3.13 Typical Baud Rates and Errors.............................................................................. 781
30.3.14 Using the eUSCI_A Module in UART Mode With Low-Power Modes ................................. 783
30.3.15 eUSCI_A Interrupts in UART Mode......................................................................... 784
30.3.16 DMA Operation................................................................................................ 785
30.4 eUSCI_A UART Registers............................................................................................... 786
30.4.1 UCAxCTLW0 Register ......................................................................................... 787
30.4.2 UCAxCTLW1 Register ......................................................................................... 788
30.4.3 UCAxBRW Register............................................................................................ 789
30.4.4 UCAxMCTLW Register ........................................................................................ 789
30.4.5 UCAxSTATW Register......................................................................................... 790
30.4.6 UCAxRXBUF Register ......................................................................................... 791
30.4.7 UCAxTXBUF Register ......................................................................................... 791
30.4.8 UCAxABCTL Register.......................................................................................... 792
30.4.9 UCAxIRCTL Register........................................................................................... 793
30.4.10 UCAxIE Register .............................................................................................. 794
30.4.11 UCAxIFG Register ............................................................................................ 795
30.4.12 UCAxIV Register .............................................................................................. 796
31 Enhanced Universal Serial Communication Interface (eUSCI) – SPI Mode ............................... 797
31.1 Enhanced Universal Serial Communication Interfaces (eUSCI_A, eUSCI_B) Overview ....................... 798
31.2 eUSCI Introduction – SPI Mode ........................................................................................ 798
31.3 eUSCI Operation – SPI Mode........................................................................................... 800
31.3.1 eUSCI Initialization and Reset ................................................................................ 800
31.3.2 Character Format............................................................................................... 801
31.3.3 Master Mode .................................................................................................... 801
31.3.4 Slave Mode...................................................................................................... 802
31.3.5 SPI Enable....................................................................................................... 803

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31.3.6 Serial Clock Control ............................................................................................ 803
31.3.7 Using the SPI Mode With Low-Power Modes............................................................... 804
31.3.8 eUSCI Interrupts in SPI Mode ................................................................................ 804
31.4 eUSCI_A SPI Registers.................................................................................................. 806
31.4.1 UCAxCTLW0 Register ......................................................................................... 807
31.4.2 UCAxBRW Register............................................................................................ 808
31.4.3 UCAxSTATW Register......................................................................................... 809
31.4.4 UCAxRXBUF Register ......................................................................................... 810
31.4.5 UCAxTXBUF Register ......................................................................................... 811
31.4.6 UCAxIE Register................................................................................................ 812
31.4.7 UCAxIFG Register.............................................................................................. 813
31.4.8 UCAxIV Register................................................................................................ 814
31.5 eUSCI_B SPI Registers.................................................................................................. 815
31.5.1 UCBxCTLW0 Register ......................................................................................... 816
31.5.2 UCBxBRW Register............................................................................................ 817
31.5.3 UCBxSTATW Register......................................................................................... 817
31.5.4 UCBxRXBUF Register ......................................................................................... 818
31.5.5 UCBxTXBUF Register ......................................................................................... 818
31.5.6 UCBxIE Register ............................................................................................... 819
31.5.7 UCBxIFG Register.............................................................................................. 819
31.5.8 UCBxIV Register................................................................................................ 820
32 Enhanced Universal Serial Communication Interface (eUSCI) – I2C Mode ................................ 821
32.1 Enhanced Universal Serial Communication Interface B (eUSCI_B) Overview................................... 822
32.2 eUSCI_B Introduction – I2C Mode...................................................................................... 822
32.3 eUSCI_B Operation – I2C Mode ........................................................................................ 823
32.3.1 eUSCI_B Initialization and Reset............................................................................. 824
32.3.2 I2C Serial Data .................................................................................................. 824
32.3.3 I2C Addressing Modes ......................................................................................... 825
32.3.4 I2C Quick Setup ................................................................................................. 826
32.3.5 I2C Module Operating Modes ................................................................................. 827
32.3.6 Glitch Filtering................................................................................................... 837
32.3.7 I2C Clock Generation and Synchronization.................................................................. 837
32.3.8 Byte Counter .................................................................................................... 839
32.3.9 Multiple Slave Addresses...................................................................................... 839
32.3.10 Using the eUSCI_B Module in I2C Mode With Low-Power Modes ..................................... 840
32.3.11 eUSCI_B Interrupts in I2C Mode ............................................................................ 840
32.4 eUSCI_B I2C Registers.................................................................................................. 844
32.4.1 UCBxCTLW0 Register ......................................................................................... 845
32.4.2 UCBxCTLW1 Register ......................................................................................... 847
32.4.3 UCBxBRW Register............................................................................................ 849
32.4.4 UCBxSTATW.................................................................................................... 849
32.4.5 UCBxTBCNT Register ......................................................................................... 850
32.4.6 UCBxRXBUF Register ......................................................................................... 851
32.4.7 UCBxTXBUF .................................................................................................... 851
32.4.8 UCBxI2COA0 Register......................................................................................... 852
32.4.9 UCBxI2COA1 Register......................................................................................... 853
32.4.10 UCBxI2COA2 Register ....................................................................................... 853
32.4.11 UCBxI2COA3 Register ....................................................................................... 854
32.4.12 UCBxADDRX Register ....................................................................................... 854
32.4.13 UCBxADDMASK Register ................................................................................... 855
32.4.14 UCBxI2CSA Register......................................................................................... 855
32.4.15 UCBxIE Register .............................................................................................. 856
32.4.16 UCBxIFG Register ............................................................................................ 858

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32.4.17 UCBxIV Register .............................................................................................. 860
33 REF_A............................................................................................................................. 861
33.1 REF_A Introduction....................................................................................................... 862
33.2 Principle of Operation .................................................................................................... 863
33.2.1 Low-Power Operation.......................................................................................... 863
33.2.2 Reference System Requests.................................................................................. 863
33.3 REF_A Registers ......................................................................................................... 865
33.3.1 REFCTL0 Register (offset = 00h) [reset = 0000h] ......................................................... 866
34 ADC12_B ......................................................................................................................... 868
34.1 ADC12_B Introduction ................................................................................................... 869
34.2 ADC12_B Operation...................................................................................................... 871
34.2.1 12-Bit ADC Core................................................................................................ 871
34.2.2 ADC12_B Inputs and Multiplexer............................................................................. 872
34.2.3 Voltage References ............................................................................................ 872
34.2.4 Auto Power Down .............................................................................................. 873
34.2.5 Sample Frequency Mode Selection.......................................................................... 873
34.2.6 Sample and Conversion Timing .............................................................................. 873
34.2.7 Conversion Memory............................................................................................ 876
34.2.8 ADC12_B Conversion Modes................................................................................. 877
34.2.9 Operation in LPM3 and LPM4 ................................................................................ 882
34.2.10 Window Comparator.......................................................................................... 882
34.2.11 Using the Integrated Temperature Sensor................................................................. 883
34.2.12 ADC12_B Grounding and Noise Considerations ......................................................... 884
34.2.13 ADC12_B Calibration......................................................................................... 885
34.2.14 ADC12_B Interrupts .......................................................................................... 885
34.3 ADC12_B Registers...................................................................................................... 887
34.3.1 ADC12CTL0 Register (offset = 00h) [reset = 0000h] ...................................................... 893
34.3.2 ADC12CTL1 Register (offset = 02h) [reset = 0000h] ...................................................... 895
34.3.3 ADC12CTL2 Register (offset = 04h) [reset = 0020h] ...................................................... 897
34.3.4 ADC12CTL3 Register (offset = 06h) [reset = 0000h] ...................................................... 898
34.3.5 ADC12MEMx Register (x = 0 to 31) ......................................................................... 899
34.3.6 ADC12MCTLx Register (x = 0 to 31) ........................................................................ 900
34.3.7 ADC12HI Register (offset = 0Ah) [reset = 0FFFh] ......................................................... 902
34.3.8 ADC12LO Register (offset = 08h) [reset = 0000h] ......................................................... 902
34.3.9 ADC12IER0 Register (offset = 12h) [reset = 0000h]....................................................... 903
34.3.10 ADC12IER1 Register (offset = 14h) [reset = 0000h] ..................................................... 905
34.3.11 ADC12IER2 Register (offset = 16h) [reset = 0000h] ..................................................... 907
34.3.12 ADC12IFGR0 Register (offset = 0Ch) [reset = 0000h]................................................... 908
34.3.13 ADC12IFGR1 Register (offset = 0Eh) [reset = 0000h]................................................... 910
34.3.14 ADC12IFGR2 Register (offset = 10h) [reset = 0000h] ................................................... 912
34.3.15 ADC12IV Register (offset = 18h) [reset = 0000h]......................................................... 913
35 Comparator E (COMP_E) Module........................................................................................ 915
35.1 COMP_E Introduction.................................................................................................... 916
35.2 COMP_E Operation ...................................................................................................... 917
35.2.1 Comparator...................................................................................................... 917
35.2.2 Analog Input Switches ......................................................................................... 917
35.2.3 Port Logic........................................................................................................ 917
35.2.4 Input Short Switch .............................................................................................. 917
35.2.5 Output Filter ..................................................................................................... 918
35.2.6 Reference Voltage Generator................................................................................. 919
35.2.7 Port Disable Register (CEPD) ................................................................................ 920
35.2.8 Comparator_E Interrupts ...................................................................................... 920
35.2.9 Comparator_E Used to Measure Resistive Elements ..................................................... 920

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Contents
35.3 COMP_E Registers....................................................................................................... 923
35.3.1 CECTL0 Register (offset = 00h) [reset = 0000h]........................................................... 924
35.3.2 CECTL1 Register (offset = 02h) [reset = 0000h]........................................................... 925
35.3.3 CECTL2 Register (offset = 04h) [reset = 0000h]........................................................... 926
35.3.4 CECTL3 Register (offset = 06h) [reset = 0000h]........................................................... 927
35.3.5 CEINT Register (offset = 0Ch) [reset = 0000h]............................................................. 929
35.3.6 CEIV Register (offset = 0Eh) [reset = 0000h]............................................................... 930
36 LCD_C Controller.............................................................................................................. 931
36.1 LCD_C Introduction....................................................................................................... 932
36.2 LCD_C Operation......................................................................................................... 934
36.2.1 LCD Memory .................................................................................................... 934
36.2.2 LCD Timing Generation........................................................................................ 935
36.2.3 Blanking the LCD............................................................................................... 936
36.2.4 LCD Blinking..................................................................................................... 936
36.2.5 LCD Voltage And Bias Generation........................................................................... 937
36.2.6 LCD Outputs..................................................................................................... 940
36.2.7 LCD Interrupts................................................................................................... 941
36.2.8 Static Mode...................................................................................................... 943
36.2.9 2-Mux Mode ..................................................................................................... 944
36.2.10 3-Mux Mode.................................................................................................... 945
36.2.11 4-Mux Mode.................................................................................................... 946
36.2.12 6-Mux Mode.................................................................................................... 947
36.2.13 8-Mux Mode.................................................................................................... 948
36.3 LCD_C Registers ......................................................................................................... 950
36.3.1 LCDCCTL0 Register ........................................................................................... 955
36.3.2 LCDCCTL1 Register ........................................................................................... 957
36.3.3 LCDCBLKCTL Register........................................................................................ 958
36.3.4 LCDCMEMCTL Register....................................................................................... 959
36.3.5 LCDCVCTL Register ........................................................................................... 960
36.3.6 LCDCPCTL0 Register.......................................................................................... 962
36.3.7 LCDCPCTL1 Register.......................................................................................... 962
36.3.8 LCDCPCTL2 Register.......................................................................................... 963
36.3.9 LCDCPCTL3 Register.......................................................................................... 963
36.3.10 LCDCCPCTL Register........................................................................................ 964
36.3.11 LCDCIV Register.............................................................................................. 964
37 Extended Scan Interface (ESI)............................................................................................ 965
37.1 ESI Introduction........................................................................................................... 966
37.2 ESI Operation ............................................................................................................. 967
37.2.1 ESI Analog Front End.......................................................................................... 967
37.2.2 ESI Timing State Machine..................................................................................... 974
37.2.3 ESI Pre-Processing and State Storage...................................................................... 979
37.2.4 TimerA Output Stage........................................................................................... 980
37.2.5 ESI Processing State Machine................................................................................ 981
37.2.6 ESI Debug Register ............................................................................................ 985
37.2.7 ESI Interrupts.................................................................................................... 985
37.2.8 Overview of ESI Applications ................................................................................. 986
37.3 ESI Registers.............................................................................................................. 993
37.3.1 ESIDEBUG1 Register.......................................................................................... 994
37.3.2 ESIDEBUG2 Register.......................................................................................... 994
37.3.3 ESIDEBUG3 Register.......................................................................................... 994
37.3.4 ESIDEBUG4 Register.......................................................................................... 995
37.3.5 ESIDEBUG5 Register.......................................................................................... 995
37.3.6 ESICNT0 Register.............................................................................................. 996

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37.3.7 ESICNT1 Register.............................................................................................. 996
37.3.8 ESICNT2 Register.............................................................................................. 997
37.3.9 ESICNT3 Register.............................................................................................. 997
37.3.10 ESIIV Register................................................................................................. 998
37.3.11 ESIINT1 Register.............................................................................................. 999
37.3.12 ESIINT2 Register ............................................................................................ 1001
37.3.13 ESIAFE Register............................................................................................. 1003
37.3.14 ESIPPU Register ............................................................................................ 1005
37.3.15 ESITSM Register ............................................................................................ 1006
37.3.16 ESIPSM Register ............................................................................................ 1008
37.3.17 ESIOSC Register ............................................................................................ 1009
37.3.18 ESICTL Register............................................................................................. 1010
37.3.19 ESITHR1 Register........................................................................................... 1012
37.3.20 ESITHR2 Register........................................................................................... 1012
37.3.21 ESIDAC1Rx Register (x = 0 to 7) ......................................................................... 1013
37.3.22 ESIDAC2Rx Register (x = 0 to 7) ......................................................................... 1013
37.3.23 ESITSMx Register (x = 0 to 31) ........................................................................... 1014
37.3.24 Extended Scan Interface Processing State Machine Table Entry (ESI Memory)................... 1016
38 Embedded Emulation Module (EEM).................................................................................. 1017
38.1 Embedded Emulation Module (EEM) Introduction.................................................................. 1018
38.2 EEM Building Blocks.................................................................................................... 1020
38.2.1 Triggers......................................................................................................... 1020
38.2.2 Trigger Sequencer ............................................................................................ 1020
38.2.3 State Storage (Internal Trace Buffer)....................................................................... 1020
38.2.4 Cycle Counter.................................................................................................. 1020
38.2.5 EnergyTrace++ Technology ................................................................................. 1021
38.2.6 Clock Control .................................................................................................. 1021
38.2.7 Debug Modes.................................................................................................. 1021
38.3 EEM Configurations..................................................................................................... 1021
Revision History ...................................................................................................................... 1023

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List of Figures
List of Figures
1-1. BOR, POR, and PUC Reset Circuit...................................................................................... 49
1-2. Interrupt Priority............................................................................................................. 50
1-3. Interrupt Processing........................................................................................................ 52
1-4. Return From Interrupt...................................................................................................... 53
1-5. Operation Modes........................................................................................................... 57
1-6. Devices Descriptor Table.................................................................................................. 66
1-7. SFRIE1 Register ........................................................................................................... 73
1-8. SFRIFG1 Register.......................................................................................................... 74
1-9. SFRRPCR Register........................................................................................................ 75
1-10. SYSCTL Register .......................................................................................................... 77
1-11. SYSJMBC Register ........................................................................................................ 78
1-12. SYSJMBI0 Register........................................................................................................ 79
1-13. SYSJMBI1 Register........................................................................................................ 79
1-14. SYSJMBO0 Register....................................................................................................... 80
1-15. SYSJMBO1 Register....................................................................................................... 80
1-16. SYSUNIV Register......................................................................................................... 81
1-17. SYSSNIV Register ......................................................................................................... 81
1-18. SYSRSTIV Register........................................................................................................ 82
2-1. PMM Block Diagram....................................................................................................... 84
2-2. Voltage Failure and Resulting PMM Actions ........................................................................... 85
2-3. PMM Action at Device Power-Up ........................................................................................ 86
2-4. PMMCTL0 Register........................................................................................................ 89
2-5. PMMCTL1 Register........................................................................................................ 90
2-6. PMMIFG Register .......................................................................................................... 91
2-7. PM5CTL0 Register......................................................................................................... 92
3-1. Clock System Block Diagram............................................................................................. 95
3-2. Module Request Clock System........................................................................................... 99
3-3. Oscillator Fault Logic..................................................................................................... 101
3-4. Switch MCLK From DCOCLK to LFXTCLK ........................................................................... 102
3-5. CTL0 Register............................................................................................................. 104
3-6. CTL1 Register............................................................................................................. 105
3-7. CTL2 Register............................................................................................................. 106
3-8. CTL3 Register............................................................................................................. 107
3-9. CTL4 Register............................................................................................................. 108
3-10. CTL5 Register............................................................................................................. 110
3-11. CTL6 Register............................................................................................................. 111
4-1. MSP430X CPU Block Diagram ......................................................................................... 114
4-2. PC Storage on the Stack for Interrupts ................................................................................ 115
4-3. Program Counter.......................................................................................................... 116
4-4. PC Storage on the Stack for CALLA................................................................................... 116
4-5. Stack Pointer .............................................................................................................. 117
4-6. Stack Usage............................................................................................................... 117
4-7. PUSHX.A Format on the Stack ......................................................................................... 117
4-8. PUSH SP, POP SP Sequence.......................................................................................... 117
4-9. SR Bits ..................................................................................................................... 118
4-10. Register-Byte and Byte-Register Operation........................................................................... 120
4-11. Register-Word Operation ................................................................................................ 120

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List of Figures
4-12. Word-Register Operation ................................................................................................ 121
4-13. Register – Address-Word Operation ................................................................................... 121
4-14. Address-Word – Register Operation ................................................................................... 122
4-15. Indexed Mode in Lower 64KB........................................................................................... 124
4-16. Indexed Mode in Upper Memory ....................................................................................... 125
4-17. Overflow and Underflow for Indexed Mode ........................................................................... 126
4-18. Example for Indexed Mode.............................................................................................. 127
4-19. Symbolic Mode Running in Lower 64KB .............................................................................. 130
4-20. Symbolic Mode Running in Upper Memory ........................................................................... 131
4-21. Overflow and Underflow for Symbolic Mode .......................................................................... 132
4-22. MSP430 Double-Operand Instruction Format......................................................................... 141
4-23. MSP430 Single-Operand Instructions.................................................................................. 142
4-24. Format of Conditional Jump Instructions .............................................................................. 143
4-25. Extension Word for Register Modes ................................................................................... 146
4-26. Extension Word for Non-Register Modes.............................................................................. 146
4-27. Example for Extended Register or Register Instruction ............................................................. 147
4-28. Example for Extended Immediate or Indexed Instruction ........................................................... 148
4-29. Extended Format I Instruction Formats................................................................................ 149
4-30. 20-Bit Addresses in Memory ............................................................................................ 149
4-31. Extended Format II Instruction Format................................................................................. 150
4-32. PUSHM and POPM Instruction Format................................................................................ 151
4-33. RRCM, RRAM, RRUM, and RLAM Instruction Format.............................................................. 151
4-34. BRA Instruction Format .................................................................................................. 151
4-35. CALLA Instruction Format ............................................................................................... 151
4-36. Decrement Overlap....................................................................................................... 177
4-37. Stack After a RET Instruction ........................................................................................... 196
4-38. Destination Operand—Arithmetic Shift Left ........................................................................... 198
4-39. Destination Operand—Carry Left Shift................................................................................. 199
4-40. Rotate Right Arithmetically RRA.B and RRA.W ...................................................................... 200
4-41. Rotate Right Through Carry RRC.B and RRC.W .................................................................... 201
4-42. Swap Bytes in Memory................................................................................................... 208
4-43. Swap Bytes in a Register................................................................................................ 208
4-44. Rotate Left Arithmetically—RLAM[.W] and RLAM.A................................................................. 235
4-45. Destination Operand-Arithmetic Shift Left............................................................................. 236
4-46. Destination Operand-Carry Left Shift .................................................................................. 237
4-47. Rotate Right Arithmetically RRAM[.W] and RRAM.A ................................................................ 238
4-48. Rotate Right Arithmetically RRAX(.B,.A) – Register Mode.......................................................... 240
4-49. Rotate Right Arithmetically RRAX(.B,.A) – Non-Register Mode.................................................... 240
4-50. Rotate Right Through Carry RRCM[.W] and RRCM.A .............................................................. 242
4-51. Rotate Right Through Carry RRCX(.B,.A) – Register Mode ........................................................ 244
4-52. Rotate Right Through Carry RRCX(.B,.A) – Non-Register Mode .................................................. 244
4-53. Rotate Right Unsigned RRUM[.W] and RRUM.A..................................................................... 245
4-54. Rotate Right Unsigned RRUX(.B,.A) – Register Mode .............................................................. 246
4-55. Swap Bytes SWPBX.A Register Mode ................................................................................ 250
4-56. Swap Bytes SWPBX.A In Memory ..................................................................................... 250
4-57. Swap Bytes SWPBX[.W] Register Mode .............................................................................. 251
4-58. Swap Bytes SWPBX[.W] In Memory................................................................................... 251
4-59. Sign Extend SXTX.A ..................................................................................................... 252
4-60. Sign Extend SXTX[.W]................................................................................................... 252