Texas Instruments TPS7H3014EVM-CVAL User manual

EVM User's Guide: TPS7H3014EVM-CVAL
TPS7H3014EVM-CVAL Evaluation Module (EVM)
Description
The TPS7H3014EVM-CVAL demonstrates the
operation of a single TPS7H3014-SP sequencer
(ceramic package). The board provides footprints
that can be populated with additional components to
allow for testing of customized configurations, such as
daisy-chained sequencers.
Features
• Flexible configuration options, including single-
device and daisy-chained device circuits.
• Customizable delay timers, sense thresholds,
sense hysteresis, and sequence up/down
thresholds.
• Footprints for optional external system reset
signal.
Figure 1-1. EVM Board
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Table of Contents
Description................................................................................................................................................................................. 1
Features......................................................................................................................................................................................1
1 Evaluation Module Overview................................................................................................................................................. 3
1.1 Introduction........................................................................................................................................................................ 3
1.2 Kit Contents........................................................................................................................................................................3
1.3 Specification.......................................................................................................................................................................3
1.4 Device Information............................................................................................................................................................. 6
2 Hardware................................................................................................................................................................................. 7
2.1 Power Requirements..........................................................................................................................................................7
2.2 Important Usage Notes...................................................................................................................................................... 7
2.3 Connector Descriptions......................................................................................................................................................7
3 Implementation Results....................................................................................................................................................... 10
3.1 Default Configuration Results.......................................................................................................................................... 10
3.2 Sequence UP and DOWN Thresholds.............................................................................................................................10
3.3 Delay Timer...................................................................................................................................................................... 12
3.4 Regulation Timer.............................................................................................................................................................. 15
3.5 Disabled Channels........................................................................................................................................................... 17
3.6 Externally Induced System RESET..................................................................................................................................18
4 Hardware Design Files......................................................................................................................................................... 19
4.1 Schematics.......................................................................................................................................................................19
4.2 PCB Layouts.................................................................................................................................................................... 23
4.3 Bill of Materials (BOM)..................................................................................................................................................... 28
5 Compliance Information.......................................................................................................................................................32
5.1 Compliance and Certifications......................................................................................................................................... 32
6 Additional Information..........................................................................................................................................................32
6.1 Known Hardware Issues.................................................................................................................................................. 32
7 Related Documentation........................................................................................................................................................32
8 Revision History................................................................................................................................................................... 32
Trademarks
All trademarks are the property of their respective owners.
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1 Evaluation Module Overview
1.1 Introduction
The TPS7H3014EVM-CVAL is the Evaluation Module (EVM) for the ceramic package option of the TPS7H3014
and provides a platform to electrically evaluate its features. This user’s guide provides details about the EVM,
including the configuration,schematics, and BOM.
The EVM is designed to provide flexibility in configuring the device under different conditions, through footprints
for external components and multiple connection options for monitored external rails and enable signal outputs.
By default, the device on the EVM is configured as shown in TPS7H3014EVM-CVAL Default Configuration and
Default EVM Schematic. To configure the device in a different configuration, please refer to the TPS7H3014 data
sheet to calculate the values of the passives around the device that needs to be changed.
1.2 Kit Contents
• EVM board (1)
• EVM Kit User Guide (1)
1.3 Specification
RREG
RDLY
GND
IN
SENSE1
SENSE2
SENSE3
SENSE4
HYS
DOWN
SEQ_DONE
UP
RTOP4
RBOTTOM4
VOUT4
RTOP2
RBOTTOM2
VOUT2
VIN
RTOP3
RBOTTOM3
VOUT3
RTOP1
RBOTTOM1
VOUT1
GND
VPULL_UP1
REG_TMR
VLDO
EN2
EN1
EN3
EN4
FAULT
REFCAP
PULL_UP1
VPULL_UP2
PULL_UP2
DLY_TMR
RHYS PWRGD
RFAULT_PU
CREFCAP
CVLDO
VLDO
VLDO
CPULL_UP1
CPULL_UP2
Figure 1-1. Default Configuration Simplified Schematic
Specification Value Description
Input Voltage
VIN 12V Falls within the recommended device input voltage range of 3V to 14V.
Sequence Up Threshold 10.2V
VIN rising threshold that initiates sequence UP.
Set by:
R16 = 10 kΩ
R20 = 620 Ω
Sequence Down Threshold 6V
VIN falling threshold that initiates sequence DOWN.
Set by:
R29 = 10 kΩ
R34 = 909 Ω
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Specification Value Description
PULL_UP1 Voltage 1.8V Voltage used by all ENx outputs. Falls within the recommended device input
voltage range of 1.6V to 7V.
PULL_UP2 Voltage 1.8V Voltage used by SEQ_DONE and PWRGD outputs. Falls within the
recommended device input voltage range of 1.6V to 7V.
VOUT1 VON Threshold 1.64V
(91 % of 1.8V)
Rising and falling voltage thresholds where the monitored VOUT rail is
considered ON or OFF, respectively.
Set by:
R21 = 60.4 kΩ
R25 = 34.8 kΩ
VOUT1 VOFF Threshold 0.19V
(11 % of 1.8V)
VOUT2 VON Threshold 1.34 V
(90 % of 1.5V)
Rising and falling voltage thresholds where the monitored VOUT rail is
considered ON or OFF, respectively.
Set by:
R22 = 49.9 kΩ
R26 = 40.2 kΩ
VOUT2 VOFF Threshold 0.15 V
(10 % of 1.5V)
VOUT3 VON Threshold 0.72 V
(90 % of 0.8V)
Rising and falling voltage thresholds where the monitored VOUT rail is
considered ON or OFF, respectively.
Set by:
R32 = 26.7 kΩ
R35 = 130 kΩ
VOUT3 VOFF Threshold 0.08 V
(10 % of 0.8V)
VOUT4 VON Threshold 0.79 V
(90 % of 0.88V)
Rising and falling voltage thresholds where the monitored VOUT rail is
considered ON or OFF, respectively.
Set by:
R33 = 29.4 kΩ
R36 = 90.9 kΩ
VOUT4 VOFF Threshold 0.09 V
(10 % of 0.88V)
ENx Delay Time
tDLY_TMR 12.35 ms
Programmable time delay between when the condition for an ENx signal to
transition is met and when the signal actually transitions.
Set by:
R11 = 619 kΩ
J16 shunted
SENSEx Regulation Timer
tREG_TMR 12.35 ms
Programmable timer that sets the amount of time SENSEx is allowed to
reach the regulation threshold voltage (VTH_SENSEx, typically 599mV).
If VTH_SENSEx is not reached before the timer expires, the device will
sequence down.
Set by:
R14 = 619 kΩ
J20 shunted
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1.3.1 Alternate Board Configurations
The TPS7H3014EVM-CVAL board provides footprints that can be populated with components for testing a
"daisy-chain" configuration of 2 TPS7H3014-SP sequencers. The configuration is used to increase the number
of monitored SENSEx inputs and ENx outputs that can be used for sequencing.
The Daisy-chain Configuration EVM Schematic shows an example of how this configuration can be set up. This
dual-device configuration has the same specifications as the table in the previous section which described the
default single-device EVM configuration. Also, the following specifications for the additional SENSEx rails and
timer settings of the secondary device are provided.
RREG
RDLY
GND
IN
SENSE1
SENSE2
SENSE3
SENSE4
HYS
DOWN
SEQ_DONE
UP
RTOP4
RBOTTOM4
VOUT4
RTOP2
RBOTTOM2
VOUT2
VIN
RTOP3
RBOTTOM3
VOUT3
RTOP1
RBOTTOM1
VOUT1
GND
VPULL-UP1
REG_TMR
VLDO
EN2
EN1
EN3
EN4
FAULT
REFCAP
PULL_UP1
VPULL_UP2
PULL_UP2
DLY_TMR
RHYS PWRGD
RREG
RDLY
GND
IN
SENSE1
SENSE2
SENSE3
SENSE4
HYS
DOWN
SEQ_DONE
UP
RTOP4
RBOTTOM4
VOUT4
RTOP2
RBOTTOM2
VOUT2
VIN
RTOP3
RBOTTOM3
VOUT3
RTOP1
RBOTTOM1
VOUT1
GND
VPULL-UP1
REG_TMR
VLDO
EN2
EN1
EN3
EN4
FAULT
REFCAP
PULL_UP1
VPULL_UP2
PULL_UP2
DLY_TMR
RHYS PWRGD
To Controller
From Controller
RFAULT_PU
VLDO1
RFAULT_PU
VLDO2
CREFCAP CREFCAP
CVLDO
VLDO1
CVLDO
VLDO2
Figure 1-2. Daisy-chain Configuration Example
Specification Value Description
VOUT1 VON Threshold
VON1_S
1.34V
(90 % of 1.5V)
Rising and falling voltage thresholds where the monitored VOUT rail is
considered ON or OFF, respectively.
Set by:
R57 = 49.9kΩ
R59 = 40.2kΩ
VOUT1 VOFF Threshold
VOFF1_S
0.15V
(10 % of 1.5V)
VOUT2 VON Threshold
VON2_S
0.85V
(85% of 1V)
Rising and falling voltage thresholds where the monitored VOUT rail is
considered ON or OFF, respectively.
Set by:
R58 = 14.5kΩ
R60 = 34.8kΩ
VOUT2 VOFF Threshold
VOFF2_S
0.50V
(50 % of 1V)
Secondary VOUT3 VON Threshold
VON3_S
1.08V
(90 % of 1.2V)
Rising and falling voltage thresholds where the monitored VOUT rail is
considered ON or OFF, respectively.
Set by:
R65 = 40.2kΩ
R68 = 49.9kΩ
Secondary VOUT3 VOFF Threshold
VOFF3_S
0.12V
(10% of 1.2V)
VOUT4 VON Threshold
VON4_S
1.16V
(97 % of 1.2V)
Rising and falling voltage thresholds where the monitored VOUT rail is
considered ON or OFF, respectively.
Set by:
R66 = 1kΩ
R69 = 1.07kΩ
VOUT4 VOFF Threshold
VOFF4_S
1.14
(95 % of 1.2V)
ENx Delay Time
tDLY_TMR 0.25ms
Programmable time delay between when the condition for an ENx signal to
transition is met and when the signal actually transitions.
Set by:
R52 = 10kΩ
J53 shunted
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Specification Value Description
SENSEx Regulation Timer
tREG_TMR 0.25ms
Programmable timer that sets the amount of time SENSEx is allowed to
reach the regulation threshold voltage (VTH_SENSEx, typically 599mV). If
VTH_SENSEx is not reached before the timer expires, the device sequences
down.
Set by:
R53 = 10kΩ
J54 shunted
1.4 Device Information
The TPS7H3014 is an integrated, 3V to 14V, four-channel radiation-hardness-assured power supply sequencer.
Channel count can be expanded by connecting multiple devices in a daisy-chain configuration. The device has
active high sequence UP and DOWN inputs. Additionally, the SEQ_DONE, PWRGD, and FAULT outputs of the
device provide information about the sequence, power, and internally-generated fault status of the monitored
power tree to increase system-level reliability. An accurate 599mV ± 1 % SENSEx threshold voltage and a
24μA ± 3 % hysteresis current allow the user to set programmable rise and fall thresholds for the voltage rails
monitored by the sequencer. The rise/fall delay time of all ENx outputs is globally programmed via a single
resistor on the DLY_TMR pin, or by floating the pin to result in the shortest possible delay time. Similarly, the
time the device allows for the SENSEx voltage to pass the ON threshold can be globally programmed via a
single resistor on the REG_TMR pin, or by floating the pin to allow infinite time for the SENSEx voltage to pass
the on threshold. A standard microcircuit drawing (SMD) is available for the QML variants: 5962R23201VXC.
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2 Hardware
2.1 Power Requirements
The TPS7H3014EVM-CVAL board requires 3 power rails (VIN, VPULL_UP1, and VPULL_UP2) to be externally
provided by power supplies. These can be separate or shared as long as the voltage ranges of each are
respected. The test results shown in this user guide were performed with 1 power supply used for VIN and 1
power supply shared by VPULL_UP1 and VPULL_UP2.
• 3V ≤ VIN ≤ 14V
• 1.6V ≤ VPULL_UPx ≤ 7V
2.2 Important Usage Notes
The TPS7H3014EVM-CVAL board is configured so that the ENx signals are tied by a 0Ω resistor to their
respective SENSEx signal. This configuration is purely for simplicity of testing device features and behavior
when external voltages are not available to be sensed by the SENSEx pins. If external voltages are applied to
the VOUTx jumpers, the 0Ω resistors tying ENx to VOUTx must be removed.
Because the board is configured with ENx tied to VOUTx, the user should make sure VPULL_UP1 is low enough
that VSENSEx does not reach the channel-disabling voltage threshold (VTURN_OFF). If the user intends to
disable channels, it is recommended to do so by using R3, R4 and R5 to tie the SENSEx nodes to VLDO or
another stable voltage rail.
It is important to calculate the expected maximum SENSEx voltage both before and after the SENSEx hysteresis
current has been added, since the hysteresis current increases the voltage at the SENSEx node.
If VSENSEx is lower than the channel-disabling threshold before the SENSEx hysteresis current is added,
but above the threshold after the hysteresis current is added, then the channel(s) experience Enable-Disable
behavior. This state is not desirable or recommended and users should make sure that the channels are either
fully enabled or disabled.
2.3 Connector Descriptions
Primary Device Secondary Device
Designator Function Designator Function
J10
VIN_P
Power input connector for
VIN of the primary device. R42
VIN_S
0 Ohm resistor for tying
VIN of the primary and
secondary devices.
TP3 Test point TP22 Test point
J5
PULL_UP1_P
Power input connector for
PULL_UP1 of the primary
device.
R41
PULL_UP1_S
0 Ohm resistor for tying
PULL_UP1 of the primary
and secondary devices.
TP5 Test point TP24 Test point
J2
PULL_UP2_P
Power input connector for
PULL_UP2 of the primary
device.
R38
PULL_UP2_S
0 Ohm resistor for tying
PULL_UP2 of the primary
and secondary devices.
TP7 Test point TP35 Test point
J6, J23
GND
Power input connector for
GND of the primary device.
GND power connections are shared between primary and secondary
devices.
TP26, TP27,
TP28, TP29,
TP30, TP31,
TP32, TP33
Test point
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Primary Device Secondary Device
Designator Function Designator Function
J24 VOUT1_P Input connector for an
external VOUT rail to be
monitored by SENSE1 of the
primary device.
J55 VOUT1_S Input connector for an
external VOUT rail to be
monitored by SENSE1 of the
secondary device.
J31 GND J62 GND
J28
SENSE1_P
Probe test point J57
SENSE1_S
TP13 Test point TP38 Test point
J25 VOUT2_P Input connector for an
external VOUT rail to be
monitored by SENSE2 of the
primary device.
J56 VOUT2_S Input connector for an
external VOUT rail to be
monitored by SENSE2 of the
secondary device.
J32 GND J63 GND
J29
SENSE2_P
Probe test point J58
SENSE2_S
Probe test point
TP14 Test point TP39 Test point
J33 VOUT3_P Input connector for an
external VOUT rail to be
monitored by SENSE3 of the
primary device.
J65 VOUT3_S Input connector for an
external VOUT rail to be
monitored by SENSE3 of the
secondary device.
J39 GND J70 GND
J37
SENSE3_P
Probe test point J68
SENSE3_S
Probe test point
TP18 Test point TP45 Test point
J34 VOUT4_P Input connector for an
external VOUT rail to be
monitored by SENSE4 of the
primary device.
J66 VOUT4_S Input connector for an
external VOUT rail to be
monitored by SENSE4 of the
secondary device.
J40 GND J71 GND
J38
SENSE4_P
Probe test point J69
SENSE4_S
Probe test point
TP19 Test point TP46 Test point
TP1
EN1_P
Test point TP20
EN1_S
Test point
J3 Probe test point J42 Probe test point
J1 Output connector for EN1 of
the primary device.
J41 Output connector for EN1 of
the secondary device.
J4 GND J43 GND
TP2
EN2_P
Test point TP21
EN2_S
Test point
J8 Probe test point J45 Probe test point
J7 Output connector for EN2 of
the primary device.
J44 Output connector for EN2 of
the secondary device.
J9 GND J46 GND
TP4
EN3_P
Test point TP23
EN3_S
Test point
J12 Probe test point J48 Probe test point
J11 Output connector for EN3 of
the primary device.
J47 Output connector for EN3 of
the secondary device.
J13 GND J49 GND
TP8
EN4_P
Test point TP34
EN4_S
Test point
J18 Probe test point J51 Probe test point
J14 Output connector for EN4 of
the primary device.
J50 Output connector for EN4 of
the secondary device.
J22 GND J52 GND
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Primary Device Secondary Device
Designator Function Designator Function
J15, J16, J17 DLY_TMR_P
Shunt for DLY_TMR resistor
configuration of the primary
device.
J53 DLY_TMR_S
Shunt for DLY_TMR
resistor configuration of the
secondary device.
J19, J20, J21 REG_TMR_P
Shunt for REG_TMR resistor
configuration of the primary
device.
J54 REG_TMR_S
Shunt for REG_TMR
resistor configuration of the
secondary device.
TP11
UP_P
Test point TP41
UP_S
Test point
J26 Probe test point J60 Probe test point
TP17
DOWNb_P
Test point TP42
DOWNb_S
Test point
J36 Probe test point J61 Probe test point
TP6 HYS_P Test point TP25 HYS_S Test point
TP15
FAULTb_P
Test point TP43
FAULTb_S
Test point
J30 Probe test point J64 Probe test point
TP16
SEQ_DONE_P
Test point TP44
SEQ_DONE_S
Test point
J35 Probe test point J67 Probe test point
TP12
PWRGD_P
Test point TP40
PWRGD_S
Test point
J27 Probe test point J59 Probe test point
TP9 VLDO_P Test point TP36 VLDO_S Test point
TP10 REFCAP_P Test point TP37 REFCAP_S Test point
TP47 RESET Test point External RESET will apply to both the primary and secondary device.
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3 Implementation Results
Test results are shown below for the following features:
1. Sequence UP and DOWN thresholds
2. ENx Delay Time
3. SENSEx Regulation Timer
4. Disabling Channels
5. External System RESET
3.1 Default Configuration Results
The following tests were performed using the TPS7H3014EVM-CVAL in the default configuration with VIN=12V
and PULL_UP1=PULL_UP2=1.8V or 3.3V (indicated by voltage seen on the ENx, PWRGD, SEQ_DONE, and
FAULT signals). All UP and DOWN sequences were initiated by raising or lowering VIN, as shown in the first two
tests, unless stated otherwise.
3.2 Sequence UP and DOWN Thresholds
VIN>10.2V initiates sequence UP. EN1 goes HIGH after DLY_TMR (12.35ms) expires.
Figure 3-1. VIN Rising, Initiate Sequence UP
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VIN<6V initiates sequence DOWN. EN2 goes LOW after DLY_TMR (12.35ms) expires.
Figure 3-2. VIN Falling, Initiate Sequence DOWN
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3.3 Delay Timer
The shunt and resistor used on the DLY_TMR pin set the delay time that occurs between when the condition for
an ENx signal to transition HIGH or LOW is met and when the ENx signal transitions.
Figure 3-3. Sequence UP, 23ms Delay
Figure 3-4. Sequence DOWN, 23ms Delay
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Figure 3-5. Sequence UP, 12ms Delay
Figure 3-6. Sequence DOWN, 12ms Delay
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Figure 3-7. Sequence UP, DLY_TMR Floating
Figure 3-8. Sequence DOWN, DLY_TMR Floating
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3.4 Regulation Timer
In the following tests, SENSE3 is tied to GND to prevent reaching the VON3 threshold before the Regulation
Timer expires. Sequence DOWN is initiated automatically by the device when REG_TMR expires. This time is
set by the jumper and resistor used on the REG_TMR pin. If REG_TMR is floating, the Regulation Timer does
not expire, and the device waits indefinitely for a condition that changes the state.
Figure 3-9. Regulation Timer Expiration, 23ms
Figure 3-10. Regulation Timer Expiration, 12ms
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Figure 3-11. Sequence UP, REG_TMR Floating
Figure 3-12. Sequence DOWN, REG_TMR Floating
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3.5 Disabled Channels
The following tests were performed with SENSE3 and SENSE4 tied to 3.3V to disable channels 3 and 4.
Figure 3-13. Sequence UP, CH3-4 Disabled
Figure 3-14. Sequence DOWN, CH3-4 Disabled
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3.6 Externally Induced System RESET
The following test was performed using a FET to ground the SENSE1 pin to induce a FAULT. This can be
done if an external system RESET signal is desired by the user. CH3 and CH4 were disabled during this test
for convenience of displaying the results. Applying 3.3V to the gate of the FET circuitry shown in the "Optional
External Reset" section of the EVM Schematic induces the external RESET. If used, it is recommended to
choose a FET with low leakage to minimize the error it introduces to the SENSEx ON and OFF thresholds.
Figure 3-15. Sequence UP
Figure 3-16. External System RESET
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4 Hardware Design Files
4.1 Schematics
Default EVM Schematic
1
TPS7H3014HFT/EM
SENSE1
2SENSE2
3SENSE3
4SENSE4
17
PULL_UP2
DOWN
16
22
EN1
21
EN2
20
EN3
19
EN4
11 DLY_TMR
UP
8 5
REFCAP
IN
9
PWRGD 13
18
PULL_UP1
7FAULT
12
6HYS
SEQ_DONE
23
10
Thermal_pad
REG_TMR
15
VLDO
14
GND
U1
470nF
25V
C6
1µF
50V
C7
0.1%
50k
R9
10.0k
R10
619k
R11
1.17M
R12
VLDO_P
TP3
IN_P
1µF
50V
C3
J23
GND
J10
VIN
J5
1
PULL_UP1
2
Prima ry
PULL_UPx: 1.6 - 7V
J2
PULL_UP2
J15
1
2
J16
1
2
J17
10.0k
R13
619k
R14
1.17M
R15
1
2
J19
1
2
J20
1
2
J21
VLDO_P
R3
DN0
PR4
DNP
0
R5
DNP
0
GND
GND EN4_P
EN3_P
EN2_P
EN1_P
PWRGD_P
SEQ_DONE_P
TP7
PULL_UP2_P
TP5
PULL_UP1_P
TP6
HYS_P
TP9
VLDO_P
TP10
REFCAP_P
SENSE1_P
SENSE2_P
SENSE3_P
SENSE4_P
FAULTb_P
UP_P
DOWNb_P
0
DNPR8
PULL_UP2_P
VIN_P
PULL_UP1_P
GND
GND
10.0k
R23
50V
100pF
DNPC10
VLDO_P
0.1%
60.4k
R21
0.1%
34.8k
R25
0.1%
26.7k
R32
0.1%
130k
R35
GND
SENSE3_P
0.1%
49.9k
R22
0.1%
40.2k
R26
GND
SENSE2_P
0.1%
29.4k
R33
0.1%
90.9k
R36
GND
SENSE4_P
SENSEx Inputs of U1 (VSENSEx = 0 - 3.5V) SR_FAULTb Outpu t of U1
FAULTb_P
TP13
TP18
TP14
TP19
50V
100pF
DNPC11
50V
100pF
DNPC12
50V
100pF
DNPC16
50V
100pF
DNPC15
0
R17
EN1_P
0
R27
0
R18
0
R28
EN3_P
EN2_P
EN4_P
GND
GND
GND
GND
EN1_P
EN2_P
EN3_P
EN4_P
50V
100pF
DNPC1
4
P
9.9k
DNR1
50V
100pF
DNPC2
49.9k
P
DNR2
50V
100pF
DNPC4
49.9k
P
DNR6
50V
100pF
DNPC5
49.9k
P
DNR7
ENx Outpu ts of U1
GND
GND
PWRGD_P
SEQ_DONE_P
50V
100pF
DNPC9
4
P
9.9k
R24
DN
50V
100pF
DNPC13
49.9k
P
R31
DN
PWRGD & SEQ_DONE
GND
GND
VIN_P
0
R19 10.0k
R16
620
R20
909
R34
VIN_P
10.0k
R29
0
R30
UP_P
DOWNb_P
3.3µF
35V
C8
SEQUENCE UP/DOWN Inpu ts (0 - 7V)
VIN: 3 - 14V
J6
GND
GND
J28
SENSE1_P DNP
J24
VOUT1_P
J31
J25
VOUT2_P
J32
J40J39
J34
VOUT4_P
J33
VOUT3_P
Wait at least 2.8ms after VIN>UVLO_rise before
sequencing up.
t_startup_delay = 2.8ms
Default Schematic Values:
VOUT1_P=1.80 V with VON=90% and VOFF=10%
VOUT2_P=1.50 V with VON=90% and VOFF=10%
VOUT3_P=0.8 V with VON=90% and VOFF=10%
VOUT4_P=0.88 V with VON=90% and VOFF=10%
Note: 0-Ohm resistors connecting ENx to VOUTx are
for simplicity of testing when external voltages are not
available to sense. DNP if connecting external voltage
to VOUTx.
SENSE1_P
VUP > 0.6-V when VIN > 10.2 V (or 85% of 12-V)
VUP > 0.6-V after 3.7ms
VDOWNb < 0.5-V when VIN < 6 V (or 50% of 12-V)
J37
SENSE3_P DNP
J29
SENSE2_P DNP
J38
SENSE4_P DNP
J30
FAULTb_P DNP J27
PWRGD_P
DNP
J35
DNP SEQ_DONE_P
J26
UP_P DNP
J36
DOWNb_P DNP
J3
EN1_P
DNP
J1
EN1_P
J4
J8
EN2_P
DNP
J7
EN2_P
J9
J12
EN3_P
DNP
J11
EN3_P
J13
J18
EN4_P
DNP
J14
EN4_P
J22
TP1
EN1_P
TP11
TP12
PWRGD_P
TP2
EN2_P
TP4
EN3_P
TP8
EN4_P
TP16
SEQ_DONE_P
TP17
TP15
REG_TMR_P
DLY_TMR_P
HYS_P
REFCAP_P
50V
100pF
DNPC14
1µF
50V
C33
GND
1µF
50V
C34
GND
3
1
Channel-Disabling Connections
2
Q1
Idss_max: 50nA
DNP
CSD13380F3
GND
SENSE1_P
TP47
RESET
SH-J21
Optional External Reset
SH-J20SH-J19
SH-J17SH-J16SH-J15
1
P
0.0k
R70
DN
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SLVUCT9 – JANUARY 2024
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TPS7H3014EVM-CVAL Evaluation Module (EVM) 19
Copyright © 2024 Texas Instruments Incorporated

Seconda ry
1
TPS7H3014HFT/EM
SENSE1
2SENSE2
3SENSE3
4SENSE4
17
PULL_UP2
DOWN
16
22
EN1
21
EN2
20
EN3
19
EN4
11 DLY_TMR
UP
8 5
REFCAP
9IN
PWRGD 13
18
PULL_UP1
7FAULT
12
6HYS
SEQ_DONE
23
10
Thermal_pad
REG_TMR
15
VLDO
GND 14
U2
DNP
470nF
25V
DNPC22
1µF
50V
DNPC23
0.1%
50k
DNPR51
VLDO_S
R42
0
DNP
R41
0
DNP
R38
0
DNP
0
DNPR48
0
DNPR46
0
DNPR47
VLDO_S
TP22
IN_S
TP35
PULL_UP2_S
EN4_S
EN3_S
EN2_S
EN1_S
PWRGD_S
SEQ_DONE_S
TP24
PULL-UP1_S
10.0k
DNPR52
10.0k
DNPR53
TP37
REFCAP_S
TP36
VLDO_S
TP25
HYS_S
SENSE1_S
SENSE2_S
SENSE3_S
SENSE4_S
FAULTb_S
UP_S
DOWNb_S
Primary-Secondary Power Connections
0
PULL_UP2_S
DNPR54
TP41
UP_S
TP42
DOWNb_S
VIN_P
PULL_UP2_P
PULL_UP1_P PULL_UP1_S
FAULTb_P
FAULTb_S
UP_P
DOWNb_S
SEQ_DONE_S
DOWNb_P
R37
0
DNP
R40
0
DNP
R43
0
DNP
SEQ_DONE_P
UP_S
R45
0
DNP
TP26 TP27 TP28
GND
0.1%
49.9k
DNPR57
0.1%
40.2k
DNPR59
GND
SENSE1_S
GND
SENSE3_S
0.1%
40.2k
R65
DNP
0.1%
49.9k
DNPR68
GND
SENSE2_S
0.1%
14.5k
DNPR58
0.1%
34.8k
DNPR60
0.1%
1.00k
R66
DNP
0.1%
1.07k
DNPR69
GND
SENSE4_S
TP38
TP45
TP39
TP46
50V
100pF
DNPC24
50V
100pF
DNPC25
50V
100pF
DNPC32
50V
100pF
DNPC31
R55
0
DNP
R56
0
DNP
R64
0
DNP
R63
0
DNP
EN1_S
EN3_S
EN2_S
EN4_S
GND
GND
GND
GND
GND
EN1_S
EN2_S
EN3_S
EN4_S
50V
100pF
DNPC17
4
P
9.9k
DNR39
50V
100pF
DNPC19
49.9k
P
DNR44
50V
100pF
DNPC20
49.9k
P
DNR49
50V
100pF
DNPC21
49.9k
P
R50
DN
GND
GND
PWRGD_S
SEQ_DONE_S
50V
100pF
DNPC26
4
P
9.9k
DNR61
50V
100pF
DNPC30
49.9k
P
DNR67
GND
10.0k
R62
DNP
50V
100pF
DNPC29
VLDO_S
FAULTb_S
1µF
50V
DNPC18
GND
J42
EN1_S
DNP
J41
EN1_S
J43
J45
EN2_S
DNP
J44
EN2_S
J46
J48
Default Schematic Values:
VOUT1_S=1.50 V with VON=90% and VOFF=10%
VOUT2_S=1.00 V with VON=85% and VOFF=50%
VOUT3_S=1.20 V with VON=90% and VOFF=10%
VOUT4_S=1.20 V with VON=97% and VOFF=95%
EN3_S
DNP
J47
EN3_S
J49
J51
EN4_S
DNP
J50
EN4_S
J52
ENx Outpu ts of U2
GND Tes t Poin ts
Prima ry-Secondary "Dais y Chain " Connec tions
FAULTb Outpu t of U2
SENSEx Inputs of U2 (VSENSEx = 0 - 3.5V)
PWRGD & SEQ_DONE
J64
FAULTb_S DNP
J59
PWRGD_S
DNP
J57
SENSE1_S DNP
J55
VOUT1_S
J62
J58
SENSE2_S DNP
J56
VOUT2_S
J63
J68
SENSE3_S DNP
J65
VOUT3_S
J70
J69
SENSE4_S DNP
J66
VOUT4_S
J71
TP20
EN1_S
TP21
EN2_S
TP23
EN3_S
TP34
EN4_S
TP40
TP29 TP30 TP31 TP32 TP33
PWRGD_S
TP44
SEQ_DONE_S
TP43
1
2
J53
GND
50V
100pF
DNPC27
UP_S
J60
Sequence UP/DOWN Tes t Poin ts
UP_S
DNP
GND
50V
100pF
DNPC28
DOWNb_S
J61
DOWNb_S
DNP
1
2
J54
J67
DNP SEQ_DONE_S
HYS_S
DLY_TMR_S
REG_TMR_S
REFCAP_S
VIN_S
1µF
50V
DNPC35
GND
1µF
50V
DNPC36
GND
Channel-Disabling Connections
SH-J54SH-J53
Figure 4-1. Default EVM Schematic
Hardware Design Files www.ti.com
20 TPS7H3014EVM-CVAL Evaluation Module (EVM) SLVUCT9 – JANUARY 2024
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Copyright © 2024 Texas Instruments Incorporated