Texas Instruments TIDA-050038 Guide

LP873347
BUCK0 (3A)
BUCK1 (3A)
LDO0 (300mA)
LDO1 (300mA)
0.85 V
1.1 V
1.8 V
1.8V
1.2 V
3.3 V
0.9 V
1.8 V
MIPI CSI/DSI
i.MX 8M Mini, Nano
VDD_ARM
VDD_SOC, VDD_ANA_0P8, VDD_ARM_PLL_0P8,
VDD_USB_0P8, VDD_PCI_0P8
NVCC_DRAM
NVCC_SNVS_1P8
NVCC_xxx (1.8 V)
VDD_MIPI_1P2
NVCC_xxx (3.3 V)
VDD_MIPI_0P9
0.85 / 0.9 / 0.95 V
0.85 / 0.95 / 1.0 V
TPS6521825
2.8 V to 5.5 V
DCDC1 (1.8A)
DCDC2 (1.8A)
DCDC3 (1.8A)
LDO1 (400mA)
IN_BIAS
IN_DCDCx
IN_LDO
4
DCDC4 (1.6A)
Regulators
DCDC5 (25mA)
DCDC6 (25mA)
Backup (BU) Domain
CC
IN_BU
Load Switches 1-3
LS2
IN_LS2
LS3
IN_LS3
NOTE: DCDC5/6 are high-efficiency bucks for RTC
VDD_VPU, VDD_DRAM, VDD_GPU,
VDD_DRAM_PLL_0P8
NVDD_ANAx_1P8, VDD_24M_XTAL_1P8,
VDD_DRAM_PLL_1P8, VDD_ARM_PLL_1P8,
VDD_USB_1P8, VDD_PCI_1P8,
VDD_MIPI_1P8
3.3V (DCDC3)
0.8 V VDD_SNVS_0P8
5 V *VDD_VPU not included in Nano
connectors
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Integrated Power Supply Reference Design for NXP i.MX 8M Mini Processor
Design Guide: TIDA-050038
Integrated Power Supply Reference Design for NXP i.MX
8M Mini Processor
Description
TIDA-050038 is a system-on-module (SoM)
development board integrating two TI PMICs,
TPS6521825 and LP873347, with the NXP™ i.MX 8M
Mini Application Processor. The hardware design also
includes LPDDR4 SDRAM (2GB, x32-bit), QSPI NOR-
Flash (32MB), 16GB eMMC 5.1, 32-kHz RTC
oscillator, WiFi + Bluetooth module, and 9-channel
current monitoring. The SoM board is compatible with
the 8MMiniLPD4-EVK base board for full system
evaluation. This design is intended for any project that
is using the i.MX 8M Mini or i.MX 8M Nano processor
and requires evaluation of alternate power solutions.
Resources
TIDA-050038 Design Folder
TPS6521825 Product Folder
LP873347 Product Folder
INA3221 Product Folder
Search Our E2E™ support forums
Features
• SoM for rapid development of NXP i.MX8M Mini
systems
• Low-power modes and DVFS supported
• 9-channel current monitoring for DC-DCs and
LDOs
• Wi-Fi®+ Bluetooth®wireless connectivity
• Display connector (DSI), Camera connector (CSI),
additional peripherals on compatible base-board
• Selectable boot options (SD, eMMC, QSPI)
Applications
•ARM-based SoM/CoM
•Intrusion control panel
•Barcode scanner
•HVAC gateway
•Thermostat
•Building security gateway
•Panel PLC (HMI)
i
i
Order from RadiumBoards.
An IMPORTANT NOTICE at the end of this TI reference design addresses authorized use, intellectual property matters and other
important disclaimers and information.

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Integrated Power Supply Reference Design for NXP i.MX 8M Mini Processor
1 System Description
TIDA-050038 is first-and-foremost a reference design for powering the NXP i.MX 8M Mini processor from
the TPS6521825 and LP873347 PMICs. In order to show that the PMICs can power the processor, it
made the most sense to build a SoM board that is compatible with the existing base-board (8MMiniLPD4-
EVK), which includes a variety of peripheral connections to assist with development of various end
equipments. As a result, the base board contains all the large connectors for wired communication, a slot
for an SD Card containing the software image, as well as DIP switches for multiple BOOT options. The
SoM board, on the other hand, contains all the on-board memory and module for wireless communication.
Finally, to ensure the entire board is operational, we developed and tested software using the open-source
embedded Linux Yocto SDK to get started testing this design.
1.1 Key System Specifications
Table 1. Key System Specifications
PARAMETER SPECIFICATIONS DETAILS
Processor i.MX 8M Mini Dual-Core Applications Processor, MIMX8MM6DVTLZAA Section 2.2.1
PMICs
TPS6521825 PMIC for powering RTC (SNVS) domain with GPIOs to enable
external ICs, EEPROM pre-programmed with correct automatic sequencing for
i.MX 8M Mini & DVFS controlled by I2CSection 2.3.1
LP873347PMIC for delivering up to 3 A for core rails of i.MX 8M Mini processor,
OTP pre-programmed with correct sequencing for i.MX 8M Mini & DVFS
controlled by I2CSection 2.3.2
Memory 2GB x32-bit LPDDR4, 512Mb QSPI NOR-Flash (64MB), 8GB eMMC 5.0, SD
v3.0 interface Section 2.2.2
Wifi + Bluetooth Support WiFi + Bluetooth with Murata device. WiFi must support 802.11ac
standard and package size must fit in allotted board area. Section 2.2.3
Current Monitoring 3x TI INA3221 devices are used to monitor current through 9 rails in the system
(all DC-DCs and LDOs providing >100-mA of current) Section 2.3.3
USB2ANY header Debug method for PMIC separate from processor provided by USB2ANY (standard 100-mil pitch, 10-pin header). Must be outside of 2" x 2" square and
capable of being detached from PCB. Section 2.2.5
Manufacturability The PCB must be completed without HDI (high-density interconnect) manufacturing technologies. For example, via hole size ≥8 mil and no via-in-
pad allowed. Section 2.4
Compatibility Must be compatible with 8MMiniLPD4-EVK, using same high-density
connectors from SoM board to base-board Section 2.2.4
Size Main PCB (excluding USB2ANY header) must be same size as original
8MMiniLPD4-EVK SoM board, 2" x 2" Section 2.4.1

ESD Protection
ESD9L5.0ST5G
Boot Mode
Select
(2x 10POS)
ON/OFF
Switch
32K RTC
Oscillator
Ethernet PHY
AR8031
USB Debug
FT2232D
ESD Protection
ESD5B5.0ST1G
DAC
WM8524CGEDT
PCIe 2 (M.2)
eMMC 16GB
SDINBDG4-16G-I1
NOR Flash 32 MB
MT25QU256ABA1EW7
LPDDR4 x32 2GB
MT53D512M32D2DS-053
USB
Debug Port
Micro-B
Audio Card
(8-channel)
Expansion
Connector
I2C
Connector
PMIC
LP873347
Current &
Voltage
Monitoring
INA3221
To Processor I2C
i.MX 8M Mini
Applications
Processor
ARM CORTEX 4x A53 + M4
Power IN
WiFi + Bluetooth
LBEE5HY1MW
MIPI CSI
MINI SAS
RGMII
ON-OFF I/P
RESET I/P
RTC_XTALI
BOOT
MODE I/P
SDIO, UART
MIPI CSI
SDIO
JTAG
I2S
PCIe x 1
MMC 5.0
QSPI
LPDDR4 x32 2GB
UART
GPIO,
UART
I2C
USB2.x
Reset
Switch
GPIO,
SAI, I2C
MIPI DSI
MINI SAS
Micro-SD
Card SLot
USB OTG
TYPE-C JTAG
MIPI DSI
PMIC
TPS6521825
USB2.0
A
2 x USB2.0 A
SISO
ESD Protection
ESD5B5.0ST1G
On SOM Board
LEGEND:
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Integrated Power Supply Reference Design for NXP i.MX 8M Mini Processor
2 System Overview
2.1 Block Diagram
Figure 1. TIDA-050038 Block Diagram

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2.2 Design Considerations
This design is intended to show the ability of the TI power devices to provide power to the i.MX 8M Mini
processor and all of the peripheral ICs in a variety of designs. In order to verify this, we had to populate all
of these other ICs on the design, starting with the processor. All other devices necessary to build an
operational evaluation kit are included in this section. The power devices and other TI devices used in this
design are described in Section 2.3.
2.2.1 Processor - i.MX 8M Mini Applications Processor
The i.MX 8M Mini applications processor is a processor from NXP and is their first embedded multi-core
applications processor built using advanced 14LPC FinFET process technology providing more speed and
improved power efficiency. This processor specializes in optimized low power consuming state-of-the-art
media-specific features like high performance audio and video processing. The i.MX 8M Mini family of
processor features of five cores (Quad Arm® Cortex®-A53 core operating up to 1.8GHz and one Cortex®-
M4 core operating at 400MHz). It supports 32-bit/16bit LPDDR4 and DDR3L memory. This processor has
number of other interfaces like Ethernet, MIPI CSI, MIPI DSI, PCIe and also supports audio interfaces
such as I2S, AC97, TDM and S/PDIF. A detailed table listing the mapping for each pin on the iMX8MM
processor can be found in Appendix A.
DESCRIPTION MFG. PART NUMBER
IC, i.MX 8M Mini series , Quad ARM
Cortex-A53 core NXP MIMX8MM6DVTLZAA
2.2.2 i.MX 8M Mini Memory Interfaces
This project makes use of i.MX 8MM processor’s four different external memory interfaces using LPDDR4
SDRAM (2GB), 256Mb QSPI NOR-Flash (32MB), 16GB eMMC 5.1, and SD v3.0 (connector on base-
board).
2.2.2.1 LPDDR4
i.MX 8M Mini has a dedicated DDR memory controller which supports DDR3L, DDR4, and LPDDR4.
Memory speeds supported are LPDDR4 up to 1.5GHz, DDR4-2400 and DDR3L-1600. This design is
provided with two 2GB x32 LPDDR4 memory. Micron’s, MT53D512M32D2DS-053 WT:D is a 16Gb
LPDDR4 SDRAM (two die per package), currently used in this design. The memory interface comprises of
two channel of 16-bit data signals, along with separate command and address for each die.
DESCRIPTION MFG. PART NUMBER
IC, LPDDR4 SDRAM, 2GB, x32bit,
1866MHz, WFBGA-200 Micron MT53D512M32D2DS-053 WT:D

i.MX 8M Mini
DRAM_DQ[00-15]
DRAM_DM[0-1]
DRAM_DQS[0-1]_P/N
DRAM_AC04/05
DRAM_AC00
DRAM_AC02
DRAM_AC[08-13]
DRAM_DQ[16-31]
DRAM_DM[2-3]
DRAM_DQS[2-3]_P/N
DRAM_AC24/25
DRAM_AC20
DRAM_AC23
DRAM_AC[28-33]
RESET_n
MT53D512M32D2D
DQ[00-15]_B
DM[0-1]_B
DQS[0-1]_T/C_B
CK_T/C_B
CKE0_B
CS0_B
CA[0-5]_B
DQ[00-15]_A
DM[0-1]_A
DQS[0-1]_T/C_A
CK_T/C_A
CKE0_A
CS0_A
CA[0-5]_A
RESET_N
NVCC_DRAM VDD_DRAM
1V1 0V9
VDD1 VDD2 VDDQ
1V8 1V1 1V1
240E, 1%
1V1
ZQ0
VSS VSS
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Figure 2. LPDDR4 Interface
2.2.2.2 Quad SPI NOR Flash
i.MX 8M Mini processor supports Serial NOR Flash interface (QSPI). This project will support one Serial
NOR Flash. Micron’s, MT25QU256ABA1EW7-0SIT is a Serial NOR Flash Memory with a density 256Mb
(32MB) at clock frequency 133MHz and data through-put up to 90MB/s.
DESCRIPTION MFG. PART NUMBER
IC, NOR Flash, 32MB, 133MHz, SPI, 1.7-
2V, W-PDFN-8 Micron MT25QU256ABA1EW7-0SIT
2.2.2.3 eMMC iNAND
For this design an 8GB eMMC 5.1 compliant Memory is included. The interface diagram of eMMC with
processor is shown in . The part used here is a from Micron, P/N: MTFC8GAKAJCN- 4M IT. It supports
HS400 which is High Speed Mode supporting 400MBps @ 200MHz Dual Data Rate Bus.

SDINBDG4-16G-I1
DAT[0-7]
CLK
CMD
VSS
VCC VCCQ
3V3 1V8
i.MX 8M Mini
SD3_DATA[0-7]
SD3 CLK
SD3_STROBE
1V8
RCLK
SD3 CMD
VSS
NVCC_NAND
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For this design an 16GB eMMC 5.1 compliant Memory is included. The interface diagram of eMMC with
processor is shown in Figure 3. The part used here is from Western Digital, SDINBDG4-16G-I1. It
supports HS400 which is High Speed Mode supporting 400MBps at 200-MHz Dual Data Rate Bus with 8-
bit bus width.
DESCRIPTION MFG. PART NUMBER
IC, eMMC 16GB iNAND 7250 eMMC 5.1 Western Digital SDINBDG4-16G-I1
Figure 3. eMMC interface
2.2.2.4 Power for SD Card (connector on base-board)
In this design, there is an SD card connector on the base-board but the power supply for the SD card is
on the TIDA-050038 SoM board. The power supply to the SD Card is selectable between 1.8 V and 3.3 V
using a power multiplexer (mux), and both input voltages to the mux are provided by the TPS6521825
PMIC. The initial voltage applied to the VDD pin of the SD Card connector must always be 3.3 V and may
be lowered to 1.8 V after the SD Card confirms the allowed operating voltages. The power circuit for the
SD Card connector are shown in Figure 4.
DESCRIPTION MFG. PART NUMBER
IC, Power Switch P-Channel 2:1,
6WLCSP ON Semiconductor FPF1321UCX

VDD_3V3
TPS6521825
i.MX 8M Mini
SD2_DATA[0-3]
SD2_CLK
SD2_CD_B
SD2_WP
SD2_CMD
4
VDD_SD2
SD Card Voltage Mux
FPF1321
GPIO1_IO04
VINA
VINB
VOUT
VDD_1V8
VDD_SD2
EN
SEL
to B2B connector
DCDC4
DCDC3
NVCC_SD2
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Figure 4. SD Card Power
2.2.3 WiFi + Bluetooth Module
This design makes use of Murata’s WiFi + Bluetooth Module, the LBEE5HY1MW device. The interface
with the processor is through UART for Bluetooth and SDIO for WLAN (WiFi). The design provides a
coaxial connection for connection to the antenna, which is on the 8MMiniLPD4-EVK base-board.
DESCRIPTION MFG. PART NUMBER
Module, WiFi-Bluetooth, 802.11a/b/g/n/ac
2.4GHz/5GHz, BLE 5.0, Shielded, Type
1MW
Murata LBEE5HY1MW-230
2.2.4 High-Density Connectors
The connections between the TIDA-050034 SoM board and 8MMiniLPD4-EVK base-board are pre-defined
and there are no deviations possible from the electrical and mechanical specifications.
The interfaces contained on the base-board are as follows:
• SD Card connector
• Audio CODEC IC and connectors
• Ethernet PHY and connector
• USB-to-UART IC and connector
• USB Type-C connectors for main power supply and data transmission
• MIPI DSI connector
• MIPI CSI connector
• mini-PCI Express connector
• JTAG header

PMIC
LP873347
GPIO
SPI:MISO
GPIO
SPI:CS
SPI:MOSI
SPI:SCLK
SCL
SDA
I2C1:SCL
I2C1:SDA
10
8
6
4
2 1
3
5
7
9
10-Pin USB2ANY Connector
PMIC
TPS6521825
SCL
SDA
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2.2.5 USB2ANY Header
USB2ANY is TI MCU-based adaptor intended to allow a computer to control an electronic evaluation
module (EVM) via a USB connection. In this design, the I2C interface of USB2ANY is used to externally
monitor, control, and/or re-program the internal registers of PMIC. The wiring of the USB2ANY header is
shown in Figure 5.
DESCRIPTION MFG. PART NUMBER
Connector, Berg strip, 2x5, 2.54mm, 3A,
RA, TH FCI 68021-210HLF
Figure 5. USB2ANY Header Connections to PMIC I2C pins
2.3 Highlighted Products
2.3.1 TPS6521825 - Power Management IC
The TPS6521825 device is a Power Management IC (PMIC) specifically designed to support Arm Cortex
processors like the i.MX 8M Mini from NXP. The PMIC is a good fit for applications powered from a 5-V
supply or a Li-Ion battery. The IC consists of three adjustable step-down (buck) converters, one buck-
boost converter, one adjustable LDO and three load switches with two selectable current limit. The PMIC
supports undervoltage lockout (UVLO), over-temperature warning and shutdown, separate power-good
output for all regulators, programmable power sequencing for all regulators, and an I2C interface for
register reading and writing to the device.
For this project, PMIC powers NXP’s i.MX 8M Mini Processor, providing VDD_SNVS (0V8) and
NVCC_SNVS (1V8) from DCDC5 and DCDC6 respectively. It also provides VDD_SOC (0V85/0V9)
through DCDC1, NVCC_DRAM (1V1) through DCDC2 and voltages such as 3.3V, 1.8V digital, 1V8
Analog and 2V5 are also generated from this PMIC. The voltage 5V0 is send through load switches LS2
and LS3 to peripherals. However, 3V3 for PCIe, MIPI CSI, and MIPI DSI is powered through an external
buck converter located on the base-board. The power architecture and estimation can be viewed in
Section.5.3 and Section.5.1. The full power architecture of this design is shown in Figure 7.
The control pins of the TPS6521825 PMIC are shown connected to the processor in Figure 6, as well as
analog and digital input pins on the PMIC.

TPS6521825
SCL
SDA
nINIT
PFO
PWR_EN
PGOOD
i.MX 8M Mini
I2C1:SCL
I2C1:SDA
GPIO4_IO22
GPIO4_IO20
PWR_ON_REQ
POR_B
5 V
PFI
PB
5 V
RTC_RESET_VB
RTC_XTALI
GPIO1
LP873347_PG
PGOOD_BU/
GPIO3
DC34_SEL
GND
0 Ÿ
DNI*
5 V
To Processor
GPIO
LP873347 ENABLE
LP873347
SCL
SDA
nINIT
EN
PGOOD
i.MX 8M Mini
I2C1:SCL
I2C1:SDA
GPIO
LP873347 ENABLE
LP873347_PG
*DNI ±Do not install
AC_DET
EN
0 Ÿ
23.2 NŸ
0 Ÿ
100 NŸ
DNI*
100 NŸ
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Figure 6. TPS6521825 PMIC I/O Wiring to i.MX 8M Mini Processor
NOTE: PGOOD of both PMICs will be shorted together which creates a “wire-AND” connection due
to open drain topology (as in Fig.5) to drive the Power on Reset (POR_B) input pin on the
processor. The voltage for I2C operation is 1V8, so all the open drain input-outputs (SDA &
SCL) are connected to a 4.7-kΩpull-up resistor.
2.3.2 LP873347 - Core rail power up to 3 A
Figure 7 shows the full power architecture. For this design, two of the core rails will require up to 3 A of
current and two additional LDOs are required for MIPI to meet the power needs of the i.MX 8M Mini
processor. LP873347, an OTP variant of LP8733 base part number, is a PMIC that has been programmed
specifically to meet the power requirements of this application when paired with the TPS6521825 device.
The IC has two step-down converters with both single and dual phase regulators for improved efficiency
with higher power output. It also has two linear regulators (LDOs), general purpose digital output signals
and I2C interface.
For this project LP873347 will be used to generate 0V85/0V95/1V0 (dynamic voltage/frequency scaling, or
DVFS) for VDD_VPU, VDD_GPU and VDD_DRAM with an estimated approximate current output of 2.5 A
from BUCK0. The same DVFS voltages are required for VDD_ARM with an estimated current output of
2.2 A from BUCK1. The LDOs will provide 1V2 and 0V9 for VDD_MIPI_1V2 and VDD_MIPI_0V9
respectively. The input voltage to both PMICs is 5 V in this design. The LP873347 (slave PMIC) is
enabled by a GPIO of the TPS6521825 (master PMIC), and is disabled through a combination of signals
to ensure proper power-up and power-down sequencing for the processor.

LEGEND:
LP873347
BUCK0
0V85/0V95/1V0, 3A
BUCK1
0V85/0V95/1V0, 3A
LDO0
1V2, 300 mA
LDO1
0V9V, 300 mA
TPS6521825
DCDC1
0V85/0V9, 1.8 A
DCDC2
1V1, 1.8 A
DCDC3
3V3, 1.8 A
LS1
2V5, 920 mA
LS2
5V, 920 mA
DCDC5
1V0, 20 mA
DCDC4
1V8, 1.6 A
LDO
1V8, 400 mA
DCDC6
1V8, 20 mA
LS3
5V, 900 mA
i.MX 8M Mini
VDD_VPU, VDD_GPU,
VDD_DRAM
VDD_ARM
VDD_MIPI_1V2
VDD_MIPI_0V9
VDD_SOC
NVCC_DRAM
NVCC_3V3
VDD_SNVS
NVCC_1V8
VDDA_1V8
NVCC_SNVS
NVCC_ENET
LDO
TPS7A10
R1 R2
µSD Card
MIPI
DSI
MIPI
CSI
Expansion
Connector
Ethernet PHY
LPDDR4
eMMC WiFi +
BT
I2C
Connector
Expansion
Connector
Audio
DAC
PCIe
Clock
Generator
Audio
Card
eMMC
WiFi + BT
QSPI
MIPI
DSI
MIPI
CSI
PCIe
Clock
Generator
Ethernet
PHY
Ethernet PHY
RTC
Oscillator
DC-DC
3V3, 4A
MP2147
USB 2.0
Micro-B
USB to UART
FT2232D
USB OTG
Type-C
LOAD
SWITCH
(MOSFET)
DC-DC
5 V ±20 V, 8 A
MP8759GD
LOAD
SWITCH
(MOSFET)
USB
Type-C
3V3_PERI, 2.5 A
2V5, 0.085 A
1V8, 250 mA
3V3, 1.5 A
1V1, 1.5 A
1V0,
115 mA
3V3,
100 mA
1V8, 300 mA
0V8,
20 mA
GPIO1
GPIO3
5V0,
0.9 A
1V0,
20 mA
1V8,
3 mA
1V8, 500 mA
3V3, 100 mA
1V1, 1.5 A
0V85/0V9, 1.5 A
0V9, 300 mA
1V2, 300 mA
0V85/0V95/1V0, 2.2 A
0V85/0V95/1V0, 2.5 A
OR
5V0
GPIO3/
PGOOD_BU
GPIO1
32.768
kHz
Component on base-board
Peripheral connector
(ex: card slot, USB port)
2V5
Ethernet PHY
AR8031
LPDDR4
Ethernet
PHY
2V5,
150 mA
3V3
0 
Audio
Card
MIPI
DSI
MIPI
CSI
PCIe (M.2)
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Figure 7. TIDA-050038 Full Power Architecture
2.3.3 INA3221 - Current Monitor
To measure the live current information, a current sense circuit is integrated to the power section of this
design. The current sensing is done with the INA3221 device. There are three devices used to monitor all
the TPS6521825 and LP873347 PMIC power rails that are sourcing greater than 100-mA of current to the
system. The wiring is shown in Figure 8. The address pin A0 of the INA3221 device needs to be
terminated according to Table 2.

TPS6521825
LP873347
BUCK0
BUCK1
LDO0 INA3221
VIN+1
VIN+2
VIN+3
A0
VIN-1
VIN-2
VIN-3
SDA
SCL
PV
i.MX 8M Mini
VDD_VPU,VDD_GPU, VDD_DRAM
VDD_ARM
VDD_MIPI_1V2
I2C3: SDA
I2C3: SCL
GPIO
LDO1
INA3221
VIN+1
VIN+2
VIN+3
VIN-1
VIN-2
VIN-3
SDA
SCL
PV
A0
INA3221
VIN+1
VIN+2
VIN+3
VIN-1
VIN-2
VIN-3
SDA
SCL
PV
A0
VDD_MIPI_0V9
VDD_SOC
NVCC_DRAM
I2C3: SDA
I2C3: SCL
GPIO
NVCC_3V3
NVCC_1V8, VDD_1V8
VDDA_1V8
I2C1: SDA
I2C1: SCL
GPIO
DCDC1
DCDC2
DCDC3
DCDC4
LDO
*I2C = I2C Slave address is determined by the termination of A0 pin
I2C*
I2C*
I2C*
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Figure 8. INA3221 Current Sensor Wiring from PMIC to Processor
Table 2. INA3221 I2C Slave Address Options
7-BIT BINARY ADDRESS 7-BIT HEX ADDRESS ADDR PIN TERMINATION
1000000b 0x40 GND
1000001b 0x41 VS
1000010b 0x42 SDA
1000011b 0x43 SCL
2.4 System Design Theory
The full power architecture is the result of carefully estimating the power consumed by ICs on the board
and peripherals that can be connected to the board. The ideal power sequencing of the i.MX 8M Mini
processor must be known to ensure the power sequencing of the TPS6521825 and LP873347 PMICs is
correct, and the mechanisms for resetting the system must be determined. The I2C chain must be drawn
in its entirety to ensure there are no I2C address conflicts. The BOOT Mode settings must be mapped to
boot the processor using the intended memory storage IC. And finally, designing a SoM board to be
compatible with the 8MMiniLPD4-EVK comes with additional size constraints that must be considered.
PCB floor planning must be completed to make sure the layout of the board is reasonable. All of this
system design theory is taken into consideration in this section.

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2.4.1 Size constraints
The original SoM board that is placed on top of the 8MMiniLPD4-EVK is a 2-inch by 2-inch square PCB.
The only connection that is added to the PCB is the 10-pin USB2ANY header, which is considered to be
outside the 2" by 2" square requirement. All other devices on the PCB (PMIC, WiFi + Bluetooth module)
are functionally equivalent to the pre-existing SoM board design and therefore must fit in the same area on
the PCB. This includes the INA3221 current monitoring ICs, which are not a feature of the original EVK.
For more details on the floor planning, refer to Section 2.4.8.
2.4.2 Power Estimation
The TIDA-050038 SoM board is indirectly powered from the USB Type-C input (5V to 20V) to the base
board of the 8MMiniLPD4-EVK. This input is given to a DCDC converter (MP8759GD on base-board) for a
constant 5V output, which is the given as the input to the SoM board. This 5-V supply is provided directly
to the PMICs. The PMICs will generate voltages for 11 different rails. The load switches 2 and 3 are used
to power ICs and USBs with 5.0 V. The estimated current consumption for each rail is listed in Table 3.
Table 3. System Power Estimation
VOLTAGE (V) SUPPLY IC, RAIL NAME SUPPLY
CURRENT
(mA)
LOAD IC, RAIL NAME CURRENT
(mA) POWER (mW)
0.85/0.95/1.0 LP873347, BUCK0 3000 iMX8MM VDD_VPU,
VDD_GPU, VDD_DRAM 2500 2500
0.85/0.95/1.0 LP873347, BUCK0 3000 iMX8MM VDD_ARM 2200 2200
1.2 LP873347, LDO0 300 iMX8MM VDD_MIPI_1P2 10 12
0.9 LP873347, LDO1 300 iMX8MM VDD_MIPI_0P9 10 9
0.85 TPS6521825, DCDC1 1800 iMX8MM VDD_SOC 1050 893
1.1 TPS6521825, DCDC2 1800 iMX8MM NVCC_DRAM 500 550
LPDDR4 VDD2/VDDQ 365 402
3.3 TPS6521825, DCDC3 1800 iMX8MM NVCC_3V3 100 330
eMMC VCC 60 198
WiFi/BT VIO 200 660
Eth PHY VDD 65 215
1.8 TPS6521825, DCDC4 1600 i.MX8MM NVCC_1V8 500 900
LPDDR4 VDD1 3.6 6.5
QSPI VCC 35 63
eMMC VCCQ 245 441
WiFi/BT VBAT_x 800 1440
1.8(Analog) TPS6521825, LDO1 400 iMX8MM VDD_ANA_1V8 300 540
5 TPS6521825, LS2/3 1820 FTD2232D 30 150
2x USB2 Ports 1000 5000
0.8 TPS6521825, DCDC5 30 VDD_SNVS_0V8 10 8
1.8 TPS6521825, DCDC6 30 NVCC_SNVS_1V8 10 18
Total Estimated Power 17 W

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2.4.3 Power Sequencing
The i.MX 8M Mini processor power sequencing is shown in Figure 9. Before the majority of high current
rails are turned on, SNVS power must be available. NVCC_SNVS_1P8 and VDD_SNVS_0P8 are the first
rails to be enabled, then the RTC reset (RTC_RESET_B signal) should be asserted high, followed by
enabling the RTC clock. The LP873347 is enabled by GPIO1 of the TPS6521825 after VDD_SOC turns
on. The LP873347 timing for VDD_VPU_GPU_DRAM, VDD_MIPI_0P9, and VDD_ARM is pre-
programmed in the LP873347 device to match this timing requirement and delay VDD_MIPI_1P2 for the
appropriate amount of time. The TPS6521825 internally sequences the remaining rails, which are pre-
programmed into the EEPROM of the device. After all the rails are enabled and within the acceptable
voltage range, POR_B is asserted.

LEGEND:
NVCC_SNVS_1P8
(DCDC6)
VDD_SNVS_0P8
(DCDC5)
RTC_RESET_B
(GPIO3/
PGOOD_BU)
VDD_SOC*
(DCDC1)
32K_XTAL
(From EXT OSC)
VDD_VPU_GPU_DRAM
(BUCK0)
VDD_MIPI_0P9
(LDO1)
VDD_ARM
(BUCK1)
Analog 1V8**
LDO1)
PVCCx_1P8, NVCC_1V8
(DCDC4)
NVCC_DRAM
(DCDC2)
VDD_USB_3P3, NVCC_3V3
(DCDC3)
NVCC_ENET(2V5)
(LS1)
VDD_MIPI_1P2
(LDO0)
POR_B
** Analog 1V8 includes rails : VDD_ANAx_1P8, VDD_DRAM_PLL_1P8, VDD_MIPI_1P8,
VDD_24M_XTAL_1P8, VDD_USB_1P8, VDD_PCI_1P8 , VDD_ARM_PLL_1V8
* VDD_ANA_0P8, VDD_ARM_PLL_0P8, VDD_PCI_0P8, VDD_USB_0P8 rails also powered by DCDC1
Rails powered by TPS6521825
Rails powered by LP873347
Clock generted from External Oscillator
GPIO1
(LP873347
Enable)
2ms
2ms
20ms
2ms
2ms
2ms
2ms
2ms
10 ms
0.04 ms
**ms
NOTES:
(TPS6521825
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Figure 9. Required Power Sequence for i.MX 8M Mini Processor
2.4.4 Reset Scheme
The reset scheme for this project is shown in Figure 10. There are three RESET inputs to the PMICs. The
first is through a RESET switch, which is used as hardware reset, then a Watchdog reset is used and
finally a PMIC_ON_REQ from Processor. The PGOOD output of the PMICs are shorted (AND) together to
act as the POR_B for the processor. This signal is shared to the base-board.

i.MX 8M Mini
GPIO1_IO02
PMIC_ON_REQ
POR_B
GPIO
INT_B
RTC_RESET_B
ON/OFF
PMIC
TPS6521825
SW_WDOG
PMIC
LP873347
EN
PGOOD
nPFO
nINT
ON/OFF
RESET
32K_XTALI
To Baseboard RC Time
Delay
GPIO1
PGOOD_BU
GPIO3
PGOOD
PWR_EN
OSC
32.768KHz
0 
0 (DNI)
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Figure 10. Reset Scheme
Provide pull-up through 100-kΩresistor to VSNVS for PGOOD output. Both nPFO and nINT are pulled up to 1V8
using a 2.2-kΩresistor. The I2C lines are pulled up using a 4.7kΩresistor to 1V8.
2.4.5 I2C Device Chain
Figure 11 shows the I2C channel mapping from the processor to each slave device.

LEGEND:
USB2ANY
PMIC
LP873347
PCIe CLK Source
9FGV0241AK
M.2
Connector
Type C USB
PD PHY_1&2
PTN5110NHQZ
Addr: 0x60
USB1 ±Addr: 1010000X
Addr: 0x20
Current Sense
(3 INA3221 ICs)
PMIC
TPS6521825
Type C USB
Power SW_1&2
PTN5110NHQZ
IO Expander
PCA6416APW
Expansion
Connector
Audio Card
Expansion Connector
I2C
Connector
MIPI CSI
Connector
MIPI DSI
Connector
i.MX 8M Mini
USB2 ±Addr: 1010010X
USB1 ±Addr: 1010000X
USB2 ±Addr: 1010011X
Addr1: 0x40
Addr2: 0x41
Addr3: 0x42
Addr: 0x24
Addr: 0x68
NVCC_I2C
1V8 I2C1
I2C2
I2C2
VSS
Placed on SOM board Placed on base-board
Dashed border is for connector Solid border is for IC
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Figure 11. I2C Device Chain
2.4.6 Clock Scheme
Below is a list matching the required clock frequency to each IC that needs clocking on the SoM board.
• i.MX 8M Mini – 24MHz and 32.768 kHz
• LBEE5HY1MW (Wi-Fi/BT) – 32.768KHz

PMIC
LP873347
PMIC
TPS6521825
i.MX8MM
Application Processor
ARM Cortex
4xA53 + M4
32k
OSC
USB2ANY
LPDDR4
QSPI
NOR Flash
x
x
x
x
x
x
eMMC
WiFi + BT
x
x
x
x
x
x
B2B Connector 1
B2B Connector 2
ENET
CONN
ISENSE
INA3221
ISENSE
INA3221
ISENSE
INA3221
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All other clock sources are generated on the 8MMiniLPD4-EVK base-board.
2.4.7 BOOT Configuration
This design uses two BOOT configuration. BOOT Mode pins controlled by DIP switches 1-2 on SW1101
of the base-board are connected to dedicated BOOT_MODE0 and BOOT_MODE1 input pins of i.MX 8M
Mini processor. Along with these, there are 16 additional pins for setting the BOOT configuration
(BOOT_CFG0-15) which are dual-purpose pins (also SAI1_RXD0-7, SAI1_TXD0-7). These 16 pins are
controlled by DIP switches 5-10 of SW1101 and all 10 DIP switches of SW1102. All of the required BOOT
settings for TIDA-050038 are given in Table 4 (SW1101, switches 1-2) and Table 5 (SW1101, switches 5-
10; SW1102).
Table 4. SW1101[1-2] BOOT Mode Settings
BOOT_MODE[1..0] BIT 1 (SW1101[2]) BIT 0 (SW1101[1])
Fuses 0 0
Serial Download 0 1
Internal BOOT 1 0
Reserved 1 1
Table 5. SW1101, SW1102 BOOT Mode Settings for TIDA-050038
BOOT Device SW1101[1-10], SW1102[1-10] Settings
eMMC/SDHC3 01 10 11 00 01, 00 01 01 01 00
MicroSD/SDHC2 01 10 11 00 10, 00 01 10 10 00
NAND 01 10 00 00 00, 10 00 11 11 00
Download Mode 10 10 xx xx xx, xx xx xx xx x0
2.4.8 PCB Floor Planning
Figure 12 shows the floor planning for the top side of the PCB and Figure 13 shows the floor planning for
the bottom side of the PCB.
Figure 12. PCB Floor Planning (top) Figure 13. PCB Floor Planning (bottom)

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3 Getting Started, Testing Setup, and Test Results
3.1 Getting Started with Hardware and Software
3.1.1 Hardware
This section contains information about the initial set-up of the TIDA-050038 board, power-up options and
user interfaces. Figure 14 shows the top side of the fully assembled PCB with labels to help locate
connectors or switches on the boards.
Figure 14. Top of TIDA-050038 PCB with Labels
Figure 15 shows the bottom side of the fully assembled PCB with labels.

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Figure 15. Bottom of TIDA-050038 PCB with Labels
Below is a list of steps that must be followed to set up the hardware of the system:
1. Place and attach TIDA-050034 SoM board to the 8MMiniLPD4-EVK base-board with screws inserted
in the three holes at the corners of the PCB (Figure 16 and Figure 17).
2. Set the BOOT option using SW1101/SW1102 DIP switches (Figure 18).
3. Insert and push-in the µSD card into slot J701 on base-board, if µSD Card is used for BOOT
(Figure 19). Push-out to remove µSD card, when necessary.
4. Insert the USB micro-B cable into port J901 on base-board for UART debug in Terminal window
(Figure 20). Type-A plug connects to computer USB port.
5. Insert the DC adaptor with USB Type-C plug into J302 connector to supply power (Figure 21). The
recommended power supply is included in the 8MMiniLPD4-EVK.
6. Set SW101 in the ON position.
7. After BOOT is complete, connect the desired peripherals to the base-board. For example: RJ-45
Ethernet, mini-PCIe (Figure 22), 3.5-mm headphone jack, MIPI camera (CSI), MIPI display (DSI), USB
device.

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Figure 16. Placing SoM Board on Base-board, Aligning B2B Connectors
Figure 17. Screwing SoM Board to Base-board