Texas Instruments DEM-DAI3052A User manual

DEM-DAI3052A
User's Guide
September 2006 DAP
SLEU079

DEM-DAI3052A
User's Guide
Literature Number: SLEU079September 2006

Contents
1 Description ................................................................................................................ 51.1 Block Diagram ....................................................................................................... 61.2 Basic Connection and Operation ................................................................................. 71.2.1 Basic Connections and Configurations ................................................................. 71.2.2 Configuration Controls .................................................................................... 81.2.3 DEM-DAI3052A EVM Operation ....................................................................... 111.3 Typical Performance and Measurement Example ............................................................ 12
2 Schematics and Printed Circuit Boards ....................................................................... 192.1 DEM-DAI3052A Schematics ..................................................................................... 202.2 DEM-DAI3052A Bill of Materials (BOM) ........................................................................ 242.3 DEM-DAI3052A Printed Circuit Boards ........................................................................ 27
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List of Figures
1-1 DEM-DAI3052A Block Diagram ............................................................................................ 62-1 DEM-DAI3052A Power and Interface Section .......................................................................... 202-2 DEM-DAI3052A Digital Section (Digital Audio Interface) ............................................................. 212-3 DEM-DAI3052A Analog Section .......................................................................................... 222-4 DEM-DAI3052A DUT Section ............................................................................................ 232-5 DEM-DAI3052A Top Silkscreen .......................................................................................... 272-6 DEM-DAI3052A Top Copper ............................................................................................. 282-7 DEM-DAI3052A Bottom Copper .......................................................................................... 292-8 DEM-DAI3052A Form, Dimension, and Drill ............................................................................ 30
List of Tables
1-1 CN057: 3.3-V Power Source Selection ................................................................................... 81-2 SW001: SPDIF Input Selection ............................................................................................ 81-3 SW051: SPDIF Output Selection .......................................................................................... 81-4 SW052: SPDIF Output Source Signal Selection ........................................................................ 81-5 SW004: DIR1703 Clock Source Selection ............................................................................... 81-6 SW003: DIR1703 System Clock Selection ............................................................................... 81-7 SW005: DIT4096 Master Clock Selection ................................................................................ 81-8 JP001: DIR1703 Crystal Selection for Crystal Mode System Clock and Default Sampling Frequency .......... 91-9 SW003: DIR1703 Format Selection ....................................................................................... 91-10 SW005: DIT4096 Format Selection ....................................................................................... 91-11 SW006: DIT4096 Channel Status Information Control ................................................................. 91-12 SW053: Mode Control ....................................................................................................... 91-13 JP051: DOUTS or MDO Setting for Mode Control ..................................................................... 101-14 JP109: DUT (PCM3052A) V
CC
Supply Voltage Selection ............................................................ 101-15 JP110: MIC Input Configuration .......................................................................................... 101-16 JP101-104: Lineout LPF Selection ....................................................................................... 101-17 JP105, JP106: ADC Input Level Selection .............................................................................. 101-18 JP107: Bridge for PCM Audio Interface ................................................................................. 101-19 JP108: Bridge for Mode Control Interface .............................................................................. 10
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Chapter 1SLEU079 – September 2006
Description
The DEM-DAI3052A is an evaluation board for the PCM3052A, a 96-kHz, 24-bit stereoaudio coder/decoder (codec), with digital audio interface receiver/transmitter, opticaland coaxial interface, onboard clock generator, –6-dB amplifier with LPF for ADC and4-dB amplifier with LPF for DAC, switches or jumpers for mode or clock control, andinterface connector with PC for serial mode control.
The DEM-DAI3052A operates under 5-V and ±15-V analog power supplies, with1-Vrms or 2-Vrms unbalanced analog signal input and 2-Vrms unbalanced analogsignal output.
Topic .................................................................................................. Page
1.1 Block Diagram ............................................................................ 61.2 Basic Connection and Operation .................................................. 71.3 Typical Performance and Measurement Example .......................... 12
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1.1 Block Diagram
SW003
System Clock
Data Format
SW004
Clock Mode
JP001
X’tal Frequency
System Clock
DIR1703
24.576MHz
PCM3052A
(Slave Only)
LPF
2 Vrms
LPF
LPF
R-ch
LPF
JP107
JP105
JP106
DIT4096
SW005
System Clock
Data Format
SW006
74HCT244
OPT. IN
COAX. IN
S/PDIF Input
SW001
SW051
1/2 Vrms
S/PDIF Output
R-ch
OPT. OUT
COAX. OUT
DAC Output
ADC Input
MIC Input
Channel Status
L-ch
10/20 mVrms
L-ch
Block Diagram
Figure 1-1. DEM-DAI3052A Block Diagram
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1.2 Basic Connection and Operation
1.2.1 Basic Connections and Configurations
Basic Connection and Operation
•Install REGTEST_I2C and other programs attached to the EVM into the appropriate folder of the PCthat is used to control this EVM.•Confirm EVM settings. SW053 must be all OFF (High). JP051 SCL, SDA, MDO, and DOUTS must beOFF, OFF, OFF, and ON, respectively.•Connect the 5-V and ±15-V power supplies to V
CC
,±AV
CC
, and GND on CN051–CN055. If external3.3 V is used on CN056, jumper CN057 must be removed. The ±15-V power supplies are required for2-Vrms input and 2-Vrms output.•Connect the SPDIF input to CN059 (coaxial) or U053 (optical) and output to CN058 (coaxial) or U052(optical), and select coaxial or optical for SPDIF input and output using SW001 and SW051. Also,select the SPDIF output source from the analog-to-digital converter (ADC) output or thedigital-to-analog converter (DAC) input using SW052.•Select the system clock source from x’tal or SPDIF input recover clock using SW004, select thesystem clock using SW003 SCF1/0 for DIR1703 and using SW005 CLK1/0 for DIT4096, and select thesystem clock frequency for x’tal mode using JP001 setting.•Set the interface format (24-bit I
2
S) using SW003 FMT1/0 for DIR1703 and using SW005 FMT1/0 forDIT4096.
•Set the channel status for DIT4096 using SW006 if required. (It is not required for PCM3052Aevaluation.)
•Select the analog input/output configuration according to application interface, specifically, select theDUT PCM3052A V
CC
from 5 V or 4.5 V using JP109, the Mic input configuration of single ended ordifferential using JP110, the ADC input full scale from 2 Vrms or 1 Vrms using JP105/6, and the DACoutput LPF band width from 20 kHz or 40 kHz using JP101-104.
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1.2.2 Configuration ControlsBasic Connection and Operation
Table 1-1. CN057: 3.3-V Power Source Selection
CN057 DESCRIPTION
OFF 3.3 V must be supplied on CN056.ON 3.3 V must be supplied by on board regulator, U051 (default).
Table 1-2. SW001: SPDIF Input Selection
SW001 DESCRIPTION
COAX Select coaxial connector as SPDIF input (default)OPT Select optical connector as SPDIF input
Table 1-3. SW051: SPDIF Output Selection
SW051 DESCRIPTION
COAX Select coaxial connector as SPDIF outputOPT Select optical connector as SPDIF output (default)
Table 1-4. SW052: SPDIF Output Source Signal Selection
SW052 DESCRIPTION
REC Select DOUTS of PCM3052A, DAC inputDIT Select DIT4096 output, ADC output (default)
Table 1-5. SW004: DIR1703 Clock Source Selection
SW004 DESCRIPTION
X’tal SCKO (system clock out) is generated from crystal clock.PLL SCKO is generated from SPDIF recovery clock.AUTO Source clock of SCKO is automatically selected according to PLL lock state (default).
Table 1-6. SW003: DIR1703 System Clock Selection
SW003
DESCRIPTIONSCF1 SCF0
OFF (L) OFF (L) 128 f
S
OFF (L) ON (H) 256 f
S
(Default)ON (H) OFF (L) 384 f
S
ON (H) ON (H) 512 f
S
Table 1-7. SW005: DIT4096 Master Clock Selection
SW005
DESCRIPTIONCLK1 CLK0
OFF (H) OFF (H) 512 f
S
OFF (H) ON (L) 384 f
S
ON (L) OFF (H) 256 f
S
(default)ON (L) ON (L) Unused
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Basic Connection and Operation
Table 1-8. JP001: DIR1703 Crystal Selection for Crystal Mode System Clock and Default SamplingFrequency
JP001 DESCRIPTION
OPEN 6.144/12.288/18.432/24.576 MHz for 128 f
S
/256 f
S
/384 f
S
/512 f
S
, 48 kHzCSBIT 12.288/24.576/36.864/49.152 MHz for 128 f
S
/256 f
S
/384 f
S
/512 f
S
, 96 kHz (default)URBIT 11.2896/22.5792/33.8688/45.158 MHz for 128 f
S
/256 f
S
/384 f
S
/512 f
S
, 88.2 kHzEMFLG 5.6448/11.2896/16.9344/22.5792 MHz for 128 f
S
/256 f
S
/384 f
S
/512 f
S
, 44.1 kHzBFRAME 4.096/8.192/12.288/16.384 MHz for 128 f
S
/256 f
S
/384 f
S
/512 f
S
, 32 kHz
Table 1-9. SW003: DIR1703 Format Selection
SW003
DESCRIPTIONFMT1 FMT0
OFF (L) OFF (L) 16 bits MSB first, right justifiedOFF (L) ON (H) 24 bits MSB first, right justifiedON (H) OFF (L) 24 bits MSB first, left justifiedON (H) ON (H) 24 bits MSB first, I
2
S format (default)
Table 1-10. SW005: DIT4096 Format Selection
SW005
DESCRIPTIONFMT1 FMT0
OFF (H) OFF (H) 16-bit right justifiedOFF (H) ON (L) 24-bit right justifiedON (L) OFF (H) 24-bit I
2
S (default)ON (L) ON (L) 24-bit left justified
Table 1-11. SW006: DIT4096 Channel Status Information Control
(1)
SW006 DESCRIPTION
CSS Channel status data mode input (default: on)COPY-C Copy protect or channel status data input (default: on)U User data input (default: on)V Validity data input (default: on)L Generation status input (default: on)/AUDIO Audio data valid control input (default: on)/EMPH Pre-emphasis status input (default: off)BLSM Block start mode control input (default: off)BLS Block start I/O (default: off)
(1)
Control of these switches is not required for PCM3052A function and performance evaluation.
Table 1-12. SW053: Mode Control
SW053 DESCRIPTION
RESET Function control that is defined on RESET (default: off)MDI Function control that is defined on MDI (default: off)MC Function control that is defined on MC (default: off)ML Function control that is defined on ML (default: off)
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Basic Connection and Operation
Table 1-13. JP051: DOUTS or MDO Setting for Mode Control
JP051 DESCRIPTION
1/4 Change SCL configuration to MC configuration (default: off)2/4 Change SCA configuration to MD configuration (default: off)3/4 Enable MDO (default: off)4/4 Enable DOUTS (default: on)
Table 1-14. JP109: DUT (PCM3052A) V
CC
Supply Voltage Selection
JP109 DESCRIPTION
LEFT DUT V
CC
is supplied from external 5 V (default).RIFHT DUT V
CC
is supplied from onboard 4.5-V regulator
Table 1-15. JP110: MIC Input Configuration
JP110 DESCRIPTION
LEFT Single-ended microphone inputRIFHT Differential microphone input (default)
Table 1-16. JP101-104: Lineout LPF Selection
JP101,102,103,104 DESCRIPTION
OFF 40-kHz BWON 20-kHz BW (default)
Table 1-17. JP105, JP106: ADC Input Level Selection
JP105,106 DESCRIPTION
1 Vrms 1.06-Vrms full-scale voltage on ADC inputs (default)2 Vrms 2.12-Vrms full-scale voltage on ADC inputs
Table 1-18. JP107: Bridge for PCM Audio Interface
JP107 DESCRIPTION
ON All straps must be mounted for interfacing onboard SPDIF receiver/transmitter.All straps must be removed and connecting external audio interface signals on JP107 (signal) –OFF
JP111 (GND) for interfacing with external equipment.
Table 1-19. JP108: Bridge for Mode Control Interface
JP108 DESCRIPTION
ON All straps must be mounted for interfacing with PC via CN060.All straps must be removed and connecting external control interface signals on right-side ofOFF
JP108 for interfacing with external equipment.
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