Texas Instruments ADS8472EVM User manual

User's GuideSLAU203 – February 2007
ADS8472EVM
This user guide describes the characteristics, operation, and use of the ADS8472 16-bit, 1MHz parallelinterface analog-to-digital converter evaluation board. A complete circuit description as well as schematicdiagram and bill of materials is included.
Contents1 EVM Overview ............................................................................................................... 22 Introduction ................................................................................................................... 23 Analog Interface .............................................................................................................. 24 Digital Interface .............................................................................................................. 55 Power Supplies .............................................................................................................. 76 Using the ADS8472EVM .................................................................................................... 87 ADS8472EVM BoM ........................................................................................................ 108 ADS8472EVM Layout ..................................................................................................... 129 ADS8472EVM Schematic ................................................................................................. 15
List of Figures
1 Input Buffer, Bipolar Fully Differential Input .............................................................................. 42 Top – Layer 1 ............................................................................................................... 123 Ground Plane – Layer 2 ................................................................................................... 134 Power Plane – Layer 3 .................................................................................................... 135 Bottom – Layer 4 ........................................................................................................... 146 Top Overlay ................................................................................................................ 147 Bottom OverLay ............................................................................................................ 15
List of Tables
1 Analog Input Connector ..................................................................................................... 32 Analog Circuitry Jumper Configurations .................................................................................. 43 Pinout for Parallel Control Connector P3 ................................................................................. 54 Jumper Settings .............................................................................................................. 55 Data Bus Connector P2 ..................................................................................................... 66 TSW1100 Connector ........................................................................................................ 67 Pin out for Converter Control Connector, J6 ............................................................................. 78 Power Supply Test Points .................................................................................................. 79 Power Connector, J5, Pin Out ............................................................................................. 710 Bill of Materials ............................................................................................................. 10
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1 EVM Overview
1.1 Features
1.2 Related Documentation from Texas Instruments
2 Introduction
3 Analog Interface
EVM Overview www.ti.com
•Full-featured Evaluation Board for the high-speed ADS8472 16-bit, 1MSPS single channel, parallelinterface SAR type Analog to Digital Converters.•On board signal conditioning•On board Reference•Input and Output Digital Buffers•On board decoding for stacking multiple EVMs.
To obtain a copy of any of the following TI documents, call the Texas Instruments Literature ResponseCenter at [phone] or the Product Information Center (PIC) at [phone]. When ordering,identify this booklet by its title and literature number. Updated documents can also be obtained throughour website at www.ti.com .
Data Sheets: Literature Number:ADS8472 SLAS514REF3240 SBVS058REF3225 SBVS058SN74AHC138 SCLS258SN74AHC245 SCLS230SN74AHC1G04 SCLS318THS4031 SLOS224THS4032 SLOS224
The ADS8472 is 16-bit, 1-MSPS analog to digital converter (ADC) with an internal 4.096V reference and apseudo-bipolar, fully differential input. The device is a capacitor based successive approximation register(SAR) converter with an inherent sample and hold. The ADS8472 has a 16-bit and 8-bit parallel interfacebus options, allowing a variety of processors to interface easily with it.
The ADS8472EVM is an evaluation and demonstration platform for the ADS8472 ADC. The board is aflexible design that allows the user to choose among many different analog signal conditioning, referenceand interface modes. The standardized I/O headers not only allow the user to quickly interface to FPGAs,but also to the full line of microprocessors and digital signal processors from Texas Instruments.
The analog-to-digital converter accepts a pseudo-bipolar differential input. A pseudo-bipolar differentialsignal is a fully differential signal that has a common-mode voltage such that the voltage on each input isalways equal to or above zero volts. The common mode voltage should typically be half the referencevoltage. The peak-to-peak amplitude on each input leg can be as large as the reference voltage.
The positive leg of the input signal can be applied at connector P1 pin 2 (shown in Table 1 ) or via centerpin of SMA connector J1. Likewise the negative input signal can be applied at P1 pin1 or via center pin ofSMA connector J2.
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3.1 Input Signal Conditioning
www.ti.com Analog Interface
Table 1. Analog Input Connector
Description Signal Name Connector.Pin# Signal Name Description
Inverting Input Channel — P1.1 P1.2 + Non-inverting Input ChannelReserved N/A P1.3 P1.4 N/A ReservedReserved N/A P1.5 P1.6 N/A ReservedReserved N/A P1.7 P1.8 N/A ReservedReserved N/A P1.9 P1.10 N/A ReservedPin tied to Ground AGND P1.11 P1.12 N/A ReservedPin tied to Ground AGND P1.13 P1.14 N/A ReservedN/A Reserved P1.15 P1.16 N/A ReservedPin tied to Ground AGND P1.17 P1.18 N/A ReservedPin tied to Ground AGND P1.19 P1.20 REF+ External Reference Input
The analog input circuitry, consisting of the THS4031 and THS4032 operational amplifiers, allow the userto install passive components to configure it for positive or negative gains, as well as input range scaling,filtering and leveling translation (e.g., adding a DC offset). The operational amplifiers are housed in anindustry standard SOIC footprint. This enables the user to replace the THS4031 with a plethora of dualand single supply amplifiers housed in an SOIC package.
When choosing the driver amplifier the user should consider the following requirements. The drivingamplifier must be able to settle the input to 16-bit level within the sample time of the converter. It shouldhave Total Harmonic Distortion(THD) characteristics comparable to or better than the ADS8472. Lastly,the noise generated by the amplifier needs to be as low as possible, so as not to degrade the SNRperformance of the ADS8472.
The noise coming through the driver amplifiers are filtered by a single-pole filter using R = 10.2 Ωand C=2.2nF with a corner frequency of 7MHz. The 5.1- Ωseries resistor works with the capacitor to filter the inputsignal, but also isolates the amplifier from the capacitive load. The 2200-pF capacitor to ground at theinput of the ADC works with the series resistor to filter the input signal, behaves like a charge reservoir,and provides a path to ground for high-frequency noise and the low small input current transient whichoccurs when the device switches from hold to sample mode. This external filter capacitor works with theamplifier to charge the internal sampling capacitor during sampling mode.
The supplies to the input amplifier are selectable with solder jumper pad SJP3, and SJP4. Shorting acrosspads 1 and 2 will ground the negative rail. Shorting across pads 2 and 3 will tie the negative supply of theamplifiers to the voltage applied at node –VCC.
When deciding on supply rails, a good rule of thumb is to add at least 2V of head room on either side toachieve optimal performance. For example, if the signal applied to the amplifier is 0–4V, then the amplifierrails should be at least –2V and +6V. At the 16-bit performance node, the amplifier introduced distortioncan become significant. Be aware when reading amplifiers data sheets that they may not be specified withlarge amplitudes. Therefore, it may not be possible to surmise from a cursory glance how well theamplifier will behave in system.
Single-ended signal sources are readily available, but rarely allow the user to evaluate the fullperformance of 16-bit converters. Although the ADS8472EVM can be configured for this inputconfiguration, the factory set configuration of the input circuitry is for a bipolar fully differential input signal.The necessary DC component to offset the signal at U7 is generated by U4. U4 is the low noise THS4032amplifier. It can be configured to further filter the reference voltage IC, U2, and provide positive or negativegains. The ADS8472EVM leaves the factory with potentiometer, R24, set to 2.048V and set as shown inFigure 1 .Table 1 indicates how the solder pad jumpers should be set to select from the various supplyand input options for the analog driver circuitry. The copy of the schematic for the ADS8472EVM isattached at the end of this document.
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-6 V
+6 V
THS4031
2.2 nF
(+)IN
0.1 Fm
C11
+Vin
-4 V to +4 V
C45
R39
U6
0-4 V
R36
3
2
7
4
6
-6 V
+6 V
THS4031 (-)IN
C13
R40
U7
0-4 V
R38
3
2
7
4
6
4.096 V
-Vin
-4 V to +4 V
4.096 V
R8
R31
R37
R21
75 W
C12
0.1 Fm
5.1 W
1000 W
1000 W
5.1 W
C14
0.1 Fm
75 W
0.1 Fm
1000 W
1000 W
3.2 Reference
Analog Interface www.ti.com
Figure 1. Input Buffer, Bipolar Fully Differential Input
Table 2. Analog Circuitry Jumper Configurations
Reference 1-2 2-3 DescriptionDesignator
SJP1 Installed †
(1)
Not Installed Select onboard reference (REF3230).Not Installed Installed Select user-supplied reference at P1 pin 20.SJP2 Installed †
(1)
Not Installed Set REFIN pin of ADS8472 to on-chip (internal) reference voltage.Not Installed Installed Set REFIN pin of ADS8472 to reference selected by SJP1.SJP3 Installed Not Installed Set U6 operational amplifier minus rail supply to ground.Not Installed Installed †
(1)
Set U6 operational amplifier minus rail supply to –VCC.SJP4 Installed Not Installed Set U7 operational amplifier minus rail supply to ground.Not Installed Installed †
(1)
Set U7 operational amplifier minus rail supply to –VCC.SJP5 Not Installed N/A Short voltage node –DC to U6 pin 2 via R35.SJP6 Not Installed N/A Short –IN pin of U5 to ground at C45.
(1)
† Indicates factory installed option.
The ADS8472 can operate with an external reference voltage in the range of 3.0V up to 4.2V. It generatesan on-chip 4.096V reference voltage. The ADS8472EVM allows the user to select the external referencevoltage from three sources. The first option is to use the internally generated 4.096V from the ADC. Theother two options are to select from the on board reference (U1) or a user supplied voltage applied at pin20 of P1. Refer to Table 1 for solder jumper options for selecting from the various reference sources.
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4 Digital Interface
www.ti.com Digital InterfaceThe reference voltage provides the scale factor for the conversion result. The input voltage is measuredagainst the reference voltage. It is imperative the reference voltage be clean, low noise and welldecoupled.
The default configuration is to use the internal on-chip reference.
The ADS8472EVM is designed for easy interfacing to multiple platforms. The digital interface input andoutput signals of the converter are on connectors P2, P3, J6 and J7. These are 0.1" on-centers, plug andsocket connectors, allowing the user to plug the ADS8472EVM onto the various motherboard interfacecards from Texas Instruments, or ribbon cable onto the user development board. The following tables listthe connector pin outs.
Table 3. Pinout for Parallel Control Connector P3
Description Signal Name Connector.Pin# Signal Name Description
Not connected DC_CS P3.1 P3.2 + Non-inverting Input ChannelReserved N/A P3.3 P3.4 GND GroundReserved N/A P3.5 P3.6 GND GroundAddress line 0 A0 P3.7 P3.8 GND GroundAddress line 1 A1 P3.9 P3.10 GND GroundAddress line 2 A2 P3.11 P3.12 GND GroundReserved N/A P3.13 P3.14 GND GroundReserved N/A P3.15 P3.16 GND GroundConvert Start DC_CONVST P3.17 P3.18 GND GroundInterrupt pin INTC P3.19 P3.20 GND Ground
Conversions are initiated on the falling edge of the convert start signal. It is therefore critical whenmeasuring large amplitude and/or high frequency input signals, the user provide a clean low jitter convertstart pulse.
The convert start signal can be applied to the ADS8472 from the decoder outputs or from connector P3pin 17. Address decoder SN74ACH138 is used to generate the read ( RD) and conversion start ( CONVST)signals to the converter. Jumpers W3 and W4 allow the user to assign these two signals to differentaddresses in memory. This allows for the stacking of up to two ADS8472EVMs into processor memory.See Table 3 for jumper settings. If the user applies a convert start signal directly on P3 pin 17, then besure to short W6 pins 1-2. This will bypass the decoder output selected by position of W4.
Note, the evaluation module does not allow chip select ( CS) line of the converter to be assigned todifferent memory locations. It is therefore suggested the CS line be grounded or wired to an appropriatesignal of the processor.
Table 4. Jumper Settings
Reference Description 1-2 2-3Designator
W1 Set digital buffer supply voltage to +5V Installed Not installedSet digital buffer supply voltage to +3.3V Not installed Installed †
(1)
W2 Apply inverted BUSY to INTC signal Installed †
(1)
Not installedApply BUSY signal to INTC signal Not installed InstalledW3 Set RD signal to add[0x3] Installed Not installedSet RD signal to add[0x4] Not installed InstalledW4 Set CONVST signal to add[0x1] Installed Not installedSet CONVST signal to add[0x2] Not installed Installed
(1)
† Indicates factory installed option.
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Digital Interface www.ti.com
Table 4. Jumper Settings (continued)
Reference Description 1-2 2-3Designator
W5 Set DC_CS to CS of ADS8472 Installed N/AW6 Set DC_CONVST to CONVST of ADS8472 Installed InstalledSet decoder output to CONVST of ADS8472 Not installed Installed
The data bus is available at connector P2, see Table 4 for pin out information.
Table 5. Data Bus Connector P2
Description Signal Name Connector.Pin# Signal Name Description
Reserved N/A P2.1 P2.2 GND GroundReserved N/A P2.3 P2.4 GND GroundData Bit 0 DB0 P2.5 P2.6 GND GroundData Bit 1 DB1 P2.7 P2.8 GND GroundData Bit 2 DB2 P2.9 P2.10 GND GroundData Bit 3 DB3 P2.11 P2.12 GND GroundData Bit 4 DB4 P2.13 P2.14 GND GroundData Bit 5 DB5 P2.15 P2.16 GND GroundData Bit 6 DB6 P2.17 P2.18 GND GroundData Bit 7 DB7 P2.19 P2.20 GND GroundData Bit 8 DB8 P2.21 P2.22 GND GroundData Bit 9 DB9 P2.23 P2.24 GND GroundData Bit 10 DB10 P2.25 P2.26 GND GroundData Bit 11 DB11 P2.27 P2.28 GND GroundData Bit 12 DB12 P2.29 P2.30 GND GroundData Bit 13 DB13 P2.31 P2.32 GND GroundData Bit 14 DB14 P2.33 P2.34 GND GroundData Bit 15 DB15 P2.35 P2.36 GND Ground
In addition to interfacing to the various micro controller and digital signal processors from TexasInstruments, this board also plugs into the TSW1100 card. The TSW1100 is a PC-based data capturecard. J7 connector is installed to allow the user to plug the ADS8472EVM directly and collect data foranalysis.
Table 6. TSW1100 Connector
Description Signal Name Connector.Pin# Signal Name Description
Ground Ground J7.1 J7.2 N/C Not ConnectedGround Ground J7.3 J7.4 N/C Not ConnectedGround Ground J7.5 J7.6 D0 Data Bit 0 (LSB)Ground Ground J7.7 J7.8 D1 Data Bit 1Ground Ground J7.9 J7.10 D2 Data Bit 2Ground Ground J7.11 J7.12 D3 Data Bit 3Ground Ground J7.13 J7.14 D4 Data Bit 4Ground Ground J7.15 J7.16 D5 Data Bit 5Ground Ground J7.17 J7.18 D6 Data Bit 6Ground Ground J7.19 J7.20 D7 Data Bit 7Ground Ground J7.21 J7.22 D8 Data Bit 8Ground Ground J7.23 J7.24 D9 Data Bit 9Ground Ground J7.25 J7.26 D10 Data Bit 10
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5 Power Supplies
www.ti.com Power Supplies
Table 6. TSW1100 Connector (continued)
Description Signal Name Connector.Pin# Signal Name Description
Ground Ground J7.27 J7.28 D11 Data Bit 11Ground Ground J7.29 J7.30 D12 Data Bit 12Ground Ground J7.31 J7.32 D13 Data Bit 13Ground Ground J7.33 J7.34 D14 Data Bit 14Ground Ground J7.35 J7.36 D15 Data Bit 15Ground Ground J7.37 J7.38 N/C Not ConnectedGround Ground J7.39 J7.40 INTc Trigger Clock
This evaluation module provides direct access to all the analog-to-digital converter input control and outputsignals via connector J6, see Table 6 .
Table 7. Pin out for Converter Control Connector, J6
Description Signal Name Connector.Pin# Signal Name Description
Chip Select Signal CS J6.1 J6.2 GND GroundRead Signal RD J6.3 J6.4 GND GroundConvert Start Signal CONVST J6.5 J6.6 GND GroundByte Signal BYTE J6.7 J6.8 GND GroundRESERVED RESERVED J6.9 J6.10 GND GroundBusy Signal BUSY J6.11 J6.12 GND Ground
The EVM accepts four power supplies.•A dual ±VA DC supply for the dual supply op-amps. Recommend ±6VDC supply.•A single +5.0 V DC supply for analog section of the board (A/D + Reference).•A single +5.0V or +3.3V DC supply for digital section of the board (A/D + address decoder + buffers).
There are two ways to provide these voltages.1. Wire in the voltages at test points on the EVM. See Table 8 .
Table 8. Power Supply Test Points
Test Point Signal Description
TP6 +BVDD Apply +3.3VDC or +5.0VDC. See ADC datasheet for full range.TP3 +AVCC Apply +5.0VDC.TP4 +VA Apply +6.0VDC. Positive supply for amplifier.TP5 –VA Apply -6.0VDC. Negative supply for amplifier.
2. Use the power connector J5, and derive the voltages elsewhere. The pinout for this connector isshown in Table 9 . If using this connector, then set W1 jumper to connect +3.3VD or +5VD fromconnector to +BVDD. Short between pins 1-2 to select +5VD, or short between pins 2-3 to select+3.3VD as the source for the digital buffer voltage supply (+BVDD).
Table 9. Power Connector, J5, Pin Out
Signal Power Connector – J5 Signal
+VA(+6V) 1 2 –VA (-6V)+5VA 3 4 N/CDGND 5 6 AGNDN/C 7 8 N/C+3.3VD 9 10 +5VD
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6 Using the ADS8472EVM
6.1 As a Reference Board
6.2 As a Prototype Board
6.2.1 Evaluation Board
6.2.2 EVM and TSW1100 Capture Card
Using the ADS8472EVM www.ti.com
The ADS8472EVM serves the functions of being a reference design, a prototyping board, and finally as ansoftware test platform.
As a reference design, the ADS8472EVM contains the essential circuitry to showcase the analog-to-digitalconverter. This essential circuitry includes the input amplifier, reference circuit, and buffers. TheADS8472EVM analog input circuit is optimized for a wide bandwidth signal; therefore, the user may needto adjust the input buffer circuitry to better suit your needs. In AC-type applications where signal distortionis a concern, the user should use high quality capacitors such as Mica, polypropylene or COGs typecapacitors in the signal path. In applications where the input is multiplexed, the A/D input resistor andcapacitor may need to be adjusted further.
As a prototype board, the ADS8472EVM features amplifiers in a standard 8-pin SOIC package and manyresistor pads scattered around allowing the user to experiment with a host of circuits, as needed. TheADS8472EVM can be used to evaluate both dual- and single-supply amplifiers in both inverting andnon-inverting configurations. The ADS8472EVM comes installed with a dual-supply amplifier which allowsthe user to take advantage of the full input voltage range of the converter. For applications that requiresignal supply operation and smaller input voltage range, the THS4031 can be replaced with thesingle-supply amplifier like the OPA300 or OPA350. Pad jumper SJP3 should be shorted between pads 1and 2. This shorts the minus supply pin of the amplifier to ground. Positive supply voltage can be appliedat test point TP4 or at connector J5 pin 1.
There are two common methods to evaluate the ADS8472EVM’s performance.1. EVM used as a stand-alone system. The user is responsible for capturing and analyzing the data,typically via a logic analyzer and analysis software (LABView, MATLAB, etc)2. EVM used in conjunction with TI’s TSW1100 data capture card,http://focus.ti.com/docs/toolsw/folders/print/tsw1100.html
The following section discusses method two.
The User’s Guide for the data capture card is available at http://focus.ti.com/lit/ug/slau155a/slau155a.pdf .Refer to this guide for detailed information and set-up instructions.
The ADS8472EVM mates with the TSW1100 card via J7. There are two data ports available on thecapture card, the reference designators are J1 and J2. The ADS8472EVM can be plugged into either port.
The TSW1100 is a data capture card and provides no control signals to the ADS8472. The ADS8472requires a CONVST pulse to begin digitizing the signal. Therefore, the user must provide a CONVST tothe ADS8472 at P3 pin 17 or at J6 pin 5 on the ADS8472EVM. In this case, it is recommended theADS8472 be operated in the CS and RD tied low mode, as this requires only CONVST to toggle. To shortthis signals to ground, simply short across pins 1 and 2, and 3 and 4 of J6, respectively. The digitized datais available on the data bus at the end of every busy cycle. In this operating scheme, the inverted BUSYsignal is used to trigger the TSW1100 card to read the data bus. To avoid line contention remove jumpersfrom W3, W4, W5, and W6 on the ADS8472EVM.
The ADS8472 EVM is supported with the TSW1100 capture card firmware release 1.x. Please use theADS1610EVM entry as a template for acquiring data from the ADS8374EVM. Due to hardware limitationson the TSW1100 platform, data capture from the ADS8472EVM is restricted to 1MSPS minimum.
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6.3 As a Software Test Platform
www.ti.com Using the ADS8472EVM
As a software test platform, connectors P1, P2, and P3 plug into the parallel interface connectors of the5-6K interface board. The 5-6K interface board sits on the C5000 and C6000 digital signal processorstarter kits (DSK). The ADS8472EVM is mapped then into the processor’s memory space. The 5-6kinterface board also provides an area for signal conditioning. This area can be used to install applicationcircuit(s) for digitization by the ADS8472 analog-to-digital converter. For more information, see the 5-6KInterface Board user’s guide (SLAU104 ) .
For the software engineer, the ADS8472EVM provides a simple platform for interfacing to the converter.The EVM provides standard 0.1-inch headers and sockets to wire into prototype boards. The user needonly provide three address lines (A2, A1, and A0) and address valid line ( DC_CS) to connector P3. Toselect which address combinations generate RD and CONVST, set jumpers as shown in Table 3. Recallthat the Chip Select ( CS) signal is not memory-mapped; therefore, it must be controlled by ageneral-purpose pin or shorted to ground at J6 pin 1. If address decoding is not required, the EVMprovides direct access to converter data bus by P3 and control by J6.
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7 ADS8472EVM BoM
ADS8472EVM BoM www.ti.com
The following table contains a complete Bill of Materials for the ADS8472EVM. The schematic diagram isalso provided for reference. Contact the Product Information Center or e-mail [email protected]for questions regarding this EVM.
Table 10. Bill of MaterialsQTY Value REF DES Footprint MFG MFG Part No. Description
3 0 R16 R17 R33 603 Panasonic – ERJ-3GEY0R00V RES 0 Ω1/16W 5% 0603 SMDECG orAlternate
2 0 R19 R22 805 Panasonic – ERJ-6GEY0R00V RES 0.0 Ω1/10W 5% 0805 SMDECG orAlternate
2 5.1 R39 R40 805 Panasonic – ERJ-6GEYJ5R1V Resistor 5.1 Ω1/8W 5% 0805ECG orAlternate
3 33 R5 R25 R26 603 Yageo America 9C06031A33R0FKHFT RES 33.0 Ω1/10W 1% 0603 SMDor Alternate
3 49.9 R1–R3 603 Panasonic - ERJ-3EKF49R9V RES 49.9 Ω1/10W 1% 0603 SMDECG orAlternate
2 75 R36 R38 805 Yageo America 9C08052A75R0FKHFT RES 75.0 Ω1/8W 1% 0805 SMDor Alternate
3 300 R4 R27 R29 603 Yageo America RC0603FR-07300RL RES 300 Ω1/10W 1% 0603 SMDor Alternate
4 1k R8 R21 R31 805 Yageo America 9C08052A1001JLHFT RES 1.0k Ω1/8W 5% 0805 SMDR37 or Alternate
5 10k R41–R45 603 Panasonic - ERJ-3EKF1002V RES 10.0k Ω1/10W 1% 0603 SMDECG orAlternate
1 10k R46 805 Panasonic - ERJ-6GEYJ103V RES 10k Ω1/8W 5% 0805 SMDECG orAlternate
2 NI R6 R28 603 Not Installed Not Installed
11 NI R7 R9–R13 805 Not Installed Not InstalledR18 R20 R32R34 R35
2 47 RP1 RP2 CTS_742 CTS 742C163470JTR RES ARRAY 47 Ω16TERM 8RES SMDCorporation
1 1K RP3 CTS_742 CTS 742C163102JTR RES ARRAY 1k Ω16TERM 8RES SMDCorporation
1 51 RP4 CTS_742_4RES CTS 742C083510JTR RES ARRAY 51 Ω8TERM 4RES SMDCorporation
1 10K R24 BOURNS_3296Y Bourns Inc. 3296Y-1-103 POT 10k Ω3/8" SQ CERM SL MT
4 MMZ2012 L1–L4 805 TDK MMZ2012R601A FERRITE CHIP 600 Ω500MA 0805R601A Corporation
13 1000pF C28–C36 603 TDK C1608X7R1H102K CAP CER 1000pF 50V XR7 10% 0603C62–C65 Corporation orAlternate
1 2200pF C45 603 TDK C1608C0G1H222J CAP CER 2200pF 50V C0G 5% 0603Corporation orAlternate
6 0.1 µF C66–C71 603 TDK C1608X7R1E104K CAP CER 0.10 µF 25V X7R 10% 0603Corporation orAlternate
6 0.1 µF C9–C14 805 TDK C2012X7R1H104K CAP CER 0.10 µF 50V X7R 10% 0805Corporation orAlternate
2 0.47 µF C1 C2 603 TDK C1608X5R1A474K CAP CER 0.47 µF 10V X5R 10% 0603Corporation orAlternate
2 1 µF C5 C7 603 TDK C1608X5R1A105KT CAP CER 1.0 µF 10V X5R 10% 0603Corporation orAlternate
10 ADS8472EVM SLAU203 – February 2007Submit Documentation Feedback

www.ti.com ADS8472EVM BoM
Table 10. Bill of Materials (continued)QTY Value REF DES Footprint MFG MFG Part No. Description
2 1 µF C41 C42 805 TDK C2012X7R1E105K CAP CER 1.0 µF 25V X7R 0805 T/RCorporation orAlternate
8 2.2 µF C20–C27 603 TDK C1608X5R1A225MT CAP CER 2.2 µF 6.3V X5R 20% 0603Corporation orAlternate
1 10 µF C40 805 TDK C2012X5R0J106M CAP CER 10 µF 6.3V X5R 20% 0805Corporation orAlternate
8 10 µF C48–C55 1206 TDK C3216X5R1C106M CAP CER 10 µF 16V X5R 20% 1206Corporation orAlternate
1 22 µF C6 805 TDK C2012X5R0J226M CAP CER 22 µF 6.3V X5R 20% 0805Corporation orAlternate
1 47 µF C37 1206 TDK C3216X5R0J476M CAP CER 47 µF 6.3V X5R 20% 1206Corporation orAlternate
15 NI C3 C4 C8 C15 603 Not Installed Not Installed Multilayer CeramicC16 C18 C19C46 C47C56–C61
4 NI C38 C39 C43 805 Not Installed Not Installed 1/10W 0805 Chip ResistorC44
1 REF3230 U1 6-SOT(DBV) Texas REF3230AIDBVR 3.0V 4ppm/ °C, 100 µA SOT23-6 SeriesInstruments (Bandgap) Voltage Reference
1 REF3240 U2 6-SOT(DBV) Texas REF3240AIDBVR 4.096V 4ppm/ °C, 100 µA SOT23-6 SeriesInstruments (Bandgap) Voltage Reference
1 NI U3 8-SOP(D) Not Installed Not Installed SOIC reference alternate
1 THS4032 U4 8-SOP(D) Texas THS4032CD 100-MHz Low Noise Voltage-FeedbackInstruments Amplifier, Dual
1 ADS8472 U5 48-QFN(RGZ) Texas ADS8472IBRGZR ADS8472 16-bit 1MSPS A/DInstruments
2 THS4031 U6 U7 8-SOP(D) Texas THS4031IDR 100-MHz Low-noise high-speed amplifierInstruments
4 SN74AHC U8–U11 20-TSSOP(PW) Texas SN74AHC245PWR Octal Bus Transceiver, 3-State245PWR Instruments
1 SN74AHC U12 5-SOT(DBV) Texas SN74AHC1G04DBVR Single Inverter Gate1G04DBV Instruments
1 SN74AHC U13 16-TSSOP(PW) Texas SN74AHC138PWR 3-Line to 8-Line Decoder / Demultiplexer138PWR Instruments
2 SMA_PCB J1 J2 SMA_JACK Johnson 142-0701-301 Right Angle SMA Connector_MT Components
Inc.
2 NI J3 J4 SMA_JACK Not Installed Not Installed MaCom #5002-5003-10/Amphenol #901-144
1 5X2X.1 J5 5X2X.1_SMT_SOCKET Samtec SSW-105-22-S-D-VS 0.025" SMT Socket – Bottom side of PWB
1 Samtec TSM-105-01-T-D-V-P 0.025" SMT Plug - Top side of PWB
1 6X2X.1 J6 6X2X.1_SMT_PLUG_ Samtec TSM-105-01-T-D-V-P 0.025" SMT Plug - Top side of PWB& _SOCKET
1 40-PIN J7 20X2X.1 Tyco 4-103149-0-20 CONN HEADR BRKWAY 0.100 40POS R/AHeader Electronics/Am
p
2 10X2X.1 P1 P3 10X2X.1_SMT_PLUG_ Samtec SSW-110-22-S-D-VS 0.025" SMT Socket - Bottom side of PWB& _SOCKET
1 18X2X.1_ P2 18X2.1_SMT_PLUG_ Samtec SSW-118-22-S-D-VS 0.025" SMT Socket - Bottom side of PWBSMT_PLU & _SOCKETG_
& _SOCKE
T
1 Samtec TSM-118-01-T-D-V-P 0.025" SMT Plug - Top side of PWB
2 SJP2 SJP5 SJP6 SJP2 NOT NOT INSTALLEDINSTALLED
4 SJP3 SJP1–SJP4 SJP3 NOT NOT INSTALLED NOT INSTALLED NOT INSTALLEDINSTALLED
SLAU203 – February 2007 ADS8472EVM 11Submit Documentation Feedback

8 ADS8472EVM Layout
ADS8472EVM Layout www.ti.com
Table 10. Bill of Materials (continued)QTY Value REF DES Footprint MFG MFG Part No. Description
5 3POS_JU W1–W4 W6 3pos_jump Samtec TSW-103-07-L-S 3 Position Jumper _ 0.1" spacingMPER
1 2POS_JU W5 2pos_jump Samtec TSW-102-07-L-S 2 Position Jumper _ 0.1" spacingMPER
8 TP_0.025 TP3–TP7 TP9 test_point2 Keystone 5000K–ND TEST POINT PC MINI 0.040"D REDTP11 TP12 Electronics
6 TP_0.025 TP1 TP2 TP8 test_point2 Keystone 5001K–ND TEST POINT PC MINI 0.040"D BLACKTP10 TP13 ElectronicsTP14
This section contains the EVM layout.
Figure 2. Top – Layer 1
12 ADS8472EVM SLAU203 – February 2007Submit Documentation Feedback

www.ti.com ADS8472EVM Layout
Figure 3. Ground Plane – Layer 2
Figure 4. Power Plane – Layer 3
SLAU203 – February 2007 ADS8472EVM 13Submit Documentation Feedback

ADS8472EVM Layout www.ti.com
Figure 5. Bottom – Layer 4
Figure 6. Top Overlay
14 ADS8472EVM SLAU203 – February 2007Submit Documentation Feedback

9 ADS8472EVM Schematic
www.ti.com ADS8472EVM Schematic
Figure 7. Bottom OverLay
Schematic diagram pages are appended to this user's guide.
SLAU203 – February 2007 ADS8472EVM 15Submit Documentation Feedback

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BlockDiagram.sch
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ADS8471/ADS8472EVM Block Diagram
6485904
-IN
+IN
B_CS B_RD B_CONVST B_BYTE B_BUS18/16 BUSY DB[17...0]
EXT_REF
A alog-to-Digital Co verter
B_DB[17...0]
DB[17...0]
CS RD CONVST BYTE BUS18/16 B_BUSY
BUSY
B_CS
B_RD
B_CONVST
B_BYTE
B_BUS18/16
+AVCC
+VA
-VA
+BVDD
INTc DC_CS
A0 A1 A2
DC_CONVST
Power & Digital Buffer
B_DB[17...0]
DB[17...0]
+BVDD
TP3
TP6
TP5
TP4
CS
RD
CONVST
BYTE
BUS18/16
B_BUSY
ADC Co trol
12
34
56
78
9
11
10
12
J6
TP1
TP2
1 2
3 4
5 6
7 8
9 10
J5
+VA -VA
+5VD
AGND
+5VA
DGND
+3.3VD
W1
Lijoy Philipose
Lijoy Philipose
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
P3
Parallel Control
INTC
A1
DC_CS
A2
ADC Data Bus
1
122
3
344
5
566
7
788
9
910 10
11
11 12 12
13
13 14 14
15
15 16 16
17
17 18 18
19
19 20 20
21
21 22 22
23
23 24 24
25
25 26 26
27
27 28 28
29
29 30 30
31
31 32 32
33
33 34 34
35
35 36 36
P2
B_DB0
B_DB1
B_DB2
B_DB3
B_DB4
B_DB5
B_DB6
B_DB7
B_DB8
B_DB9
B_DB10
B_DB11
B_DB12
B_DB13
B_DB14
B_DB15
B_DB16
B_DB17
A alog I put
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
P1
J1
J2
DC_CONVST
A0
12
34
56
78
910
1112
1314
1516
1718
1920
2122
2324
2526
2728
2930
3132
3334
3536
3738
3940
J7
40-PIN eader
B_DB17
B_DB16
B_DB15
B_DB14
B_DB13
B_DB12
B_DB11
B_DB10
B_DB9
B_DB8
B_DB7
B_DB6
B_DB5
B_DB4
B_DB3
B_DB2
INTc
TSW1100 Co ector

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A alog-to-Digital Co verter
A
DATE: 31-Ja -2009
A alog-to-Digital Co verter
6485904
C32
1000pF
C5
1uF
C22
2.2uF
C30
1000pF
C34
1000pF
C23
2.2uF
C26
2.2uF
C35
1000pF
C27
2.2uF
C36
1000pF
+5VCC
+5VCC
+5VCC
+5VCC
C20
2.2uF
C28
1000pF
+5VCC
C21
2.2uF
C29
1000pF
+VBD
B_CS
B_RD
B_CONVST
B_BYTE
BUSY
B_BUS18/16
+VBD
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB8
DB9
DB10 DB11 DB12 DB13 DB14 DB15
C31
1000pF
C24
2.2uF
+5VCC
BUSY
DB[17...0]
B_CS
B_RD
B_BYTE
B_CONVST
B_BUS18/16
DB[17...0]
31
2
SJP2
C6
22uF
R33
0
C25
2.2uF
C33
1000pF
R1
49.9
Lijoy Philipose
Lijoy Philipose
C37
47uF
+VCC
-VCC
C9
0.1uF
C10
0.1uF
R27
300
R4
300
3
2
1
84
U4A
T S4032
5
6
7
U4B
T S4032
R28
NI
R29
300
C3
NI
C38
NI C4
NI
C39
NI
R16
0
R6
NI
-VCC
+VCC
C13
0.1uF
C14
0.1uF
3
2
6
7 4
51
8
U7
T S4031
3
2
6
74
5 1
8
U6
T S4031
C12 0.1uF
C11 0.1uF
+VCC
-VCC
R9 NI
-IN
+IN
R37 1k
R21 1k
R35
NI
R31 1k
R32
NI
12
SJP5
-DC
R38 75
R36 75
+DC
R20
NI
R34
NI
R12
NI
R18
NI
R7
NI
R39
5.1
R40
5.1
C45
2200pF
C47
NI
C46
NI
R19
0
R22
0
*
*
*C0G*
*
*
C41
1uF
C42
1uF
R8
1k
R26
33
C19
NI
C18
NI
R25
33
+DC
-DC
R2
49.9
R3
49.9
C44 NI
C43 NI
R17
0
+VBD 1
BUS18/16 2
BYTE 3
CONVST 4
RD 5 CS 6
+VA 7
AGND 8 AGND 9
+VA 10
REFM 11 REFM 12
REFIN
13
REFOUT
14
NC
15
+VA
16
AGND
17
+IN
18
-IN
19
AGND
20
+VA
21
+VA
22
AGND
23
AGND
24
+VA
25
AGND
26
AGND
27
DB17
28
DB16
29
DB15
30
DB14
31
DB13
32
DB12
33
DB11
34
DB10
35
+VBD
36
BDGND 37
DB9 38
DB8 39
DB7 40
DB6 41
DB5 42
DB4 43
DB3 44
DB2 45
DB1 46
DB0 47
BUSY 48
U5
ADS8472
DB16 DB17
EXT_REF
31
2
SJP1
J3
J4
31
2
SJP3
31
2
SJP4
R10
NI
R13
NI
R24 10K
12
SJP6
C40
10uF
+5VCC
C1
0.47uF
GND_F
1
GND_S
2
ENABLE
3IN 4
OUT_S 5
OUT_F 6
U1
REF3230
+5VCC
C2
0.47uF
GND_F
1
GND_S
2
ENABLE
3IN 4
OUT_S 5
OUT_F 6
U2
REF3240
NC
1
+VIN
2
EN
3
GND
4NC 5
VREF 6
NC 7
NC 8
U3
NI
C8
NI
+5VCC
C7
1uF
**VRE4141**
R5
33
R11
NI

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Power & Digital Buffer
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Power Supply & Digital Buffer Circuit
6485904
B_DB[17...0]
1 16
2 15
3 14
4 13
5
9
12
6
8
10
11
7
RP2
47
+VBD
/OE
DIR
A1
A2
A3
A4
A5
A6
A7
A8
B1
B2
B3
B4
B5
B6
B7
B8
VCC
GND
U10
SN74A C245PWR
+VBD C70
0.1uF
1 16
2 15
3 14
4 13
5
9
12
6
8
10
11
7
RP1
47
+VBD
/OE
DIR
A1
A2
A3
A4
A5
A6
A7
A8
B1
B2
B3
B4
B5
B6
B7
B8
VCC
GND
U9
SN74A C245PWR
+VBD
C67
0.1uF
DB[17...0]
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
B_DB15
B_DB14
B_DB13
B_DB12
B_DB11
B_DB0
B_DB10
B_DB1
B_DB9
B_DB2
B_DB8
B_DB3
B_DB7
B_DB4
B_DB6
B_DB5
B_BUSY
1 16
2 15
3 14
4 13
5
9
12
6
8
10
11
7
RP3
1K
/OE
DIR
A1
A2
A3
A4
A5
A6
A7
A8
B1
B2
B3
B4
B5
B6
B7
B8
VCC
GND
U8
SN74A C245PWR
+VBD
C66
0.1uF
CS
RD
CONVST
BYTE
R42
10k
R43
10k
R44
10k
+VBD
R45
10k
R41
10k
BUSY
B_CS
B_RD
B_CONVST
B_BYTE
B_BUS18/16
DB[17...0]
B_DB[17...0]
B_CS
B_BYTE
B_CONVST
B_RD
B_BUS18/16
2 4
53
U12
SN74A C1G04DBV
+VBD C68
0.1uF W2
INTc
Lijoy Philipose
Lijoy Philipose
A1
B2
C3
G1 6
G2A 4
G2B 5
Y0
15
Y1
14
Y2
13
Y3
12
Y4
11
Y5
10
Y6
9
Y7
7
VCC 16
GND
8
U13
SN74A C138PWR
A0
A1
A2
A0
A2
A1
+VBD
C69
0.1uF
+VBD
1
3
2W4
1
3
2W3
DC_CS
R46
10k
+VBD
DC_CS
+VBD
/OE
DIR
A1
A2
A3
A4
A5
A6
A7
A8
B1
B2
B3
B4
B5
B6
B7
B8
VCC
GND
U11
SN74A C245PWR
C71
0.1uF
RD
B_DB16
B_DB17
RP4
51
+VBD
DB17
DB16
L3
MMZ2012R601A
C15
NI
C16
NI
C60
NI
C61
NI
TP11
TP12
TP10
+VCC
-VCC
C50
10uF
C51
10uF
C64
1000pF
C65
1000pF
+VA
-VA
TP13
L4
MMZ2012R601A
TP7 +5VCC
C58
NI
C56
NI
TP8
C48
10uF
C62
1000pF
+AVCC
L1
MMZ2012R601A
TP9 +VBD
C59
NI
C57
NI
TP14
C49
10uF
C63
1000pF
+BVDD
L2
MMZ2012R601A
CS
RD
CONVST
BYTE
BUS18/16
C55
10uF
C54
10uF
C52
10uF
C53
10uF
W6
DC_CONVST
W5
DC_CS

EVALUATION BOARD/KIT IMPORTANT NOTICE
Texas Instruments (TI) provides the enclosed product(s) under the following conditions:This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATION PURPOSESONLY and is not considered by TI to be a finished end-product fit for general consumer use. Persons handling the product(s) must haveelectronics training and observe good engineering practice standards. As such, the goods being provided are not intended to be completein terms of required design-, marketing-, and/or manufacturing-related protective considerations, including product safety and environmentalmeasures typically found in end products that incorporate such semiconductor components or circuit boards. This evaluation board/kit doesnot fall within the scope of the European Union directives regarding electromagnetic compatibility, restricted substances (RoHS), recycling(WEEE), FCC, CE or UL, and therefore may not meet the technical requirements of these directives or other related directives.Should this evaluation board/kit not meet the specifications indicated in the User’s Guide, the board/kit may be returned within 30 days fromthe date of delivery for a full refund. THE FOREGOING WARRANTY IS THE EXCLUSIVE WARRANTY MADE BY SELLER TO BUYERAND IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING ANY WARRANTY OFMERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE.The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user indemnifies TI from all claimsarising from the handling or use of the goods. Due to the open construction of the product, it is the user’s responsibility to take any and allappropriate precautions with regard to electrostatic discharge.EXCEPT TO THE EXTENT OF THE INDEMNITY SET FORTH ABOVE, NEITHER PARTY SHALL BE LIABLE TO THE OTHER FOR ANYINDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES.TI currently deals with a variety of customers for products, and therefore our arrangement with the user is not exclusive.
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This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATION PURPOSESONLY and is not considered by TI to be a finished end-product fit for general consumer use. It generates, uses, and can radiate radiofrequency energy and has not been tested for compliance with the limits of computing devices pursuant to part 15 of FCC rules, which aredesigned to provide reasonable protection against radio frequency interference. Operation of this equipment in other environments maycause interference with radio communications, in which case the user at his own expense will be required to take whatever measures maybe required to correct this interference.
EVM WARNINGS AND RESTRICTIONS
It is important to operate this EVM within the input voltage range of -6 VDC to +6 VDC, and the output voltage range of 0 to 4 VDC.Exceeding the specified input range may cause unexpected operation and/or irreversible damage to the EVM. If there are questionsconcerning the input range, please contact a TI field representative prior to connecting the input power.Applying loads outside of the specified output range may result in unintended operation and/or possible permanent damage to the EVM.Please consult the EVM User's Guide prior to connecting any load to the EVM output. If there is uncertainty as to the load specification,please contact a TI field representative.During normal operation, some circuit components may have case temperatures greater than 70 °C . The EVM is designed to operateproperly with certain components above 70 °C as long as the input and output ranges are maintained. These components include but arenot limited to, switching transistors, inductor, and IC. These types of devices can be identified using the EVM schematic located in the EVMUser's Guide. When placing measurement probes near these devices during operation, please be aware that these devices may be verywarm to the touch.
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